ChTheo/RadioPhotonic_PCB_software
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added tec modulation

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This commit is contained in:
Ayzen
2026-04-27 18:16:39 +03:00
parent d32db245fa
commit d3d48a5255
60 changed files with 13021 additions and 12456 deletions
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180
build/stm32f7xx_hal_pwr.lst
View File

@ -1,4 +1,4 @@
ARM GAS /tmp/ccGtbmtx.s page 1
ARM GAS /tmp/cckhqhEJ.s page 1
1 .cpu cortex-m7
@ -58,7 +58,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */
30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****
31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** @defgroup PWR PWR
ARM GAS /tmp/ccGtbmtx.s page 2
ARM GAS /tmp/cckhqhEJ.s page 2
32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief PWR HAL module driver
@ -118,7 +118,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** To enable access to the RTC Domain and RTC registers, proceed as follows:
87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+) Enable the Power Controller (PWR) APB1 interface clock using the
88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __HAL_RCC_PWR_CLK_ENABLE() macro.
ARM GAS /tmp/ccGtbmtx.s page 3
ARM GAS /tmp/cckhqhEJ.s page 3
89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
@ -178,7 +178,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** {
60 .loc 1 113 1 is_stmt 1 view -0
61 .cfi_startproc
ARM GAS /tmp/ccGtbmtx.s page 4
ARM GAS /tmp/cckhqhEJ.s page 4
62 @ args = 0, pretend = 0, frame = 0
@ -238,7 +238,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
102 .L8:
103 000c 00700040 .word 1073770496
104 .cfi_endproc
ARM GAS /tmp/ccGtbmtx.s page 5
ARM GAS /tmp/cckhqhEJ.s page 5
105 .LFE143:
@ -298,7 +298,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+) Entry:
175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLE
176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** functions with
ARM GAS /tmp/ccGtbmtx.s page 6
ARM GAS /tmp/cckhqhEJ.s page 6
177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
@ -358,7 +358,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** Wakeup event, a tamper event or a time-stamp event, without depending on
232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** an external interrupt (Auto-wakeup mode).
233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****
ARM GAS /tmp/ccGtbmtx.s page 7
ARM GAS /tmp/cckhqhEJ.s page 7
234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
@ -418,7 +418,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
135 0016 5A60 str r2, [r3, #4]
270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_IT();
136 .loc 1 270 3 view .LVU15
ARM GAS /tmp/ccGtbmtx.s page 8
ARM GAS /tmp/cckhqhEJ.s page 8
137 0018 1A68 ldr r2, [r3]
@ -478,7 +478,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
174 0054 4368 ldr r3, [r0, #4]
175 .loc 1 287 5 view .LVU28
176 0056 13F0010F tst r3, #1
ARM GAS /tmp/ccGtbmtx.s page 9
ARM GAS /tmp/cckhqhEJ.s page 9
177 005a 04D0 beq .L13
@ -538,7 +538,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
217 @ args = 0, pretend = 0, frame = 0
218 @ frame_needed = 0, uses_anonymous_args = 0
219 @ link register save eliminated.
ARM GAS /tmp/ccGtbmtx.s page 10
ARM GAS /tmp/cckhqhEJ.s page 10
304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Enable the power voltage detector */
@ -598,7 +598,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
264 .global HAL_PWR_EnableWakeUpPin
265 .syntax unified
266 .thumb
ARM GAS /tmp/ccGtbmtx.s page 11
ARM GAS /tmp/cckhqhEJ.s page 11
267 .thumb_func
@ -658,7 +658,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
293 .L25:
294 001a 00BF .align 2
295 .L24:
ARM GAS /tmp/ccGtbmtx.s page 12
ARM GAS /tmp/cckhqhEJ.s page 12
296 001c 00700040 .word 1073770496
@ -718,7 +718,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
334 .thumb
335 .thumb_func
337 HAL_PWR_EnterSLEEPMode:
ARM GAS /tmp/ccGtbmtx.s page 13
ARM GAS /tmp/cckhqhEJ.s page 13
338 .LVL4:
@ -778,7 +778,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h
3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file
ARM GAS /tmp/ccGtbmtx.s page 14
ARM GAS /tmp/cckhqhEJ.s page 14
4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4
@ -838,7 +838,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK
59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak))
60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
ARM GAS /tmp/ccGtbmtx.s page 15
ARM GAS /tmp/cckhqhEJ.s page 15
61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED
@ -898,7 +898,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
116:Drivers/CMSIS/Include/cmsis_gcc.h ****
117:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS /tmp/ccGtbmtx.s page 16
ARM GAS /tmp/cckhqhEJ.s page 16
118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */
@ -958,7 +958,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
172:Drivers/CMSIS/Include/cmsis_gcc.h **** }
173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
174:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS /tmp/ccGtbmtx.s page 17
ARM GAS /tmp/cckhqhEJ.s page 17
175:Drivers/CMSIS/Include/cmsis_gcc.h ****
@ -1018,7 +1018,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register
230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register.
231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value
ARM GAS /tmp/ccGtbmtx.s page 18
ARM GAS /tmp/cckhqhEJ.s page 18
232:Drivers/CMSIS/Include/cmsis_gcc.h **** */
@ -1078,7 +1078,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set
288:Drivers/CMSIS/Include/cmsis_gcc.h **** */
ARM GAS /tmp/ccGtbmtx.s page 19
ARM GAS /tmp/cckhqhEJ.s page 19
289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
@ -1138,7 +1138,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
344:Drivers/CMSIS/Include/cmsis_gcc.h **** {
345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
ARM GAS /tmp/ccGtbmtx.s page 20
ARM GAS /tmp/cckhqhEJ.s page 20
346:Drivers/CMSIS/Include/cmsis_gcc.h **** }
@ -1198,7 +1198,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
400:Drivers/CMSIS/Include/cmsis_gcc.h ****
401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
ARM GAS /tmp/ccGtbmtx.s page 21
ARM GAS /tmp/cckhqhEJ.s page 21
403:Drivers/CMSIS/Include/cmsis_gcc.h **** }
@ -1258,7 +1258,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority
458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register.
459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value
ARM GAS /tmp/ccGtbmtx.s page 22
ARM GAS /tmp/cckhqhEJ.s page 22
460:Drivers/CMSIS/Include/cmsis_gcc.h **** */
@ -1318,7 +1318,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
515:Drivers/CMSIS/Include/cmsis_gcc.h **** */
516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
ARM GAS /tmp/ccGtbmtx.s page 23
ARM GAS /tmp/cckhqhEJ.s page 23
517:Drivers/CMSIS/Include/cmsis_gcc.h **** {
@ -1378,7 +1378,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
572:Drivers/CMSIS/Include/cmsis_gcc.h **** }
573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
ARM GAS /tmp/ccGtbmtx.s page 24
ARM GAS /tmp/cckhqhEJ.s page 24
574:Drivers/CMSIS/Include/cmsis_gcc.h ****
@ -1438,7 +1438,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
628:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit
630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
ARM GAS /tmp/ccGtbmtx.s page 25
ARM GAS /tmp/cckhqhEJ.s page 25
631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure
@ -1498,7 +1498,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) );
ARM GAS /tmp/ccGtbmtx.s page 26
ARM GAS /tmp/cckhqhEJ.s page 26
688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
@ -1558,7 +1558,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
742:Drivers/CMSIS/Include/cmsis_gcc.h ****
743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set
ARM GAS /tmp/ccGtbmtx.s page 27
ARM GAS /tmp/cckhqhEJ.s page 27
745:Drivers/CMSIS/Include/cmsis_gcc.h **** */
@ -1618,7 +1618,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr);
801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
ARM GAS /tmp/ccGtbmtx.s page 28
ARM GAS /tmp/cckhqhEJ.s page 28
802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
@ -1678,7 +1678,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
856:Drivers/CMSIS/Include/cmsis_gcc.h **** */
857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev")
858:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS /tmp/ccGtbmtx.s page 29
ARM GAS /tmp/cckhqhEJ.s page 29
859:Drivers/CMSIS/Include/cmsis_gcc.h ****
@ -1738,7 +1738,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
384 0012 0129 cmp r1, #1
385 0014 03D0 beq .L32
404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** {
ARM GAS /tmp/ccGtbmtx.s page 30
ARM GAS /tmp/cckhqhEJ.s page 30
405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Request Wait For Interrupt */
@ -1798,7 +1798,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief Enters Stop mode.
419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @note In Stop mode, all I/O pins keep the same state as in Run mode.
ARM GAS /tmp/ccGtbmtx.s page 31
ARM GAS /tmp/cckhqhEJ.s page 31
420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
@ -1858,7 +1858,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** PWR->CR1 = tmpreg;
450 .loc 1 453 3 is_stmt 1 view .LVU79
451 .loc 1 453 12 is_stmt 0 view .LVU80
ARM GAS /tmp/ccGtbmtx.s page 32
ARM GAS /tmp/cckhqhEJ.s page 32
452 000a 1360 str r3, [r2]
@ -1918,7 +1918,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
493 0020 08D0 beq .L38
464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** {
465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Request Wait For Interrupt */
ARM GAS /tmp/ccGtbmtx.s page 33
ARM GAS /tmp/cckhqhEJ.s page 33
466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __WFI();
@ -1978,7 +1978,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
536 .section .text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits
537 .align 1
538 .global HAL_PWR_EnterSTANDBYMode
ARM GAS /tmp/ccGtbmtx.s page 34
ARM GAS /tmp/cckhqhEJ.s page 34
539 .syntax unified
@ -2038,7 +2038,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** }
569 .loc 1 503 1 is_stmt 0 view .LVU108
570 .thumb
ARM GAS /tmp/ccGtbmtx.s page 35
ARM GAS /tmp/cckhqhEJ.s page 35
571 .syntax unified
@ -2098,7 +2098,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
598 .LFE153:
600 .section .text.HAL_PWR_PVD_IRQHandler,"ax",%progbits
601 .align 1
ARM GAS /tmp/ccGtbmtx.s page 36
ARM GAS /tmp/cckhqhEJ.s page 36
602 .global HAL_PWR_PVD_IRQHandler
@ -2158,7 +2158,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
650 .thumb_func
652 HAL_PWR_EnableSleepOnExit:
653 .LFB154:
ARM GAS /tmp/ccGtbmtx.s page 37
ARM GAS /tmp/cckhqhEJ.s page 37
533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****
@ -2218,7 +2218,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex System Control Register */
557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
687 .loc 1 557 3 view .LVU123
ARM GAS /tmp/ccGtbmtx.s page 38
ARM GAS /tmp/cckhqhEJ.s page 38
688 0000 024A ldr r2, .L55
@ -2278,7 +2278,7 @@ ARM GAS /tmp/ccGtbmtx.s page 1
732 .syntax unified
733 .thumb
734 .thumb_func
ARM GAS /tmp/ccGtbmtx.s page 39
ARM GAS /tmp/cckhqhEJ.s page 39
736 HAL_PWR_DisableSEVOnPend:
@ -2320,60 +2320,60 @@ ARM GAS /tmp/ccGtbmtx.s page 1
761 .file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
762 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h"
763 .file 7 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
ARM GAS /tmp/ccGtbmtx.s page 40
ARM GAS /tmp/cckhqhEJ.s page 40
DEFINED SYMBOLS
*ABS*:00000000 stm32f7xx_hal_pwr.c
/tmp/ccGtbmtx.s:20 .text.HAL_PWR_DeInit:00000000 $t
/tmp/ccGtbmtx.s:26 .text.HAL_PWR_DeInit:00000000 HAL_PWR_DeInit
/tmp/ccGtbmtx.s:47 .text.HAL_PWR_DeInit:00000014 $d
/tmp/ccGtbmtx.s:52 .text.HAL_PWR_EnableBkUpAccess:00000000 $t
/tmp/ccGtbmtx.s:58 .text.HAL_PWR_EnableBkUpAccess:00000000 HAL_PWR_EnableBkUpAccess
/tmp/ccGtbmtx.s:75 .text.HAL_PWR_EnableBkUpAccess:0000000c $d
/tmp/ccGtbmtx.s:80 .text.HAL_PWR_DisableBkUpAccess:00000000 $t
/tmp/ccGtbmtx.s:86 .text.HAL_PWR_DisableBkUpAccess:00000000 HAL_PWR_DisableBkUpAccess
/tmp/ccGtbmtx.s:103 .text.HAL_PWR_DisableBkUpAccess:0000000c $d
/tmp/ccGtbmtx.s:108 .text.HAL_PWR_ConfigPVD:00000000 $t
/tmp/ccGtbmtx.s:114 .text.HAL_PWR_ConfigPVD:00000000 HAL_PWR_ConfigPVD
/tmp/ccGtbmtx.s:201 .text.HAL_PWR_ConfigPVD:0000007c $d
/tmp/ccGtbmtx.s:207 .text.HAL_PWR_EnablePVD:00000000 $t
/tmp/ccGtbmtx.s:213 .text.HAL_PWR_EnablePVD:00000000 HAL_PWR_EnablePVD
/tmp/ccGtbmtx.s:230 .text.HAL_PWR_EnablePVD:0000000c $d
/tmp/ccGtbmtx.s:235 .text.HAL_PWR_DisablePVD:00000000 $t
/tmp/ccGtbmtx.s:241 .text.HAL_PWR_DisablePVD:00000000 HAL_PWR_DisablePVD
/tmp/ccGtbmtx.s:258 .text.HAL_PWR_DisablePVD:0000000c $d
/tmp/ccGtbmtx.s:263 .text.HAL_PWR_EnableWakeUpPin:00000000 $t
/tmp/ccGtbmtx.s:269 .text.HAL_PWR_EnableWakeUpPin:00000000 HAL_PWR_EnableWakeUpPin
/tmp/ccGtbmtx.s:296 .text.HAL_PWR_EnableWakeUpPin:0000001c $d
/tmp/ccGtbmtx.s:301 .text.HAL_PWR_DisableWakeUpPin:00000000 $t
/tmp/ccGtbmtx.s:307 .text.HAL_PWR_DisableWakeUpPin:00000000 HAL_PWR_DisableWakeUpPin
/tmp/ccGtbmtx.s:326 .text.HAL_PWR_DisableWakeUpPin:0000000c $d
/tmp/ccGtbmtx.s:331 .text.HAL_PWR_EnterSLEEPMode:00000000 $t
/tmp/ccGtbmtx.s:337 .text.HAL_PWR_EnterSLEEPMode:00000000 HAL_PWR_EnterSLEEPMode
/tmp/ccGtbmtx.s:415 .text.HAL_PWR_EnterSLEEPMode:00000024 $d
/tmp/ccGtbmtx.s:420 .text.HAL_PWR_EnterSTOPMode:00000000 $t
/tmp/ccGtbmtx.s:426 .text.HAL_PWR_EnterSTOPMode:00000000 HAL_PWR_EnterSTOPMode
/tmp/ccGtbmtx.s:531 .text.HAL_PWR_EnterSTOPMode:00000038 $d
/tmp/ccGtbmtx.s:537 .text.HAL_PWR_EnterSTANDBYMode:00000000 $t
/tmp/ccGtbmtx.s:543 .text.HAL_PWR_EnterSTANDBYMode:00000000 HAL_PWR_EnterSTANDBYMode
/tmp/ccGtbmtx.s:576 .text.HAL_PWR_EnterSTANDBYMode:00000018 $d
/tmp/ccGtbmtx.s:582 .text.HAL_PWR_PVDCallback:00000000 $t
/tmp/ccGtbmtx.s:588 .text.HAL_PWR_PVDCallback:00000000 HAL_PWR_PVDCallback
/tmp/ccGtbmtx.s:601 .text.HAL_PWR_PVD_IRQHandler:00000000 $t
/tmp/ccGtbmtx.s:607 .text.HAL_PWR_PVD_IRQHandler:00000000 HAL_PWR_PVD_IRQHandler
/tmp/ccGtbmtx.s:641 .text.HAL_PWR_PVD_IRQHandler:0000001c $d
/tmp/ccGtbmtx.s:646 .text.HAL_PWR_EnableSleepOnExit:00000000 $t
/tmp/ccGtbmtx.s:652 .text.HAL_PWR_EnableSleepOnExit:00000000 HAL_PWR_EnableSleepOnExit
/tmp/ccGtbmtx.s:669 .text.HAL_PWR_EnableSleepOnExit:0000000c $d
/tmp/ccGtbmtx.s:674 .text.HAL_PWR_DisableSleepOnExit:00000000 $t
/tmp/ccGtbmtx.s:680 .text.HAL_PWR_DisableSleepOnExit:00000000 HAL_PWR_DisableSleepOnExit
/tmp/ccGtbmtx.s:697 .text.HAL_PWR_DisableSleepOnExit:0000000c $d
/tmp/ccGtbmtx.s:702 .text.HAL_PWR_EnableSEVOnPend:00000000 $t
/tmp/ccGtbmtx.s:708 .text.HAL_PWR_EnableSEVOnPend:00000000 HAL_PWR_EnableSEVOnPend
/tmp/ccGtbmtx.s:725 .text.HAL_PWR_EnableSEVOnPend:0000000c $d
/tmp/ccGtbmtx.s:730 .text.HAL_PWR_DisableSEVOnPend:00000000 $t
/tmp/ccGtbmtx.s:736 .text.HAL_PWR_DisableSEVOnPend:00000000 HAL_PWR_DisableSEVOnPend
/tmp/ccGtbmtx.s:753 .text.HAL_PWR_DisableSEVOnPend:0000000c $d
/tmp/cckhqhEJ.s:20 .text.HAL_PWR_DeInit:00000000 $t
/tmp/cckhqhEJ.s:26 .text.HAL_PWR_DeInit:00000000 HAL_PWR_DeInit
/tmp/cckhqhEJ.s:47 .text.HAL_PWR_DeInit:00000014 $d
/tmp/cckhqhEJ.s:52 .text.HAL_PWR_EnableBkUpAccess:00000000 $t
/tmp/cckhqhEJ.s:58 .text.HAL_PWR_EnableBkUpAccess:00000000 HAL_PWR_EnableBkUpAccess
/tmp/cckhqhEJ.s:75 .text.HAL_PWR_EnableBkUpAccess:0000000c $d
/tmp/cckhqhEJ.s:80 .text.HAL_PWR_DisableBkUpAccess:00000000 $t
/tmp/cckhqhEJ.s:86 .text.HAL_PWR_DisableBkUpAccess:00000000 HAL_PWR_DisableBkUpAccess
/tmp/cckhqhEJ.s:103 .text.HAL_PWR_DisableBkUpAccess:0000000c $d
/tmp/cckhqhEJ.s:108 .text.HAL_PWR_ConfigPVD:00000000 $t
/tmp/cckhqhEJ.s:114 .text.HAL_PWR_ConfigPVD:00000000 HAL_PWR_ConfigPVD
/tmp/cckhqhEJ.s:201 .text.HAL_PWR_ConfigPVD:0000007c $d
/tmp/cckhqhEJ.s:207 .text.HAL_PWR_EnablePVD:00000000 $t
/tmp/cckhqhEJ.s:213 .text.HAL_PWR_EnablePVD:00000000 HAL_PWR_EnablePVD
/tmp/cckhqhEJ.s:230 .text.HAL_PWR_EnablePVD:0000000c $d
/tmp/cckhqhEJ.s:235 .text.HAL_PWR_DisablePVD:00000000 $t
/tmp/cckhqhEJ.s:241 .text.HAL_PWR_DisablePVD:00000000 HAL_PWR_DisablePVD
/tmp/cckhqhEJ.s:258 .text.HAL_PWR_DisablePVD:0000000c $d
/tmp/cckhqhEJ.s:263 .text.HAL_PWR_EnableWakeUpPin:00000000 $t
/tmp/cckhqhEJ.s:269 .text.HAL_PWR_EnableWakeUpPin:00000000 HAL_PWR_EnableWakeUpPin
/tmp/cckhqhEJ.s:296 .text.HAL_PWR_EnableWakeUpPin:0000001c $d
/tmp/cckhqhEJ.s:301 .text.HAL_PWR_DisableWakeUpPin:00000000 $t
/tmp/cckhqhEJ.s:307 .text.HAL_PWR_DisableWakeUpPin:00000000 HAL_PWR_DisableWakeUpPin
/tmp/cckhqhEJ.s:326 .text.HAL_PWR_DisableWakeUpPin:0000000c $d
/tmp/cckhqhEJ.s:331 .text.HAL_PWR_EnterSLEEPMode:00000000 $t
/tmp/cckhqhEJ.s:337 .text.HAL_PWR_EnterSLEEPMode:00000000 HAL_PWR_EnterSLEEPMode
/tmp/cckhqhEJ.s:415 .text.HAL_PWR_EnterSLEEPMode:00000024 $d
/tmp/cckhqhEJ.s:420 .text.HAL_PWR_EnterSTOPMode:00000000 $t
/tmp/cckhqhEJ.s:426 .text.HAL_PWR_EnterSTOPMode:00000000 HAL_PWR_EnterSTOPMode
/tmp/cckhqhEJ.s:531 .text.HAL_PWR_EnterSTOPMode:00000038 $d
/tmp/cckhqhEJ.s:537 .text.HAL_PWR_EnterSTANDBYMode:00000000 $t
/tmp/cckhqhEJ.s:543 .text.HAL_PWR_EnterSTANDBYMode:00000000 HAL_PWR_EnterSTANDBYMode
/tmp/cckhqhEJ.s:576 .text.HAL_PWR_EnterSTANDBYMode:00000018 $d
/tmp/cckhqhEJ.s:582 .text.HAL_PWR_PVDCallback:00000000 $t
/tmp/cckhqhEJ.s:588 .text.HAL_PWR_PVDCallback:00000000 HAL_PWR_PVDCallback
/tmp/cckhqhEJ.s:601 .text.HAL_PWR_PVD_IRQHandler:00000000 $t
/tmp/cckhqhEJ.s:607 .text.HAL_PWR_PVD_IRQHandler:00000000 HAL_PWR_PVD_IRQHandler
/tmp/cckhqhEJ.s:641 .text.HAL_PWR_PVD_IRQHandler:0000001c $d
/tmp/cckhqhEJ.s:646 .text.HAL_PWR_EnableSleepOnExit:00000000 $t
/tmp/cckhqhEJ.s:652 .text.HAL_PWR_EnableSleepOnExit:00000000 HAL_PWR_EnableSleepOnExit
/tmp/cckhqhEJ.s:669 .text.HAL_PWR_EnableSleepOnExit:0000000c $d
/tmp/cckhqhEJ.s:674 .text.HAL_PWR_DisableSleepOnExit:00000000 $t
/tmp/cckhqhEJ.s:680 .text.HAL_PWR_DisableSleepOnExit:00000000 HAL_PWR_DisableSleepOnExit
/tmp/cckhqhEJ.s:697 .text.HAL_PWR_DisableSleepOnExit:0000000c $d
/tmp/cckhqhEJ.s:702 .text.HAL_PWR_EnableSEVOnPend:00000000 $t
/tmp/cckhqhEJ.s:708 .text.HAL_PWR_EnableSEVOnPend:00000000 HAL_PWR_EnableSEVOnPend
/tmp/cckhqhEJ.s:725 .text.HAL_PWR_EnableSEVOnPend:0000000c $d
/tmp/cckhqhEJ.s:730 .text.HAL_PWR_DisableSEVOnPend:00000000 $t
/tmp/cckhqhEJ.s:736 .text.HAL_PWR_DisableSEVOnPend:00000000 HAL_PWR_DisableSEVOnPend
/tmp/cckhqhEJ.s:753 .text.HAL_PWR_DisableSEVOnPend:0000000c $d
NO UNDEFINED SYMBOLS