ChTheo/RadioPhotonic_PCB_software
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This commit is contained in:
feda
2025-03-03 16:03:02 +03:00
parent 2d2912a771
commit d0637bb5e6
97 changed files with 15957 additions and 15422 deletions
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308
build/stm32f7xx_hal_cortex.lst
View File

@ -1,4 +1,4 @@
ARM GAS /tmp/ccs1e2mJ.s page 1
ARM GAS /tmp/ccvevkMB.s page 1
1 .cpu cortex-m7
@ -58,7 +58,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****
29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** The pending IRQ priority will be managed only by the sub priority.
ARM GAS /tmp/ccs1e2mJ.s page 2
ARM GAS /tmp/ccvevkMB.s page 2
31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****
@ -118,7 +118,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @{
86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */
87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****
ARM GAS /tmp/ccs1e2mJ.s page 3
ARM GAS /tmp/ccvevkMB.s page 3
88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** @defgroup CORTEX CORTEX
@ -178,7 +178,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
29 .loc 1 143 1 view -0
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30 .cfi_startproc
@ -238,7 +238,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
41:Drivers/CMSIS/Include/core_cm7.h **** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42:Drivers/CMSIS/Include/core_cm7.h **** CMSIS violates the following MISRA-C:2004 rules:
43:Drivers/CMSIS/Include/core_cm7.h ****
ARM GAS /tmp/ccs1e2mJ.s page 5
ARM GAS /tmp/ccvevkMB.s page 5
44:Drivers/CMSIS/Include/core_cm7.h **** \li Required Rule 8.5, object/function definition in header file.<br>
@ -298,7 +298,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
98:Drivers/CMSIS/Include/core_cm7.h **** #endif
99:Drivers/CMSIS/Include/core_cm7.h ****
100:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __GNUC__ )
ARM GAS /tmp/ccs1e2mJ.s page 6
ARM GAS /tmp/ccvevkMB.s page 6
101:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__)
@ -358,7 +358,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
155:Drivers/CMSIS/Include/core_cm7.h **** #endif
156:Drivers/CMSIS/Include/core_cm7.h **** #else
157:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U
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158:Drivers/CMSIS/Include/core_cm7.h **** #endif
@ -418,7 +418,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
212:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __NVIC_PRIO_BITS
213:Drivers/CMSIS/Include/core_cm7.h **** #define __NVIC_PRIO_BITS 3U
214:Drivers/CMSIS/Include/core_cm7.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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215:Drivers/CMSIS/Include/core_cm7.h **** #endif
@ -478,7 +478,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
269:Drivers/CMSIS/Include/core_cm7.h **** */
270:Drivers/CMSIS/Include/core_cm7.h ****
271:Drivers/CMSIS/Include/core_cm7.h **** /**
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272:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Application Program Status Register (APSR).
@ -538,7 +538,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
326:Drivers/CMSIS/Include/core_cm7.h ****
327:Drivers/CMSIS/Include/core_cm7.h ****
328:Drivers/CMSIS/Include/core_cm7.h **** /**
ARM GAS /tmp/ccs1e2mJ.s page 10
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329:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
@ -598,7 +598,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
383:Drivers/CMSIS/Include/core_cm7.h **** /**
384:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Control Registers (CONTROL).
385:Drivers/CMSIS/Include/core_cm7.h **** */
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386:Drivers/CMSIS/Include/core_cm7.h **** typedef union
@ -658,7 +658,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
440:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: I
441:Drivers/CMSIS/Include/core_cm7.h ****
442:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_NVIC */
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443:Drivers/CMSIS/Include/core_cm7.h ****
@ -718,7 +718,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
497:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by
498:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by
499:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED7[6U];
ARM GAS /tmp/ccs1e2mJ.s page 13
ARM GAS /tmp/ccvevkMB.s page 13
500:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memo
@ -778,7 +778,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
554:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB
555:Drivers/CMSIS/Include/core_cm7.h ****
556:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Vector Table Offset Register Definitions */
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557:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB
@ -838,7 +838,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
611:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB
612:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB
613:Drivers/CMSIS/Include/core_cm7.h ****
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614:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB
@ -898,7 +898,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
668:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB
669:Drivers/CMSIS/Include/core_cm7.h ****
670:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB
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671:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB
@ -958,7 +958,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
725:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB
726:Drivers/CMSIS/Include/core_cm7.h ****
727:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB
ARM GAS /tmp/ccs1e2mJ.s page 17
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728:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB
@ -1018,7 +1018,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
782:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size ID Register Definitions */
783:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Pos 31U /*!< SCB
784:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB
ARM GAS /tmp/ccs1e2mJ.s page 18
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785:Drivers/CMSIS/Include/core_cm7.h ****
@ -1078,7 +1078,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
839:Drivers/CMSIS/Include/core_cm7.h ****
840:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB
841:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB
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842:Drivers/CMSIS/Include/core_cm7.h ****
@ -1138,7 +1138,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
896:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB
897:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB
898:Drivers/CMSIS/Include/core_cm7.h ****
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899:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB
@ -1198,7 +1198,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
953:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick)
954:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Timer Registers.
955:Drivers/CMSIS/Include/core_cm7.h **** @{
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956:Drivers/CMSIS/Include/core_cm7.h **** */
@ -1258,7 +1258,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1010:Drivers/CMSIS/Include/core_cm7.h **** /**
1011:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
1012:Drivers/CMSIS/Include/core_cm7.h **** */
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1013:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
@ -1318,7 +1318,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1067:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM
1068:Drivers/CMSIS/Include/core_cm7.h ****
1069:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Pos 3U /*!< ITM
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1070:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM
@ -1378,7 +1378,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1124:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Registe
1125:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register
1126:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
ARM GAS /tmp/ccs1e2mJ.s page 24
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1127:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
@ -1438,7 +1438,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1181:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTR
1182:Drivers/CMSIS/Include/core_cm7.h ****
1183:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTR
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1184:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTR
@ -1498,7 +1498,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1238:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUN
1239:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUN
1240:Drivers/CMSIS/Include/core_cm7.h ****
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1241:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUN
@ -1558,7 +1558,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1295:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACP
1296:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACP
1297:Drivers/CMSIS/Include/core_cm7.h ****
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1298:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Selected Pin Protocol Register Definitions */
@ -1618,7 +1618,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1352:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITA
1353:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITA
1354:Drivers/CMSIS/Include/core_cm7.h ****
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1355:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */
@ -1678,7 +1678,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1409:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEV
1410:Drivers/CMSIS/Include/core_cm7.h ****
1411:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEV
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1412:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEV
@ -1738,7 +1738,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1466:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Pos 0U /*!< MPU
1467:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU
1468:Drivers/CMSIS/Include/core_cm7.h ****
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1469:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Base Address Register Definitions */
@ -1798,7 +1798,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1523:Drivers/CMSIS/Include/core_cm7.h **** */
1524:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
1525:Drivers/CMSIS/Include/core_cm7.h **** {
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1526:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U];
@ -1858,7 +1858,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1580:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 0 Definitions */
1581:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR
1582:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR
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1583:Drivers/CMSIS/Include/core_cm7.h ****
@ -1918,7 +1918,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1637:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Registe
1638:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Cont
1639:Drivers/CMSIS/Include/core_cm7.h **** } CoreDebug_Type;
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1640:Drivers/CMSIS/Include/core_cm7.h ****
@ -1978,7 +1978,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1694:Drivers/CMSIS/Include/core_cm7.h ****
1695:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< Core
1696:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< Core
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1697:Drivers/CMSIS/Include/core_cm7.h ****
@ -2038,7 +2038,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1751:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_core_bitfield */
1752:Drivers/CMSIS/Include/core_cm7.h ****
1753:Drivers/CMSIS/Include/core_cm7.h ****
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1754:Drivers/CMSIS/Include/core_cm7.h **** /**
@ -2098,7 +2098,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1808:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_Core_FunctionInterface
1809:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1810:Drivers/CMSIS/Include/core_cm7.h **** \brief Functions that manage interrupts and exceptions via the NVIC.
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1811:Drivers/CMSIS/Include/core_cm7.h **** @{
@ -2158,7 +2158,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1865:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
39 .loc 2 1865 22 view .LVU3
40 .LBB39:
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1866:Drivers/CMSIS/Include/core_cm7.h **** {
@ -2218,7 +2218,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
82 0020 0000FA05 .word 100270080
83 .cfi_endproc
84 .LFE141:
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86 .section .text.HAL_NVIC_SetPriority,"ax",%progbits
@ -2278,7 +2278,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1881:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the priority grouping field from the NVIC Interrupt Controller.
1882:Drivers/CMSIS/Include/core_cm7.h **** \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1883:Drivers/CMSIS/Include/core_cm7.h **** */
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1884:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
@ -2338,7 +2338,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1921:Drivers/CMSIS/Include/core_cm7.h **** return(0U);
1922:Drivers/CMSIS/Include/core_cm7.h **** }
1923:Drivers/CMSIS/Include/core_cm7.h **** }
ARM GAS /tmp/ccs1e2mJ.s page 40
ARM GAS /tmp/ccvevkMB.s page 40
1924:Drivers/CMSIS/Include/core_cm7.h ****
@ -2398,7 +2398,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1978:Drivers/CMSIS/Include/core_cm7.h ****
1979:Drivers/CMSIS/Include/core_cm7.h **** /**
1980:Drivers/CMSIS/Include/core_cm7.h **** \brief Clear Pending Interrupt
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1981:Drivers/CMSIS/Include/core_cm7.h **** \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
@ -2458,7 +2458,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
2035:Drivers/CMSIS/Include/core_cm7.h ****
2036:Drivers/CMSIS/Include/core_cm7.h ****
2037:Drivers/CMSIS/Include/core_cm7.h **** /**
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ARM GAS /tmp/ccvevkMB.s page 42
2038:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Priority
@ -2518,7 +2518,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
141 .loc 2 2078 3 is_stmt 1 view .LVU39
142 .loc 2 2078 44 is_stmt 0 view .LVU40
143 0018 03F1040E add lr, r3, #4
ARM GAS /tmp/ccs1e2mJ.s page 43
ARM GAS /tmp/ccvevkMB.s page 43
144 .loc 2 2078 109 view .LVU41
@ -2578,7 +2578,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
186 0042 C9B2 uxtb r1, r1
2028:Drivers/CMSIS/Include/core_cm7.h **** }
187 .loc 2 2028 47 view .LVU57
ARM GAS /tmp/ccs1e2mJ.s page 44
ARM GAS /tmp/ccvevkMB.s page 44
188 0044 074B ldr r3, .L10+4
@ -2638,7 +2638,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
231 .L11:
232 005e 00BF .align 2
233 .L10:
ARM GAS /tmp/ccs1e2mJ.s page 45
ARM GAS /tmp/ccvevkMB.s page 45
234 0060 00ED00E0 .word -536810240
@ -2698,7 +2698,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
268 .loc 2 1900 5 is_stmt 1 view .LVU77
1900:Drivers/CMSIS/Include/core_cm7.h **** }
269 .loc 2 1900 81 is_stmt 0 view .LVU78
ARM GAS /tmp/ccs1e2mJ.s page 46
ARM GAS /tmp/ccvevkMB.s page 46
270 0004 00F01F02 and r2, r0, #31
@ -2758,7 +2758,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
309 .loc 1 205 3 view .LVU85
206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****
207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Disable interrupt */
ARM GAS /tmp/ccs1e2mJ.s page 47
ARM GAS /tmp/ccvevkMB.s page 47
208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** NVIC_DisableIRQ(IRQn);
@ -2818,7 +2818,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
17:Drivers/CMSIS/Include/cmsis_gcc.h **** *
18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software
19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
ARM GAS /tmp/ccs1e2mJ.s page 48
ARM GAS /tmp/ccvevkMB.s page 48
20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -2878,7 +2878,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; };
75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
ARM GAS /tmp/ccs1e2mJ.s page 49
ARM GAS /tmp/ccvevkMB.s page 49
77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
@ -2938,7 +2938,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory");
132:Drivers/CMSIS/Include/cmsis_gcc.h **** }
133:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS /tmp/ccs1e2mJ.s page 50
ARM GAS /tmp/ccvevkMB.s page 50
134:Drivers/CMSIS/Include/cmsis_gcc.h ****
@ -2998,7 +2998,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
188:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure)
190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state.
ARM GAS /tmp/ccs1e2mJ.s page 51
ARM GAS /tmp/ccvevkMB.s page 51
191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set
@ -3058,7 +3058,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value
246:Drivers/CMSIS/Include/cmsis_gcc.h **** */
247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
ARM GAS /tmp/ccs1e2mJ.s page 52
ARM GAS /tmp/ccvevkMB.s page 52
248:Drivers/CMSIS/Include/cmsis_gcc.h **** {
@ -3118,7 +3118,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
302:Drivers/CMSIS/Include/cmsis_gcc.h **** {
303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
304:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS /tmp/ccs1e2mJ.s page 53
ARM GAS /tmp/ccvevkMB.s page 53
305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) );
@ -3178,7 +3178,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
359:Drivers/CMSIS/Include/cmsis_gcc.h ****
360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
ARM GAS /tmp/ccs1e2mJ.s page 54
ARM GAS /tmp/ccvevkMB.s page 54
362:Drivers/CMSIS/Include/cmsis_gcc.h **** }
@ -3238,7 +3238,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
416:Drivers/CMSIS/Include/cmsis_gcc.h ****
417:Drivers/CMSIS/Include/cmsis_gcc.h ****
418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
ARM GAS /tmp/ccs1e2mJ.s page 55
ARM GAS /tmp/ccvevkMB.s page 55
419:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
@ -3298,7 +3298,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state.
474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value
475:Drivers/CMSIS/Include/cmsis_gcc.h **** */
ARM GAS /tmp/ccs1e2mJ.s page 56
ARM GAS /tmp/ccvevkMB.s page 56
476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
@ -3358,7 +3358,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
530:Drivers/CMSIS/Include/cmsis_gcc.h ****
531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
ARM GAS /tmp/ccs1e2mJ.s page 57
ARM GAS /tmp/ccvevkMB.s page 57
533:Drivers/CMSIS/Include/cmsis_gcc.h **** }
@ -3418,7 +3418,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
588:Drivers/CMSIS/Include/cmsis_gcc.h ****
589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
ARM GAS /tmp/ccs1e2mJ.s page 58
ARM GAS /tmp/ccvevkMB.s page 58
590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value
@ -3478,7 +3478,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
646:Drivers/CMSIS/Include/cmsis_gcc.h **** }
ARM GAS /tmp/ccs1e2mJ.s page 59
ARM GAS /tmp/ccvevkMB.s page 59
647:Drivers/CMSIS/Include/cmsis_gcc.h ****
@ -3538,7 +3538,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
701:Drivers/CMSIS/Include/cmsis_gcc.h **** */
702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
703:Drivers/CMSIS/Include/cmsis_gcc.h **** {
ARM GAS /tmp/ccs1e2mJ.s page 60
ARM GAS /tmp/ccvevkMB.s page 60
704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
@ -3598,7 +3598,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
759:Drivers/CMSIS/Include/cmsis_gcc.h ****
760:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS /tmp/ccs1e2mJ.s page 61
ARM GAS /tmp/ccvevkMB.s page 61
761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
@ -3658,7 +3658,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions
816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
817:Drivers/CMSIS/Include/cmsis_gcc.h **** */
ARM GAS /tmp/ccs1e2mJ.s page 62
ARM GAS /tmp/ccvevkMB.s page 62
818:Drivers/CMSIS/Include/cmsis_gcc.h ****
@ -3718,7 +3718,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
872:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier
874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier.
ARM GAS /tmp/ccs1e2mJ.s page 63
ARM GAS /tmp/ccvevkMB.s page 63
875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete.
@ -3778,7 +3778,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
382 .fpu fpv5-d16
384 HAL_NVIC_SystemReset:
385 .LFB145:
ARM GAS /tmp/ccs1e2mJ.s page 64
ARM GAS /tmp/ccvevkMB.s page 64
210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****
@ -3838,7 +3838,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
2119:Drivers/CMSIS/Include/core_cm7.h **** \param [in] vector Address of interrupt handler function
2120:Drivers/CMSIS/Include/core_cm7.h **** */
2121:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
ARM GAS /tmp/ccs1e2mJ.s page 65
ARM GAS /tmp/ccvevkMB.s page 65
2122:Drivers/CMSIS/Include/core_cm7.h **** {
@ -3898,7 +3898,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
2151:Drivers/CMSIS/Include/core_cm7.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
417 .loc 2 2151 17 view .LVU113
418 000c 044B ldr r3, .L22+4
ARM GAS /tmp/ccs1e2mJ.s page 66
ARM GAS /tmp/ccvevkMB.s page 66
419 000e 1343 orrs r3, r3, r2
@ -3958,7 +3958,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
466 .LVL32:
467 .LFB146:
219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
ARM GAS /tmp/ccs1e2mJ.s page 67
ARM GAS /tmp/ccvevkMB.s page 67
220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****
@ -4018,7 +4018,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
2194:Drivers/CMSIS/Include/core_cm7.h **** {
2195:Drivers/CMSIS/Include/core_cm7.h **** return 2U; /* Double + Single precision FPU */
2196:Drivers/CMSIS/Include/core_cm7.h **** }
ARM GAS /tmp/ccs1e2mJ.s page 68
ARM GAS /tmp/ccvevkMB.s page 68
2197:Drivers/CMSIS/Include/core_cm7.h **** else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
@ -4078,7 +4078,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
2251:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
2252:Drivers/CMSIS/Include/core_cm7.h **** __ISB();
2253:Drivers/CMSIS/Include/core_cm7.h **** SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
ARM GAS /tmp/ccs1e2mJ.s page 69
ARM GAS /tmp/ccvevkMB.s page 69
2254:Drivers/CMSIS/Include/core_cm7.h **** SCB->ICIALLU = 0UL; /* invalidate I-Cache */
@ -4138,7 +4138,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
2308:Drivers/CMSIS/Include/core_cm7.h ****
2309:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
2310:Drivers/CMSIS/Include/core_cm7.h **** __ISB();
ARM GAS /tmp/ccs1e2mJ.s page 70
ARM GAS /tmp/ccvevkMB.s page 70
2311:Drivers/CMSIS/Include/core_cm7.h **** #endif
@ -4198,7 +4198,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
2365:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
2366:Drivers/CMSIS/Include/core_cm7.h ****
2367:Drivers/CMSIS/Include/core_cm7.h **** ccsidr = SCB->CCSIDR;
ARM GAS /tmp/ccs1e2mJ.s page 71
ARM GAS /tmp/ccvevkMB.s page 71
2368:Drivers/CMSIS/Include/core_cm7.h ****
@ -4258,7 +4258,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
2422:Drivers/CMSIS/Include/core_cm7.h ****
2423:Drivers/CMSIS/Include/core_cm7.h **** /**
2424:Drivers/CMSIS/Include/core_cm7.h **** \brief Clean & Invalidate D-Cache
ARM GAS /tmp/ccs1e2mJ.s page 72
ARM GAS /tmp/ccvevkMB.s page 72
2425:Drivers/CMSIS/Include/core_cm7.h **** \details Cleans and Invalidates D-Cache
@ -4318,7 +4318,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
2479:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
2480:Drivers/CMSIS/Include/core_cm7.h **** __ISB();
2481:Drivers/CMSIS/Include/core_cm7.h **** #endif
ARM GAS /tmp/ccs1e2mJ.s page 73
ARM GAS /tmp/ccvevkMB.s page 73
2482:Drivers/CMSIS/Include/core_cm7.h **** }
@ -4378,7 +4378,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
2536:Drivers/CMSIS/Include/core_cm7.h **** }
2537:Drivers/CMSIS/Include/core_cm7.h ****
2538:Drivers/CMSIS/Include/core_cm7.h ****
ARM GAS /tmp/ccs1e2mJ.s page 74
ARM GAS /tmp/ccvevkMB.s page 74
2539:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of CMSIS_Core_CacheFunctions */
@ -4438,7 +4438,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
2026:Drivers/CMSIS/Include/core_cm7.h **** {
495 .loc 2 2026 3 view .LVU131
2032:Drivers/CMSIS/Include/core_cm7.h **** }
ARM GAS /tmp/ccs1e2mJ.s page 75
ARM GAS /tmp/ccvevkMB.s page 75
496 .loc 2 2032 5 view .LVU132
@ -4498,7 +4498,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
542 HAL_MPU_Disable:
543 .LFB147:
232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
ARM GAS /tmp/ccs1e2mJ.s page 76
ARM GAS /tmp/ccvevkMB.s page 76
233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @}
@ -4558,7 +4558,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
559 .thumb
560 .syntax unified
561 .LBE87:
ARM GAS /tmp/ccs1e2mJ.s page 77
ARM GAS /tmp/ccvevkMB.s page 77
562 .LBE86:
@ -4618,7 +4618,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
597 @ link register save eliminated.
282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Enable the MPU */
283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
ARM GAS /tmp/ccs1e2mJ.s page 78
ARM GAS /tmp/ccvevkMB.s page 78
598 .loc 1 283 3 view .LVU155
@ -4678,7 +4678,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
640 .L34:
641 .align 2
642 .L33:
ARM GAS /tmp/ccs1e2mJ.s page 79
ARM GAS /tmp/ccvevkMB.s page 79
643 001c 00ED00E0 .word -536810240
@ -4738,7 +4738,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
684 .syntax unified
685 .thumb
686 .thumb_func
ARM GAS /tmp/ccs1e2mJ.s page 80
ARM GAS /tmp/ccvevkMB.s page 80
687 .fpu fpv5-d16
@ -4798,7 +4798,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Initializes and configures the Region and the memory to be protected.
327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * the initialization and configuration information.
ARM GAS /tmp/ccs1e2mJ.s page 81
ARM GAS /tmp/ccvevkMB.s page 81
329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval None
@ -4858,7 +4858,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
756 .loc 1 353 3 is_stmt 1 view .LVU197
757 .loc 1 353 34 is_stmt 0 view .LVU198
ARM GAS /tmp/ccs1e2mJ.s page 82
ARM GAS /tmp/ccvevkMB.s page 82
758 001a 017B ldrb r1, [r0, #12] @ zero_extendqisi2
@ -4918,7 +4918,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
795 .loc 1 362 1 view .LVU217
796 0050 7047 bx lr
ARM GAS /tmp/ccs1e2mJ.s page 83
ARM GAS /tmp/ccvevkMB.s page 83
797 .L43:
@ -4978,7 +4978,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
840 .section .text.HAL_NVIC_GetPriority,"ax",%progbits
841 .align 1
842 .global HAL_NVIC_GetPriority
ARM GAS /tmp/ccs1e2mJ.s page 84
ARM GAS /tmp/ccvevkMB.s page 84
843 .syntax unified
@ -5038,7 +5038,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
868 .loc 2 2049 3 view .LVU229
2049:Drivers/CMSIS/Include/core_cm7.h **** {
869 .loc 2 2049 6 is_stmt 0 view .LVU230
ARM GAS /tmp/ccs1e2mJ.s page 85
ARM GAS /tmp/ccvevkMB.s page 85
870 0002 0028 cmp r0, #0
@ -5098,7 +5098,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
908 0022 15D9 bls .L51
909 0024 0339 subs r1, r1, #3
910 .LVL49:
ARM GAS /tmp/ccs1e2mJ.s page 86
ARM GAS /tmp/ccvevkMB.s page 86
911 .L50:
@ -5158,7 +5158,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
950 004c 0009 lsrs r0, r0, #4
951 004e DDE7 b .L49
952 .LVL56:
ARM GAS /tmp/ccs1e2mJ.s page 87
ARM GAS /tmp/ccvevkMB.s page 87
953 .L51:
@ -5218,7 +5218,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
991 .loc 1 417 3 view .LVU267
992 .LBB106:
993 .LBI106:
ARM GAS /tmp/ccs1e2mJ.s page 88
ARM GAS /tmp/ccvevkMB.s page 88
1970:Drivers/CMSIS/Include/core_cm7.h **** {
@ -5278,7 +5278,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****
420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Gets Pending Interrupt (reads the pending register in the NVIC
ARM GAS /tmp/ccs1e2mJ.s page 89
ARM GAS /tmp/ccvevkMB.s page 89
422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * and returns the pending bit for the specified interrupt).
@ -5338,7 +5338,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1069 001a 7047 bx lr
1070 .L61:
1959:Drivers/CMSIS/Include/core_cm7.h **** }
ARM GAS /tmp/ccs1e2mJ.s page 90
ARM GAS /tmp/ccvevkMB.s page 90
1071 .loc 2 1959 11 view .LVU292
@ -5398,7 +5398,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1108 .loc 2 1987 3 view .LVU299
1987:Drivers/CMSIS/Include/core_cm7.h **** {
1109 .loc 2 1987 6 is_stmt 0 view .LVU300
ARM GAS /tmp/ccs1e2mJ.s page 91
ARM GAS /tmp/ccvevkMB.s page 91
1110 0000 0028 cmp r0, #0
@ -5458,7 +5458,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * - 1 Interrupt status is pending.
461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */
462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
ARM GAS /tmp/ccs1e2mJ.s page 92
ARM GAS /tmp/ccvevkMB.s page 92
463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
@ -5518,7 +5518,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1187 .LBE113:
1188 .LBE112:
469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
ARM GAS /tmp/ccs1e2mJ.s page 93
ARM GAS /tmp/ccvevkMB.s page 93
1189 .loc 1 469 1 view .LVU324
@ -5578,7 +5578,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
1225 .loc 1 491 1 view .LVU331
ARM GAS /tmp/ccs1e2mJ.s page 94
ARM GAS /tmp/ccvevkMB.s page 94
1226 0010 7047 bx lr
@ -5638,7 +5638,7 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1261 .syntax unified
1262 .thumb
1263 .thumb_func
ARM GAS /tmp/ccs1e2mJ.s page 95
ARM GAS /tmp/ccvevkMB.s page 95
1264 .fpu fpv5-d16
@ -5668,70 +5668,70 @@ ARM GAS /tmp/ccs1e2mJ.s page 1
1287 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
1288 .file 5 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
1289 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h"
ARM GAS /tmp/ccs1e2mJ.s page 96
ARM GAS /tmp/ccvevkMB.s page 96
DEFINED SYMBOLS
*ABS*:0000000000000000 stm32f7xx_hal_cortex.c
/tmp/ccs1e2mJ.s:17 .text.HAL_NVIC_SetPriorityGrouping:0000000000000000 $t
/tmp/ccs1e2mJ.s:25 .text.HAL_NVIC_SetPriorityGrouping:0000000000000000 HAL_NVIC_SetPriorityGrouping
/tmp/ccs1e2mJ.s:81 .text.HAL_NVIC_SetPriorityGrouping:000000000000001c $d
/tmp/ccs1e2mJ.s:87 .text.HAL_NVIC_SetPriority:0000000000000000 $t
/tmp/ccs1e2mJ.s:94 .text.HAL_NVIC_SetPriority:0000000000000000 HAL_NVIC_SetPriority
/tmp/ccs1e2mJ.s:234 .text.HAL_NVIC_SetPriority:0000000000000060 $d
/tmp/ccs1e2mJ.s:241 .text.HAL_NVIC_EnableIRQ:0000000000000000 $t
/tmp/ccs1e2mJ.s:248 .text.HAL_NVIC_EnableIRQ:0000000000000000 HAL_NVIC_EnableIRQ
/tmp/ccs1e2mJ.s:289 .text.HAL_NVIC_EnableIRQ:0000000000000018 $d
/tmp/ccs1e2mJ.s:294 .text.HAL_NVIC_DisableIRQ:0000000000000000 $t
/tmp/ccs1e2mJ.s:301 .text.HAL_NVIC_DisableIRQ:0000000000000000 HAL_NVIC_DisableIRQ
/tmp/ccs1e2mJ.s:372 .text.HAL_NVIC_DisableIRQ:0000000000000020 $d
/tmp/ccs1e2mJ.s:377 .text.HAL_NVIC_SystemReset:0000000000000000 $t
/tmp/ccs1e2mJ.s:384 .text.HAL_NVIC_SystemReset:0000000000000000 HAL_NVIC_SystemReset
/tmp/ccs1e2mJ.s:450 .text.HAL_NVIC_SystemReset:000000000000001c $d
/tmp/ccs1e2mJ.s:458 .text.HAL_SYSTICK_Config:0000000000000000 $t
/tmp/ccs1e2mJ.s:465 .text.HAL_SYSTICK_Config:0000000000000000 HAL_SYSTICK_Config
/tmp/ccs1e2mJ.s:530 .text.HAL_SYSTICK_Config:0000000000000024 $d
/tmp/ccs1e2mJ.s:535 .text.HAL_MPU_Disable:0000000000000000 $t
/tmp/ccs1e2mJ.s:542 .text.HAL_MPU_Disable:0000000000000000 HAL_MPU_Disable
/tmp/ccs1e2mJ.s:578 .text.HAL_MPU_Disable:0000000000000018 $d
/tmp/ccs1e2mJ.s:583 .text.HAL_MPU_Enable:0000000000000000 $t
/tmp/ccs1e2mJ.s:590 .text.HAL_MPU_Enable:0000000000000000 HAL_MPU_Enable
/tmp/ccs1e2mJ.s:643 .text.HAL_MPU_Enable:000000000000001c $d
/tmp/ccs1e2mJ.s:648 .text.HAL_MPU_EnableRegion:0000000000000000 $t
/tmp/ccs1e2mJ.s:655 .text.HAL_MPU_EnableRegion:0000000000000000 HAL_MPU_EnableRegion
/tmp/ccs1e2mJ.s:677 .text.HAL_MPU_EnableRegion:0000000000000014 $d
/tmp/ccs1e2mJ.s:682 .text.HAL_MPU_DisableRegion:0000000000000000 $t
/tmp/ccs1e2mJ.s:689 .text.HAL_MPU_DisableRegion:0000000000000000 HAL_MPU_DisableRegion
/tmp/ccs1e2mJ.s:711 .text.HAL_MPU_DisableRegion:0000000000000014 $d
/tmp/ccs1e2mJ.s:716 .text.HAL_MPU_ConfigRegion:0000000000000000 $t
/tmp/ccs1e2mJ.s:723 .text.HAL_MPU_ConfigRegion:0000000000000000 HAL_MPU_ConfigRegion
/tmp/ccs1e2mJ.s:800 .text.HAL_MPU_ConfigRegion:0000000000000054 $d
/tmp/ccs1e2mJ.s:805 .text.HAL_NVIC_GetPriorityGrouping:0000000000000000 $t
/tmp/ccs1e2mJ.s:812 .text.HAL_NVIC_GetPriorityGrouping:0000000000000000 HAL_NVIC_GetPriorityGrouping
/tmp/ccs1e2mJ.s:836 .text.HAL_NVIC_GetPriorityGrouping:000000000000000c $d
/tmp/ccs1e2mJ.s:841 .text.HAL_NVIC_GetPriority:0000000000000000 $t
/tmp/ccs1e2mJ.s:848 .text.HAL_NVIC_GetPriority:0000000000000000 HAL_NVIC_GetPriority
/tmp/ccs1e2mJ.s:967 .text.HAL_NVIC_GetPriority:0000000000000054 $d
/tmp/ccs1e2mJ.s:975 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 $t
/tmp/ccs1e2mJ.s:982 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 HAL_NVIC_SetPendingIRQ
/tmp/ccs1e2mJ.s:1024 .text.HAL_NVIC_SetPendingIRQ:0000000000000018 $d
/tmp/ccs1e2mJ.s:1029 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 $t
/tmp/ccs1e2mJ.s:1036 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 HAL_NVIC_GetPendingIRQ
/tmp/ccs1e2mJ.s:1082 .text.HAL_NVIC_GetPendingIRQ:0000000000000020 $d
/tmp/ccs1e2mJ.s:1087 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 $t
/tmp/ccs1e2mJ.s:1094 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 HAL_NVIC_ClearPendingIRQ
/tmp/ccs1e2mJ.s:1136 .text.HAL_NVIC_ClearPendingIRQ:0000000000000018 $d
/tmp/ccs1e2mJ.s:1141 .text.HAL_NVIC_GetActive:0000000000000000 $t
/tmp/ccs1e2mJ.s:1148 .text.HAL_NVIC_GetActive:0000000000000000 HAL_NVIC_GetActive
/tmp/ccs1e2mJ.s:1194 .text.HAL_NVIC_GetActive:0000000000000020 $d
/tmp/ccs1e2mJ.s:1199 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 $t
/tmp/ccs1e2mJ.s:1206 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 HAL_SYSTICK_CLKSourceConfig
/tmp/ccs1e2mJ.s:1239 .text.HAL_SYSTICK_Callback:0000000000000000 $t
/tmp/ccs1e2mJ.s:1246 .text.HAL_SYSTICK_Callback:0000000000000000 HAL_SYSTICK_Callback
ARM GAS /tmp/ccs1e2mJ.s page 97
/tmp/ccvevkMB.s:17 .text.HAL_NVIC_SetPriorityGrouping:0000000000000000 $t
/tmp/ccvevkMB.s:25 .text.HAL_NVIC_SetPriorityGrouping:0000000000000000 HAL_NVIC_SetPriorityGrouping
/tmp/ccvevkMB.s:81 .text.HAL_NVIC_SetPriorityGrouping:000000000000001c $d
/tmp/ccvevkMB.s:87 .text.HAL_NVIC_SetPriority:0000000000000000 $t
/tmp/ccvevkMB.s:94 .text.HAL_NVIC_SetPriority:0000000000000000 HAL_NVIC_SetPriority
/tmp/ccvevkMB.s:234 .text.HAL_NVIC_SetPriority:0000000000000060 $d
/tmp/ccvevkMB.s:241 .text.HAL_NVIC_EnableIRQ:0000000000000000 $t
/tmp/ccvevkMB.s:248 .text.HAL_NVIC_EnableIRQ:0000000000000000 HAL_NVIC_EnableIRQ
/tmp/ccvevkMB.s:289 .text.HAL_NVIC_EnableIRQ:0000000000000018 $d
/tmp/ccvevkMB.s:294 .text.HAL_NVIC_DisableIRQ:0000000000000000 $t
/tmp/ccvevkMB.s:301 .text.HAL_NVIC_DisableIRQ:0000000000000000 HAL_NVIC_DisableIRQ
/tmp/ccvevkMB.s:372 .text.HAL_NVIC_DisableIRQ:0000000000000020 $d
/tmp/ccvevkMB.s:377 .text.HAL_NVIC_SystemReset:0000000000000000 $t
/tmp/ccvevkMB.s:384 .text.HAL_NVIC_SystemReset:0000000000000000 HAL_NVIC_SystemReset
/tmp/ccvevkMB.s:450 .text.HAL_NVIC_SystemReset:000000000000001c $d
/tmp/ccvevkMB.s:458 .text.HAL_SYSTICK_Config:0000000000000000 $t
/tmp/ccvevkMB.s:465 .text.HAL_SYSTICK_Config:0000000000000000 HAL_SYSTICK_Config
/tmp/ccvevkMB.s:530 .text.HAL_SYSTICK_Config:0000000000000024 $d
/tmp/ccvevkMB.s:535 .text.HAL_MPU_Disable:0000000000000000 $t
/tmp/ccvevkMB.s:542 .text.HAL_MPU_Disable:0000000000000000 HAL_MPU_Disable
/tmp/ccvevkMB.s:578 .text.HAL_MPU_Disable:0000000000000018 $d
/tmp/ccvevkMB.s:583 .text.HAL_MPU_Enable:0000000000000000 $t
/tmp/ccvevkMB.s:590 .text.HAL_MPU_Enable:0000000000000000 HAL_MPU_Enable
/tmp/ccvevkMB.s:643 .text.HAL_MPU_Enable:000000000000001c $d
/tmp/ccvevkMB.s:648 .text.HAL_MPU_EnableRegion:0000000000000000 $t
/tmp/ccvevkMB.s:655 .text.HAL_MPU_EnableRegion:0000000000000000 HAL_MPU_EnableRegion
/tmp/ccvevkMB.s:677 .text.HAL_MPU_EnableRegion:0000000000000014 $d
/tmp/ccvevkMB.s:682 .text.HAL_MPU_DisableRegion:0000000000000000 $t
/tmp/ccvevkMB.s:689 .text.HAL_MPU_DisableRegion:0000000000000000 HAL_MPU_DisableRegion
/tmp/ccvevkMB.s:711 .text.HAL_MPU_DisableRegion:0000000000000014 $d
/tmp/ccvevkMB.s:716 .text.HAL_MPU_ConfigRegion:0000000000000000 $t
/tmp/ccvevkMB.s:723 .text.HAL_MPU_ConfigRegion:0000000000000000 HAL_MPU_ConfigRegion
/tmp/ccvevkMB.s:800 .text.HAL_MPU_ConfigRegion:0000000000000054 $d
/tmp/ccvevkMB.s:805 .text.HAL_NVIC_GetPriorityGrouping:0000000000000000 $t
/tmp/ccvevkMB.s:812 .text.HAL_NVIC_GetPriorityGrouping:0000000000000000 HAL_NVIC_GetPriorityGrouping
/tmp/ccvevkMB.s:836 .text.HAL_NVIC_GetPriorityGrouping:000000000000000c $d
/tmp/ccvevkMB.s:841 .text.HAL_NVIC_GetPriority:0000000000000000 $t
/tmp/ccvevkMB.s:848 .text.HAL_NVIC_GetPriority:0000000000000000 HAL_NVIC_GetPriority
/tmp/ccvevkMB.s:967 .text.HAL_NVIC_GetPriority:0000000000000054 $d
/tmp/ccvevkMB.s:975 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 $t
/tmp/ccvevkMB.s:982 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 HAL_NVIC_SetPendingIRQ
/tmp/ccvevkMB.s:1024 .text.HAL_NVIC_SetPendingIRQ:0000000000000018 $d
/tmp/ccvevkMB.s:1029 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 $t
/tmp/ccvevkMB.s:1036 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 HAL_NVIC_GetPendingIRQ
/tmp/ccvevkMB.s:1082 .text.HAL_NVIC_GetPendingIRQ:0000000000000020 $d
/tmp/ccvevkMB.s:1087 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 $t
/tmp/ccvevkMB.s:1094 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 HAL_NVIC_ClearPendingIRQ
/tmp/ccvevkMB.s:1136 .text.HAL_NVIC_ClearPendingIRQ:0000000000000018 $d
/tmp/ccvevkMB.s:1141 .text.HAL_NVIC_GetActive:0000000000000000 $t
/tmp/ccvevkMB.s:1148 .text.HAL_NVIC_GetActive:0000000000000000 HAL_NVIC_GetActive
/tmp/ccvevkMB.s:1194 .text.HAL_NVIC_GetActive:0000000000000020 $d
/tmp/ccvevkMB.s:1199 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 $t
/tmp/ccvevkMB.s:1206 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 HAL_SYSTICK_CLKSourceConfig
/tmp/ccvevkMB.s:1239 .text.HAL_SYSTICK_Callback:0000000000000000 $t
/tmp/ccvevkMB.s:1246 .text.HAL_SYSTICK_Callback:0000000000000000 HAL_SYSTICK_Callback
ARM GAS /tmp/ccvevkMB.s page 97
/tmp/ccs1e2mJ.s:1259 .text.HAL_SYSTICK_IRQHandler:0000000000000000 $t
/tmp/ccs1e2mJ.s:1266 .text.HAL_SYSTICK_IRQHandler:0000000000000000 HAL_SYSTICK_IRQHandler
/tmp/ccvevkMB.s:1259 .text.HAL_SYSTICK_IRQHandler:0000000000000000 $t
/tmp/ccvevkMB.s:1266 .text.HAL_SYSTICK_IRQHandler:0000000000000000 HAL_SYSTICK_IRQHandler
NO UNDEFINED SYMBOLS