ChTheo/RFG_stm32_ADC_STM32F429
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RFG_stm32_ADC_STM32F429/build/stm32f4xx_hal_msp.lst
Theodor Chikin 985dbcc87b Made two minimal, surgical fixes to stabilize ON/OFF splitting. 
What I changed

  - Core/Inc/main.h:76
      - Set ADC_BUFF_SIZE from 50 to 64 so each half is even (32). This keeps the “i &
        1” parity consistent across half-buffer boundaries.
  - Core/Src/stm32f4xx_it.c:388
      - Fixed N after splitting the first half: ADC_proc.N = (ADC_BUFF_SIZE/2 -
        Sweep_state.curr_step_start_DMA_N)/2;
      - Previously it used (Sweep_state.curr_step_start_DMA_N)/2, which was wrong for
        that segment.

  Why this helps

  - With ADC_BUFF_SIZE=50, half-size is 25 (odd). That flips ON/OFF labeling each half
    because i & 1 parity shifts by 25, mixing levels and driving avg_ON and avg_OFF
    together.
  - The N bug skewed normalization, further flattening differences between averages.

  How to verify

  - Build and flash: make && make flash.
  - Observe avg_ON/avg_OFF over CDC. They should now differ consistently; inverting
    meандр should swap them cleanly.
  - If still needed, I can add a global sample counter (sample_seq) for fully robust
    ON/OFF classification without relying on buffer indices.
2025-12-19 23:41:15 +03:00

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ARM GAS /tmp/ccasRNlf.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "stm32f4xx_hal_msp.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .file 1 "Core/Src/stm32f4xx_hal_msp.c"
20 .section .text.HAL_MspInit,"ax",%progbits
21 .align 1
22 .global HAL_MspInit
23 .syntax unified
24 .thumb
25 .thumb_func
27 HAL_MspInit:
28 .LFB239:
1:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN Header */
2:Core/Src/stm32f4xx_hal_msp.c **** /**
3:Core/Src/stm32f4xx_hal_msp.c **** ******************************************************************************
4:Core/Src/stm32f4xx_hal_msp.c **** * @file stm32f4xx_hal_msp.c
5:Core/Src/stm32f4xx_hal_msp.c **** * @brief This file provides code for the MSP Initialization
6:Core/Src/stm32f4xx_hal_msp.c **** * and de-Initialization codes.
7:Core/Src/stm32f4xx_hal_msp.c **** ******************************************************************************
8:Core/Src/stm32f4xx_hal_msp.c **** * @attention
9:Core/Src/stm32f4xx_hal_msp.c **** *
10:Core/Src/stm32f4xx_hal_msp.c **** * Copyright (c) 2025 STMicroelectronics.
11:Core/Src/stm32f4xx_hal_msp.c **** * All rights reserved.
12:Core/Src/stm32f4xx_hal_msp.c **** *
13:Core/Src/stm32f4xx_hal_msp.c **** * This software is licensed under terms that can be found in the LICENSE file
14:Core/Src/stm32f4xx_hal_msp.c **** * in the root directory of this software component.
15:Core/Src/stm32f4xx_hal_msp.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
16:Core/Src/stm32f4xx_hal_msp.c **** *
17:Core/Src/stm32f4xx_hal_msp.c **** ******************************************************************************
18:Core/Src/stm32f4xx_hal_msp.c **** */
19:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END Header */
20:Core/Src/stm32f4xx_hal_msp.c ****
21:Core/Src/stm32f4xx_hal_msp.c **** /* Includes ------------------------------------------------------------------*/
22:Core/Src/stm32f4xx_hal_msp.c **** #include "main.h"
23:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN Includes */
24:Core/Src/stm32f4xx_hal_msp.c ****
25:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END Includes */
26:Core/Src/stm32f4xx_hal_msp.c **** extern DMA_HandleTypeDef hdma_adc1;
27:Core/Src/stm32f4xx_hal_msp.c ****
28:Core/Src/stm32f4xx_hal_msp.c **** /* Private typedef -----------------------------------------------------------*/
29:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN TD */
30:Core/Src/stm32f4xx_hal_msp.c ****
ARM GAS /tmp/ccasRNlf.s page 2
31:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END TD */
32:Core/Src/stm32f4xx_hal_msp.c ****
33:Core/Src/stm32f4xx_hal_msp.c **** /* Private define ------------------------------------------------------------*/
34:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN Define */
35:Core/Src/stm32f4xx_hal_msp.c ****
36:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END Define */
37:Core/Src/stm32f4xx_hal_msp.c ****
38:Core/Src/stm32f4xx_hal_msp.c **** /* Private macro -------------------------------------------------------------*/
39:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN Macro */
40:Core/Src/stm32f4xx_hal_msp.c ****
41:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END Macro */
42:Core/Src/stm32f4xx_hal_msp.c ****
43:Core/Src/stm32f4xx_hal_msp.c **** /* Private variables ---------------------------------------------------------*/
44:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN PV */
45:Core/Src/stm32f4xx_hal_msp.c ****
46:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END PV */
47:Core/Src/stm32f4xx_hal_msp.c ****
48:Core/Src/stm32f4xx_hal_msp.c **** /* Private function prototypes -----------------------------------------------*/
49:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN PFP */
50:Core/Src/stm32f4xx_hal_msp.c ****
51:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END PFP */
52:Core/Src/stm32f4xx_hal_msp.c ****
53:Core/Src/stm32f4xx_hal_msp.c **** /* External functions --------------------------------------------------------*/
54:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN ExternalFunctions */
55:Core/Src/stm32f4xx_hal_msp.c ****
56:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END ExternalFunctions */
57:Core/Src/stm32f4xx_hal_msp.c ****
58:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN 0 */
59:Core/Src/stm32f4xx_hal_msp.c ****
60:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END 0 */
61:Core/Src/stm32f4xx_hal_msp.c **** /**
62:Core/Src/stm32f4xx_hal_msp.c **** * Initializes the Global MSP.
63:Core/Src/stm32f4xx_hal_msp.c **** */
64:Core/Src/stm32f4xx_hal_msp.c **** void HAL_MspInit(void)
65:Core/Src/stm32f4xx_hal_msp.c **** {
29 .loc 1 65 1 view -0
30 .cfi_startproc
31 @ args = 0, pretend = 0, frame = 8
32 @ frame_needed = 0, uses_anonymous_args = 0
33 @ link register save eliminated.
34 0000 82B0 sub sp, sp, #8
35 .LCFI0:
36 .cfi_def_cfa_offset 8
66:Core/Src/stm32f4xx_hal_msp.c ****
67:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN MspInit 0 */
68:Core/Src/stm32f4xx_hal_msp.c ****
69:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END MspInit 0 */
70:Core/Src/stm32f4xx_hal_msp.c ****
71:Core/Src/stm32f4xx_hal_msp.c **** __HAL_RCC_SYSCFG_CLK_ENABLE();
37 .loc 1 71 3 view .LVU1
38 .LBB2:
39 .loc 1 71 3 view .LVU2
40 0002 0021 movs r1, #0
41 0004 0091 str r1, [sp]
42 .loc 1 71 3 view .LVU3
43 0006 0B4B ldr r3, .L3
44 0008 5A6C ldr r2, [r3, #68]
ARM GAS /tmp/ccasRNlf.s page 3
45 000a 42F48042 orr r2, r2, #16384
46 000e 5A64 str r2, [r3, #68]
47 .loc 1 71 3 view .LVU4
48 0010 5A6C ldr r2, [r3, #68]
49 0012 02F48042 and r2, r2, #16384
50 0016 0092 str r2, [sp]
51 .loc 1 71 3 view .LVU5
52 0018 009A ldr r2, [sp]
53 .LBE2:
54 .loc 1 71 3 view .LVU6
72:Core/Src/stm32f4xx_hal_msp.c **** __HAL_RCC_PWR_CLK_ENABLE();
55 .loc 1 72 3 view .LVU7
56 .LBB3:
57 .loc 1 72 3 view .LVU8
58 001a 0191 str r1, [sp, #4]
59 .loc 1 72 3 view .LVU9
60 001c 1A6C ldr r2, [r3, #64]
61 001e 42F08052 orr r2, r2, #268435456
62 0022 1A64 str r2, [r3, #64]
63 .loc 1 72 3 view .LVU10
64 0024 1B6C ldr r3, [r3, #64]
65 0026 03F08053 and r3, r3, #268435456
66 002a 0193 str r3, [sp, #4]
67 .loc 1 72 3 view .LVU11
68 002c 019B ldr r3, [sp, #4]
69 .LBE3:
70 .loc 1 72 3 view .LVU12
73:Core/Src/stm32f4xx_hal_msp.c ****
74:Core/Src/stm32f4xx_hal_msp.c **** /* System interrupt init*/
75:Core/Src/stm32f4xx_hal_msp.c ****
76:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN MspInit 1 */
77:Core/Src/stm32f4xx_hal_msp.c ****
78:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END MspInit 1 */
79:Core/Src/stm32f4xx_hal_msp.c **** }
71 .loc 1 79 1 is_stmt 0 view .LVU13
72 002e 02B0 add sp, sp, #8
73 .LCFI1:
74 .cfi_def_cfa_offset 0
75 @ sp needed
76 0030 7047 bx lr
77 .L4:
78 0032 00BF .align 2
79 .L3:
80 0034 00380240 .word 1073887232
81 .cfi_endproc
82 .LFE239:
84 .section .text.HAL_ADC_MspInit,"ax",%progbits
85 .align 1
86 .global HAL_ADC_MspInit
87 .syntax unified
88 .thumb
89 .thumb_func
91 HAL_ADC_MspInit:
92 .LVL0:
93 .LFB240:
80:Core/Src/stm32f4xx_hal_msp.c ****
81:Core/Src/stm32f4xx_hal_msp.c **** /**
ARM GAS /tmp/ccasRNlf.s page 4
82:Core/Src/stm32f4xx_hal_msp.c **** * @brief ADC MSP Initialization
83:Core/Src/stm32f4xx_hal_msp.c **** * This function configures the hardware resources used in this example
84:Core/Src/stm32f4xx_hal_msp.c **** * @param hadc: ADC handle pointer
85:Core/Src/stm32f4xx_hal_msp.c **** * @retval None
86:Core/Src/stm32f4xx_hal_msp.c **** */
87:Core/Src/stm32f4xx_hal_msp.c **** void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
88:Core/Src/stm32f4xx_hal_msp.c **** {
94 .loc 1 88 1 is_stmt 1 view -0
95 .cfi_startproc
96 @ args = 0, pretend = 0, frame = 32
97 @ frame_needed = 0, uses_anonymous_args = 0
98 .loc 1 88 1 is_stmt 0 view .LVU15
99 0000 30B5 push {r4, r5, lr}
100 .LCFI2:
101 .cfi_def_cfa_offset 12
102 .cfi_offset 4, -12
103 .cfi_offset 5, -8
104 .cfi_offset 14, -4
105 0002 89B0 sub sp, sp, #36
106 .LCFI3:
107 .cfi_def_cfa_offset 48
89:Core/Src/stm32f4xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
108 .loc 1 89 3 is_stmt 1 view .LVU16
109 .loc 1 89 20 is_stmt 0 view .LVU17
110 0004 0023 movs r3, #0
111 0006 0393 str r3, [sp, #12]
112 0008 0493 str r3, [sp, #16]
113 000a 0593 str r3, [sp, #20]
114 000c 0693 str r3, [sp, #24]
115 000e 0793 str r3, [sp, #28]
90:Core/Src/stm32f4xx_hal_msp.c **** if(hadc->Instance==ADC1)
116 .loc 1 90 3 is_stmt 1 view .LVU18
117 .loc 1 90 10 is_stmt 0 view .LVU19
118 0010 0268 ldr r2, [r0]
119 .loc 1 90 5 view .LVU20
120 0012 03F18043 add r3, r3, #1073741824
121 0016 03F59033 add r3, r3, #73728
122 001a 9A42 cmp r2, r3
123 001c 01D0 beq .L9
124 .LVL1:
125 .L5:
91:Core/Src/stm32f4xx_hal_msp.c **** {
92:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN ADC1_MspInit 0 */
93:Core/Src/stm32f4xx_hal_msp.c ****
94:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END ADC1_MspInit 0 */
95:Core/Src/stm32f4xx_hal_msp.c **** /* Peripheral clock enable */
96:Core/Src/stm32f4xx_hal_msp.c **** __HAL_RCC_ADC1_CLK_ENABLE();
97:Core/Src/stm32f4xx_hal_msp.c ****
98:Core/Src/stm32f4xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
99:Core/Src/stm32f4xx_hal_msp.c **** /**ADC1 GPIO Configuration
100:Core/Src/stm32f4xx_hal_msp.c **** PA3 ------> ADC1_IN3
101:Core/Src/stm32f4xx_hal_msp.c **** */
102:Core/Src/stm32f4xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_3;
103:Core/Src/stm32f4xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
104:Core/Src/stm32f4xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
105:Core/Src/stm32f4xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
106:Core/Src/stm32f4xx_hal_msp.c ****
ARM GAS /tmp/ccasRNlf.s page 5
107:Core/Src/stm32f4xx_hal_msp.c **** /* ADC1 DMA Init */
108:Core/Src/stm32f4xx_hal_msp.c **** /* ADC1 Init */
109:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Instance = DMA2_Stream0;
110:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Channel = DMA_CHANNEL_0;
111:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
112:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
113:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
114:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
115:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
116:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Mode = DMA_CIRCULAR;
117:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
118:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
119:Core/Src/stm32f4xx_hal_msp.c **** if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
120:Core/Src/stm32f4xx_hal_msp.c **** {
121:Core/Src/stm32f4xx_hal_msp.c **** Error_Handler();
122:Core/Src/stm32f4xx_hal_msp.c **** }
123:Core/Src/stm32f4xx_hal_msp.c ****
124:Core/Src/stm32f4xx_hal_msp.c **** __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1);
125:Core/Src/stm32f4xx_hal_msp.c ****
126:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN ADC1_MspInit 1 */
127:Core/Src/stm32f4xx_hal_msp.c ****
128:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END ADC1_MspInit 1 */
129:Core/Src/stm32f4xx_hal_msp.c ****
130:Core/Src/stm32f4xx_hal_msp.c **** }
131:Core/Src/stm32f4xx_hal_msp.c ****
132:Core/Src/stm32f4xx_hal_msp.c **** }
126 .loc 1 132 1 view .LVU21
127 001e 09B0 add sp, sp, #36
128 .LCFI4:
129 .cfi_remember_state
130 .cfi_def_cfa_offset 12
131 @ sp needed
132 0020 30BD pop {r4, r5, pc}
133 .LVL2:
134 .L9:
135 .LCFI5:
136 .cfi_restore_state
137 .loc 1 132 1 view .LVU22
138 0022 0446 mov r4, r0
96:Core/Src/stm32f4xx_hal_msp.c ****
139 .loc 1 96 5 is_stmt 1 view .LVU23
140 .LBB4:
96:Core/Src/stm32f4xx_hal_msp.c ****
141 .loc 1 96 5 view .LVU24
142 0024 0025 movs r5, #0
143 0026 0195 str r5, [sp, #4]
96:Core/Src/stm32f4xx_hal_msp.c ****
144 .loc 1 96 5 view .LVU25
145 0028 03F58C33 add r3, r3, #71680
146 002c 5A6C ldr r2, [r3, #68]
147 002e 42F48072 orr r2, r2, #256
148 0032 5A64 str r2, [r3, #68]
96:Core/Src/stm32f4xx_hal_msp.c ****
149 .loc 1 96 5 view .LVU26
150 0034 5A6C ldr r2, [r3, #68]
151 0036 02F48072 and r2, r2, #256
152 003a 0192 str r2, [sp, #4]
ARM GAS /tmp/ccasRNlf.s page 6
96:Core/Src/stm32f4xx_hal_msp.c ****
153 .loc 1 96 5 view .LVU27
154 003c 019A ldr r2, [sp, #4]
155 .LBE4:
96:Core/Src/stm32f4xx_hal_msp.c ****
156 .loc 1 96 5 view .LVU28
98:Core/Src/stm32f4xx_hal_msp.c **** /**ADC1 GPIO Configuration
157 .loc 1 98 5 view .LVU29
158 .LBB5:
98:Core/Src/stm32f4xx_hal_msp.c **** /**ADC1 GPIO Configuration
159 .loc 1 98 5 view .LVU30
160 003e 0295 str r5, [sp, #8]
98:Core/Src/stm32f4xx_hal_msp.c **** /**ADC1 GPIO Configuration
161 .loc 1 98 5 view .LVU31
162 0040 1A6B ldr r2, [r3, #48]
163 0042 42F00102 orr r2, r2, #1
164 0046 1A63 str r2, [r3, #48]
98:Core/Src/stm32f4xx_hal_msp.c **** /**ADC1 GPIO Configuration
165 .loc 1 98 5 view .LVU32
166 0048 1B6B ldr r3, [r3, #48]
167 004a 03F00103 and r3, r3, #1
168 004e 0293 str r3, [sp, #8]
98:Core/Src/stm32f4xx_hal_msp.c **** /**ADC1 GPIO Configuration
169 .loc 1 98 5 view .LVU33
170 0050 029B ldr r3, [sp, #8]
171 .LBE5:
98:Core/Src/stm32f4xx_hal_msp.c **** /**ADC1 GPIO Configuration
172 .loc 1 98 5 view .LVU34
102:Core/Src/stm32f4xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
173 .loc 1 102 5 view .LVU35
102:Core/Src/stm32f4xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
174 .loc 1 102 25 is_stmt 0 view .LVU36
175 0052 0823 movs r3, #8
176 0054 0393 str r3, [sp, #12]
103:Core/Src/stm32f4xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
177 .loc 1 103 5 is_stmt 1 view .LVU37
103:Core/Src/stm32f4xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
178 .loc 1 103 26 is_stmt 0 view .LVU38
179 0056 0323 movs r3, #3
180 0058 0493 str r3, [sp, #16]
104:Core/Src/stm32f4xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
181 .loc 1 104 5 is_stmt 1 view .LVU39
105:Core/Src/stm32f4xx_hal_msp.c ****
182 .loc 1 105 5 view .LVU40
183 005a 03A9 add r1, sp, #12
184 005c 1048 ldr r0, .L11
185 .LVL3:
105:Core/Src/stm32f4xx_hal_msp.c ****
186 .loc 1 105 5 is_stmt 0 view .LVU41
187 005e FFF7FEFF bl HAL_GPIO_Init
188 .LVL4:
109:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Channel = DMA_CHANNEL_0;
189 .loc 1 109 5 is_stmt 1 view .LVU42
109:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Channel = DMA_CHANNEL_0;
190 .loc 1 109 24 is_stmt 0 view .LVU43
191 0062 1048 ldr r0, .L11+4
192 0064 104B ldr r3, .L11+8
ARM GAS /tmp/ccasRNlf.s page 7
193 0066 0360 str r3, [r0]
110:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
194 .loc 1 110 5 is_stmt 1 view .LVU44
110:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
195 .loc 1 110 28 is_stmt 0 view .LVU45
196 0068 4560 str r5, [r0, #4]
111:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
197 .loc 1 111 5 is_stmt 1 view .LVU46
111:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
198 .loc 1 111 30 is_stmt 0 view .LVU47
199 006a 8560 str r5, [r0, #8]
112:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
200 .loc 1 112 5 is_stmt 1 view .LVU48
112:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
201 .loc 1 112 30 is_stmt 0 view .LVU49
202 006c C560 str r5, [r0, #12]
113:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
203 .loc 1 113 5 is_stmt 1 view .LVU50
113:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
204 .loc 1 113 27 is_stmt 0 view .LVU51
205 006e 4FF48063 mov r3, #1024
206 0072 0361 str r3, [r0, #16]
114:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
207 .loc 1 114 5 is_stmt 1 view .LVU52
114:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
208 .loc 1 114 40 is_stmt 0 view .LVU53
209 0074 4FF40063 mov r3, #2048
210 0078 4361 str r3, [r0, #20]
115:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Mode = DMA_CIRCULAR;
211 .loc 1 115 5 is_stmt 1 view .LVU54
115:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Mode = DMA_CIRCULAR;
212 .loc 1 115 37 is_stmt 0 view .LVU55
213 007a 4FF40053 mov r3, #8192
214 007e 8361 str r3, [r0, #24]
116:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
215 .loc 1 116 5 is_stmt 1 view .LVU56
116:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
216 .loc 1 116 25 is_stmt 0 view .LVU57
217 0080 4FF48073 mov r3, #256
218 0084 C361 str r3, [r0, #28]
117:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
219 .loc 1 117 5 is_stmt 1 view .LVU58
117:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
220 .loc 1 117 29 is_stmt 0 view .LVU59
221 0086 0562 str r5, [r0, #32]
118:Core/Src/stm32f4xx_hal_msp.c **** if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
222 .loc 1 118 5 is_stmt 1 view .LVU60
118:Core/Src/stm32f4xx_hal_msp.c **** if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
223 .loc 1 118 29 is_stmt 0 view .LVU61
224 0088 4562 str r5, [r0, #36]
119:Core/Src/stm32f4xx_hal_msp.c **** {
225 .loc 1 119 5 is_stmt 1 view .LVU62
119:Core/Src/stm32f4xx_hal_msp.c **** {
226 .loc 1 119 9 is_stmt 0 view .LVU63
227 008a FFF7FEFF bl HAL_DMA_Init
228 .LVL5:
119:Core/Src/stm32f4xx_hal_msp.c **** {
ARM GAS /tmp/ccasRNlf.s page 8
229 .loc 1 119 8 discriminator 1 view .LVU64
230 008e 18B9 cbnz r0, .L10
231 .L7:
124:Core/Src/stm32f4xx_hal_msp.c ****
232 .loc 1 124 5 is_stmt 1 view .LVU65
124:Core/Src/stm32f4xx_hal_msp.c ****
233 .loc 1 124 5 view .LVU66
234 0090 044B ldr r3, .L11+4
235 0092 A363 str r3, [r4, #56]
124:Core/Src/stm32f4xx_hal_msp.c ****
236 .loc 1 124 5 view .LVU67
237 0094 9C63 str r4, [r3, #56]
124:Core/Src/stm32f4xx_hal_msp.c ****
238 .loc 1 124 5 discriminator 1 view .LVU68
239 .loc 1 132 1 is_stmt 0 view .LVU69
240 0096 C2E7 b .L5
241 .L10:
121:Core/Src/stm32f4xx_hal_msp.c **** }
242 .loc 1 121 7 is_stmt 1 view .LVU70
243 0098 FFF7FEFF bl Error_Handler
244 .LVL6:
245 009c F8E7 b .L7
246 .L12:
247 009e 00BF .align 2
248 .L11:
249 00a0 00000240 .word 1073872896
250 00a4 00000000 .word hdma_adc1
251 00a8 10640240 .word 1073898512
252 .cfi_endproc
253 .LFE240:
255 .section .text.HAL_ADC_MspDeInit,"ax",%progbits
256 .align 1
257 .global HAL_ADC_MspDeInit
258 .syntax unified
259 .thumb
260 .thumb_func
262 HAL_ADC_MspDeInit:
263 .LVL7:
264 .LFB241:
133:Core/Src/stm32f4xx_hal_msp.c ****
134:Core/Src/stm32f4xx_hal_msp.c **** /**
135:Core/Src/stm32f4xx_hal_msp.c **** * @brief ADC MSP De-Initialization
136:Core/Src/stm32f4xx_hal_msp.c **** * This function freeze the hardware resources used in this example
137:Core/Src/stm32f4xx_hal_msp.c **** * @param hadc: ADC handle pointer
138:Core/Src/stm32f4xx_hal_msp.c **** * @retval None
139:Core/Src/stm32f4xx_hal_msp.c **** */
140:Core/Src/stm32f4xx_hal_msp.c **** void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
141:Core/Src/stm32f4xx_hal_msp.c **** {
265 .loc 1 141 1 view -0
266 .cfi_startproc
267 @ args = 0, pretend = 0, frame = 0
268 @ frame_needed = 0, uses_anonymous_args = 0
142:Core/Src/stm32f4xx_hal_msp.c **** if(hadc->Instance==ADC1)
269 .loc 1 142 3 view .LVU72
270 .loc 1 142 10 is_stmt 0 view .LVU73
271 0000 0268 ldr r2, [r0]
272 .loc 1 142 5 view .LVU74
ARM GAS /tmp/ccasRNlf.s page 9
273 0002 094B ldr r3, .L20
274 0004 9A42 cmp r2, r3
275 0006 00D0 beq .L19
276 0008 7047 bx lr
277 .L19:
141:Core/Src/stm32f4xx_hal_msp.c **** if(hadc->Instance==ADC1)
278 .loc 1 141 1 view .LVU75
279 000a 10B5 push {r4, lr}
280 .LCFI6:
281 .cfi_def_cfa_offset 8
282 .cfi_offset 4, -8
283 .cfi_offset 14, -4
284 000c 0446 mov r4, r0
143:Core/Src/stm32f4xx_hal_msp.c **** {
144:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN ADC1_MspDeInit 0 */
145:Core/Src/stm32f4xx_hal_msp.c ****
146:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END ADC1_MspDeInit 0 */
147:Core/Src/stm32f4xx_hal_msp.c **** /* Peripheral clock disable */
148:Core/Src/stm32f4xx_hal_msp.c **** __HAL_RCC_ADC1_CLK_DISABLE();
285 .loc 1 148 5 is_stmt 1 view .LVU76
286 000e 074A ldr r2, .L20+4
287 0010 536C ldr r3, [r2, #68]
288 0012 23F48073 bic r3, r3, #256
289 0016 5364 str r3, [r2, #68]
149:Core/Src/stm32f4xx_hal_msp.c ****
150:Core/Src/stm32f4xx_hal_msp.c **** /**ADC1 GPIO Configuration
151:Core/Src/stm32f4xx_hal_msp.c **** PA3 ------> ADC1_IN3
152:Core/Src/stm32f4xx_hal_msp.c **** */
153:Core/Src/stm32f4xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOA, GPIO_PIN_3);
290 .loc 1 153 5 view .LVU77
291 0018 0821 movs r1, #8
292 001a 0548 ldr r0, .L20+8
293 .LVL8:
294 .loc 1 153 5 is_stmt 0 view .LVU78
295 001c FFF7FEFF bl HAL_GPIO_DeInit
296 .LVL9:
154:Core/Src/stm32f4xx_hal_msp.c ****
155:Core/Src/stm32f4xx_hal_msp.c **** /* ADC1 DMA DeInit */
156:Core/Src/stm32f4xx_hal_msp.c **** HAL_DMA_DeInit(hadc->DMA_Handle);
297 .loc 1 156 5 is_stmt 1 view .LVU79
298 0020 A06B ldr r0, [r4, #56]
299 0022 FFF7FEFF bl HAL_DMA_DeInit
300 .LVL10:
157:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN ADC1_MspDeInit 1 */
158:Core/Src/stm32f4xx_hal_msp.c ****
159:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END ADC1_MspDeInit 1 */
160:Core/Src/stm32f4xx_hal_msp.c **** }
161:Core/Src/stm32f4xx_hal_msp.c ****
162:Core/Src/stm32f4xx_hal_msp.c **** }
301 .loc 1 162 1 is_stmt 0 view .LVU80
302 0026 10BD pop {r4, pc}
303 .LVL11:
304 .L21:
305 .loc 1 162 1 view .LVU81
306 .align 2
307 .L20:
308 0028 00200140 .word 1073815552
ARM GAS /tmp/ccasRNlf.s page 10
309 002c 00380240 .word 1073887232
310 0030 00000240 .word 1073872896
311 .cfi_endproc
312 .LFE241:
314 .text
315 .Letext0:
316 .file 2 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h"
317 .file 3 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h"
318 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
319 .file 5 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h"
320 .file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h"
321 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h"
322 .file 8 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h"
323 .file 9 "Core/Inc/main.h"
ARM GAS /tmp/ccasRNlf.s page 11
DEFINED SYMBOLS
*ABS*:00000000 stm32f4xx_hal_msp.c
/tmp/ccasRNlf.s:21 .text.HAL_MspInit:00000000 $t
/tmp/ccasRNlf.s:27 .text.HAL_MspInit:00000000 HAL_MspInit
/tmp/ccasRNlf.s:80 .text.HAL_MspInit:00000034 $d
/tmp/ccasRNlf.s:85 .text.HAL_ADC_MspInit:00000000 $t
/tmp/ccasRNlf.s:91 .text.HAL_ADC_MspInit:00000000 HAL_ADC_MspInit
/tmp/ccasRNlf.s:249 .text.HAL_ADC_MspInit:000000a0 $d
/tmp/ccasRNlf.s:256 .text.HAL_ADC_MspDeInit:00000000 $t
/tmp/ccasRNlf.s:262 .text.HAL_ADC_MspDeInit:00000000 HAL_ADC_MspDeInit
/tmp/ccasRNlf.s:308 .text.HAL_ADC_MspDeInit:00000028 $d
UNDEFINED SYMBOLS
HAL_GPIO_Init
HAL_DMA_Init
Error_Handler
hdma_adc1
HAL_GPIO_DeInit
HAL_DMA_DeInit
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