ChTheo/RFG_stm32_ADC_STM32F429
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985dbcc87b88a78f3c0ad6bd32253ec400fd45bb
RFG_stm32_ADC_STM32F429/build/stm32f4xx_it.lst
Theodor Chikin 985dbcc87b Made two minimal, surgical fixes to stabilize ON/OFF splitting. 
What I changed

  - Core/Inc/main.h:76
      - Set ADC_BUFF_SIZE from 50 to 64 so each half is even (32). This keeps the “i &
        1” parity consistent across half-buffer boundaries.
  - Core/Src/stm32f4xx_it.c:388
      - Fixed N after splitting the first half: ADC_proc.N = (ADC_BUFF_SIZE/2 -
        Sweep_state.curr_step_start_DMA_N)/2;
      - Previously it used (Sweep_state.curr_step_start_DMA_N)/2, which was wrong for
        that segment.

  Why this helps

  - With ADC_BUFF_SIZE=50, half-size is 25 (odd). That flips ON/OFF labeling each half
    because i & 1 parity shifts by 25, mixing levels and driving avg_ON and avg_OFF
    together.
  - The N bug skewed normalization, further flattening differences between averages.

  How to verify

  - Build and flash: make && make flash.
  - Observe avg_ON/avg_OFF over CDC. They should now differ consistently; inverting
    meандр should swap them cleanly.
  - If still needed, I can add a global sample counter (sample_seq) for fully robust
    ON/OFF classification without relying on buffer indices.
2025-12-19 23:41:15 +03:00

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ARM GAS /tmp/cc7eGm0R.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "stm32f4xx_it.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .file 1 "Core/Src/stm32f4xx_it.c"
20 .section .text.NMI_Handler,"ax",%progbits
21 .align 1
22 .global NMI_Handler
23 .syntax unified
24 .thumb
25 .thumb_func
27 NMI_Handler:
28 .LFB239:
1:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN Header */
2:Core/Src/stm32f4xx_it.c **** /**
3:Core/Src/stm32f4xx_it.c **** ******************************************************************************
4:Core/Src/stm32f4xx_it.c **** * @file stm32f4xx_it.c
5:Core/Src/stm32f4xx_it.c **** * @brief Interrupt Service Routines.
6:Core/Src/stm32f4xx_it.c **** ******************************************************************************
7:Core/Src/stm32f4xx_it.c **** * @attention
8:Core/Src/stm32f4xx_it.c **** *
9:Core/Src/stm32f4xx_it.c **** * Copyright (c) 2025 STMicroelectronics.
10:Core/Src/stm32f4xx_it.c **** * All rights reserved.
11:Core/Src/stm32f4xx_it.c **** *
12:Core/Src/stm32f4xx_it.c **** * This software is licensed under terms that can be found in the LICENSE file
13:Core/Src/stm32f4xx_it.c **** * in the root directory of this software component.
14:Core/Src/stm32f4xx_it.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
15:Core/Src/stm32f4xx_it.c **** *
16:Core/Src/stm32f4xx_it.c **** ******************************************************************************
17:Core/Src/stm32f4xx_it.c **** */
18:Core/Src/stm32f4xx_it.c **** /* USER CODE END Header */
19:Core/Src/stm32f4xx_it.c ****
20:Core/Src/stm32f4xx_it.c **** /* Includes ------------------------------------------------------------------*/
21:Core/Src/stm32f4xx_it.c **** #include "main.h"
22:Core/Src/stm32f4xx_it.c **** #include "stm32f4xx_it.h"
23:Core/Src/stm32f4xx_it.c **** /* Private includes ----------------------------------------------------------*/
24:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN Includes */
25:Core/Src/stm32f4xx_it.c **** /* USER CODE END Includes */
26:Core/Src/stm32f4xx_it.c ****
27:Core/Src/stm32f4xx_it.c **** /* Private typedef -----------------------------------------------------------*/
28:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN TD */
29:Core/Src/stm32f4xx_it.c ****
30:Core/Src/stm32f4xx_it.c **** /* USER CODE END TD */
ARM GAS /tmp/cc7eGm0R.s page 2
31:Core/Src/stm32f4xx_it.c ****
32:Core/Src/stm32f4xx_it.c **** /* Private define ------------------------------------------------------------*/
33:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PD */
34:Core/Src/stm32f4xx_it.c ****
35:Core/Src/stm32f4xx_it.c **** /* USER CODE END PD */
36:Core/Src/stm32f4xx_it.c ****
37:Core/Src/stm32f4xx_it.c **** /* Private macro -------------------------------------------------------------*/
38:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PM */
39:Core/Src/stm32f4xx_it.c ****
40:Core/Src/stm32f4xx_it.c **** /* USER CODE END PM */
41:Core/Src/stm32f4xx_it.c ****
42:Core/Src/stm32f4xx_it.c **** /* Private variables ---------------------------------------------------------*/
43:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PV */
44:Core/Src/stm32f4xx_it.c ****
45:Core/Src/stm32f4xx_it.c **** /* USER CODE END PV */
46:Core/Src/stm32f4xx_it.c ****
47:Core/Src/stm32f4xx_it.c **** /* Private function prototypes -----------------------------------------------*/
48:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PFP */
49:Core/Src/stm32f4xx_it.c ****
50:Core/Src/stm32f4xx_it.c **** /* USER CODE END PFP */
51:Core/Src/stm32f4xx_it.c ****
52:Core/Src/stm32f4xx_it.c **** /* Private user code ---------------------------------------------------------*/
53:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN 0 */
54:Core/Src/stm32f4xx_it.c ****
55:Core/Src/stm32f4xx_it.c **** /* USER CODE END 0 */
56:Core/Src/stm32f4xx_it.c ****
57:Core/Src/stm32f4xx_it.c **** /* External variables --------------------------------------------------------*/
58:Core/Src/stm32f4xx_it.c **** extern PCD_HandleTypeDef hpcd_USB_OTG_FS;
59:Core/Src/stm32f4xx_it.c **** extern DMA_HandleTypeDef hdma_adc1;
60:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN EV */
61:Core/Src/stm32f4xx_it.c **** /* Externs are provided via main.h; no extra declarations needed here */
62:Core/Src/stm32f4xx_it.c **** /* USER CODE END EV */
63:Core/Src/stm32f4xx_it.c ****
64:Core/Src/stm32f4xx_it.c **** /******************************************************************************/
65:Core/Src/stm32f4xx_it.c **** /* Cortex-M4 Processor Interruption and Exception Handlers */
66:Core/Src/stm32f4xx_it.c **** /******************************************************************************/
67:Core/Src/stm32f4xx_it.c **** /**
68:Core/Src/stm32f4xx_it.c **** * @brief This function handles Non maskable interrupt.
69:Core/Src/stm32f4xx_it.c **** */
70:Core/Src/stm32f4xx_it.c **** void NMI_Handler(void)
71:Core/Src/stm32f4xx_it.c **** {
29 .loc 1 71 1 view -0
30 .cfi_startproc
31 @ Volatile: function does not return.
32 @ args = 0, pretend = 0, frame = 0
33 @ frame_needed = 0, uses_anonymous_args = 0
34 @ link register save eliminated.
35 .L2:
72:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
73:Core/Src/stm32f4xx_it.c ****
74:Core/Src/stm32f4xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 0 */
75:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
76:Core/Src/stm32f4xx_it.c **** while (1)
36 .loc 1 76 4 view .LVU1
77:Core/Src/stm32f4xx_it.c **** {
78:Core/Src/stm32f4xx_it.c **** }
37 .loc 1 78 3 view .LVU2
ARM GAS /tmp/cc7eGm0R.s page 3
76:Core/Src/stm32f4xx_it.c **** {
38 .loc 1 76 10 view .LVU3
39 0000 FEE7 b .L2
40 .cfi_endproc
41 .LFE239:
43 .section .text.HardFault_Handler,"ax",%progbits
44 .align 1
45 .global HardFault_Handler
46 .syntax unified
47 .thumb
48 .thumb_func
50 HardFault_Handler:
51 .LFB240:
79:Core/Src/stm32f4xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 1 */
80:Core/Src/stm32f4xx_it.c **** }
81:Core/Src/stm32f4xx_it.c ****
82:Core/Src/stm32f4xx_it.c **** /**
83:Core/Src/stm32f4xx_it.c **** * @brief This function handles Hard fault interrupt.
84:Core/Src/stm32f4xx_it.c **** */
85:Core/Src/stm32f4xx_it.c **** void HardFault_Handler(void)
86:Core/Src/stm32f4xx_it.c **** {
52 .loc 1 86 1 view -0
53 .cfi_startproc
54 @ Volatile: function does not return.
55 @ args = 0, pretend = 0, frame = 0
56 @ frame_needed = 0, uses_anonymous_args = 0
57 @ link register save eliminated.
58 .L4:
87:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN HardFault_IRQn 0 */
88:Core/Src/stm32f4xx_it.c ****
89:Core/Src/stm32f4xx_it.c **** /* USER CODE END HardFault_IRQn 0 */
90:Core/Src/stm32f4xx_it.c **** while (1)
59 .loc 1 90 3 view .LVU5
91:Core/Src/stm32f4xx_it.c **** {
92:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_HardFault_IRQn 0 */
93:Core/Src/stm32f4xx_it.c **** /* USER CODE END W1_HardFault_IRQn 0 */
94:Core/Src/stm32f4xx_it.c **** }
60 .loc 1 94 3 view .LVU6
90:Core/Src/stm32f4xx_it.c **** {
61 .loc 1 90 9 view .LVU7
62 0000 FEE7 b .L4
63 .cfi_endproc
64 .LFE240:
66 .section .text.MemManage_Handler,"ax",%progbits
67 .align 1
68 .global MemManage_Handler
69 .syntax unified
70 .thumb
71 .thumb_func
73 MemManage_Handler:
74 .LFB241:
95:Core/Src/stm32f4xx_it.c **** }
96:Core/Src/stm32f4xx_it.c ****
97:Core/Src/stm32f4xx_it.c **** /**
98:Core/Src/stm32f4xx_it.c **** * @brief This function handles Memory management fault.
99:Core/Src/stm32f4xx_it.c **** */
100:Core/Src/stm32f4xx_it.c **** void MemManage_Handler(void)
ARM GAS /tmp/cc7eGm0R.s page 4
101:Core/Src/stm32f4xx_it.c **** {
75 .loc 1 101 1 view -0
76 .cfi_startproc
77 @ Volatile: function does not return.
78 @ args = 0, pretend = 0, frame = 0
79 @ frame_needed = 0, uses_anonymous_args = 0
80 @ link register save eliminated.
81 .L6:
102:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN MemoryManagement_IRQn 0 */
103:Core/Src/stm32f4xx_it.c ****
104:Core/Src/stm32f4xx_it.c **** /* USER CODE END MemoryManagement_IRQn 0 */
105:Core/Src/stm32f4xx_it.c **** while (1)
82 .loc 1 105 3 view .LVU9
106:Core/Src/stm32f4xx_it.c **** {
107:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
108:Core/Src/stm32f4xx_it.c **** /* USER CODE END W1_MemoryManagement_IRQn 0 */
109:Core/Src/stm32f4xx_it.c **** }
83 .loc 1 109 3 view .LVU10
105:Core/Src/stm32f4xx_it.c **** {
84 .loc 1 105 9 view .LVU11
85 0000 FEE7 b .L6
86 .cfi_endproc
87 .LFE241:
89 .section .text.BusFault_Handler,"ax",%progbits
90 .align 1
91 .global BusFault_Handler
92 .syntax unified
93 .thumb
94 .thumb_func
96 BusFault_Handler:
97 .LFB242:
110:Core/Src/stm32f4xx_it.c **** }
111:Core/Src/stm32f4xx_it.c ****
112:Core/Src/stm32f4xx_it.c **** /**
113:Core/Src/stm32f4xx_it.c **** * @brief This function handles Pre-fetch fault, memory access fault.
114:Core/Src/stm32f4xx_it.c **** */
115:Core/Src/stm32f4xx_it.c **** void BusFault_Handler(void)
116:Core/Src/stm32f4xx_it.c **** {
98 .loc 1 116 1 view -0
99 .cfi_startproc
100 @ Volatile: function does not return.
101 @ args = 0, pretend = 0, frame = 0
102 @ frame_needed = 0, uses_anonymous_args = 0
103 @ link register save eliminated.
104 .L8:
117:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN BusFault_IRQn 0 */
118:Core/Src/stm32f4xx_it.c ****
119:Core/Src/stm32f4xx_it.c **** /* USER CODE END BusFault_IRQn 0 */
120:Core/Src/stm32f4xx_it.c **** while (1)
105 .loc 1 120 3 view .LVU13
121:Core/Src/stm32f4xx_it.c **** {
122:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_BusFault_IRQn 0 */
123:Core/Src/stm32f4xx_it.c **** /* USER CODE END W1_BusFault_IRQn 0 */
124:Core/Src/stm32f4xx_it.c **** }
106 .loc 1 124 3 view .LVU14
120:Core/Src/stm32f4xx_it.c **** {
107 .loc 1 120 9 view .LVU15
ARM GAS /tmp/cc7eGm0R.s page 5
108 0000 FEE7 b .L8
109 .cfi_endproc
110 .LFE242:
112 .section .text.UsageFault_Handler,"ax",%progbits
113 .align 1
114 .global UsageFault_Handler
115 .syntax unified
116 .thumb
117 .thumb_func
119 UsageFault_Handler:
120 .LFB243:
125:Core/Src/stm32f4xx_it.c **** }
126:Core/Src/stm32f4xx_it.c ****
127:Core/Src/stm32f4xx_it.c **** /**
128:Core/Src/stm32f4xx_it.c **** * @brief This function handles Undefined instruction or illegal state.
129:Core/Src/stm32f4xx_it.c **** */
130:Core/Src/stm32f4xx_it.c **** void UsageFault_Handler(void)
131:Core/Src/stm32f4xx_it.c **** {
121 .loc 1 131 1 view -0
122 .cfi_startproc
123 @ Volatile: function does not return.
124 @ args = 0, pretend = 0, frame = 0
125 @ frame_needed = 0, uses_anonymous_args = 0
126 @ link register save eliminated.
127 .L10:
132:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN UsageFault_IRQn 0 */
133:Core/Src/stm32f4xx_it.c ****
134:Core/Src/stm32f4xx_it.c **** /* USER CODE END UsageFault_IRQn 0 */
135:Core/Src/stm32f4xx_it.c **** while (1)
128 .loc 1 135 3 view .LVU17
136:Core/Src/stm32f4xx_it.c **** {
137:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
138:Core/Src/stm32f4xx_it.c **** /* USER CODE END W1_UsageFault_IRQn 0 */
139:Core/Src/stm32f4xx_it.c **** }
129 .loc 1 139 3 view .LVU18
135:Core/Src/stm32f4xx_it.c **** {
130 .loc 1 135 9 view .LVU19
131 0000 FEE7 b .L10
132 .cfi_endproc
133 .LFE243:
135 .section .text.SVC_Handler,"ax",%progbits
136 .align 1
137 .global SVC_Handler
138 .syntax unified
139 .thumb
140 .thumb_func
142 SVC_Handler:
143 .LFB244:
140:Core/Src/stm32f4xx_it.c **** }
141:Core/Src/stm32f4xx_it.c ****
142:Core/Src/stm32f4xx_it.c **** /**
143:Core/Src/stm32f4xx_it.c **** * @brief This function handles System service call via SWI instruction.
144:Core/Src/stm32f4xx_it.c **** */
145:Core/Src/stm32f4xx_it.c **** void SVC_Handler(void)
146:Core/Src/stm32f4xx_it.c **** {
144 .loc 1 146 1 view -0
145 .cfi_startproc
ARM GAS /tmp/cc7eGm0R.s page 6
146 @ args = 0, pretend = 0, frame = 0
147 @ frame_needed = 0, uses_anonymous_args = 0
148 @ link register save eliminated.
147:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 0 */
148:Core/Src/stm32f4xx_it.c ****
149:Core/Src/stm32f4xx_it.c **** /* USER CODE END SVCall_IRQn 0 */
150:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 1 */
151:Core/Src/stm32f4xx_it.c ****
152:Core/Src/stm32f4xx_it.c **** /* USER CODE END SVCall_IRQn 1 */
153:Core/Src/stm32f4xx_it.c **** }
149 .loc 1 153 1 view .LVU21
150 0000 7047 bx lr
151 .cfi_endproc
152 .LFE244:
154 .section .text.DebugMon_Handler,"ax",%progbits
155 .align 1
156 .global DebugMon_Handler
157 .syntax unified
158 .thumb
159 .thumb_func
161 DebugMon_Handler:
162 .LFB245:
154:Core/Src/stm32f4xx_it.c ****
155:Core/Src/stm32f4xx_it.c **** /**
156:Core/Src/stm32f4xx_it.c **** * @brief This function handles Debug monitor.
157:Core/Src/stm32f4xx_it.c **** */
158:Core/Src/stm32f4xx_it.c **** void DebugMon_Handler(void)
159:Core/Src/stm32f4xx_it.c **** {
163 .loc 1 159 1 view -0
164 .cfi_startproc
165 @ args = 0, pretend = 0, frame = 0
166 @ frame_needed = 0, uses_anonymous_args = 0
167 @ link register save eliminated.
160:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 0 */
161:Core/Src/stm32f4xx_it.c ****
162:Core/Src/stm32f4xx_it.c **** /* USER CODE END DebugMonitor_IRQn 0 */
163:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 1 */
164:Core/Src/stm32f4xx_it.c ****
165:Core/Src/stm32f4xx_it.c **** /* USER CODE END DebugMonitor_IRQn 1 */
166:Core/Src/stm32f4xx_it.c **** }
168 .loc 1 166 1 view .LVU23
169 0000 7047 bx lr
170 .cfi_endproc
171 .LFE245:
173 .section .text.PendSV_Handler,"ax",%progbits
174 .align 1
175 .global PendSV_Handler
176 .syntax unified
177 .thumb
178 .thumb_func
180 PendSV_Handler:
181 .LFB246:
167:Core/Src/stm32f4xx_it.c ****
168:Core/Src/stm32f4xx_it.c **** /**
169:Core/Src/stm32f4xx_it.c **** * @brief This function handles Pendable request for system service.
170:Core/Src/stm32f4xx_it.c **** */
171:Core/Src/stm32f4xx_it.c **** void PendSV_Handler(void)
ARM GAS /tmp/cc7eGm0R.s page 7
172:Core/Src/stm32f4xx_it.c **** {
182 .loc 1 172 1 view -0
183 .cfi_startproc
184 @ args = 0, pretend = 0, frame = 0
185 @ frame_needed = 0, uses_anonymous_args = 0
186 @ link register save eliminated.
173:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 0 */
174:Core/Src/stm32f4xx_it.c ****
175:Core/Src/stm32f4xx_it.c **** /* USER CODE END PendSV_IRQn 0 */
176:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 1 */
177:Core/Src/stm32f4xx_it.c ****
178:Core/Src/stm32f4xx_it.c **** /* USER CODE END PendSV_IRQn 1 */
179:Core/Src/stm32f4xx_it.c **** }
187 .loc 1 179 1 view .LVU25
188 0000 7047 bx lr
189 .cfi_endproc
190 .LFE246:
192 .section .text.SysTick_Handler,"ax",%progbits
193 .align 1
194 .global SysTick_Handler
195 .syntax unified
196 .thumb
197 .thumb_func
199 SysTick_Handler:
200 .LFB247:
180:Core/Src/stm32f4xx_it.c ****
181:Core/Src/stm32f4xx_it.c **** /**
182:Core/Src/stm32f4xx_it.c **** * @brief This function handles System tick timer.
183:Core/Src/stm32f4xx_it.c **** */
184:Core/Src/stm32f4xx_it.c **** void SysTick_Handler(void)
185:Core/Src/stm32f4xx_it.c **** {
201 .loc 1 185 1 view -0
202 .cfi_startproc
203 @ args = 0, pretend = 0, frame = 0
204 @ frame_needed = 0, uses_anonymous_args = 0
205 0000 08B5 push {r3, lr}
206 .LCFI0:
207 .cfi_def_cfa_offset 8
208 .cfi_offset 3, -8
209 .cfi_offset 14, -4
186:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 0 */
187:Core/Src/stm32f4xx_it.c ****
188:Core/Src/stm32f4xx_it.c **** /* USER CODE END SysTick_IRQn 0 */
189:Core/Src/stm32f4xx_it.c **** HAL_IncTick();
210 .loc 1 189 3 view .LVU27
211 0002 FFF7FEFF bl HAL_IncTick
212 .LVL0:
190:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 1 */
191:Core/Src/stm32f4xx_it.c ****
192:Core/Src/stm32f4xx_it.c **** /* USER CODE END SysTick_IRQn 1 */
193:Core/Src/stm32f4xx_it.c **** }
213 .loc 1 193 1 is_stmt 0 view .LVU28
214 0006 08BD pop {r3, pc}
215 .cfi_endproc
216 .LFE247:
218 .section .text.EXTI0_IRQHandler,"ax",%progbits
219 .align 1
ARM GAS /tmp/cc7eGm0R.s page 8
220 .global EXTI0_IRQHandler
221 .syntax unified
222 .thumb
223 .thumb_func
225 EXTI0_IRQHandler:
226 .LFB248:
194:Core/Src/stm32f4xx_it.c ****
195:Core/Src/stm32f4xx_it.c **** /******************************************************************************/
196:Core/Src/stm32f4xx_it.c **** /* STM32F4xx Peripheral Interrupt Handlers */
197:Core/Src/stm32f4xx_it.c **** /* Add here the Interrupt Handlers for the used peripherals. */
198:Core/Src/stm32f4xx_it.c **** /* For the available peripheral interrupt handler names, */
199:Core/Src/stm32f4xx_it.c **** /* please refer to the startup file (startup_stm32f4xx.s). */
200:Core/Src/stm32f4xx_it.c **** /******************************************************************************/
201:Core/Src/stm32f4xx_it.c ****
202:Core/Src/stm32f4xx_it.c **** /**
203:Core/Src/stm32f4xx_it.c **** * @brief This function handles EXTI line0 interrupt.
204:Core/Src/stm32f4xx_it.c **** */
205:Core/Src/stm32f4xx_it.c **** void EXTI0_IRQHandler(void)
206:Core/Src/stm32f4xx_it.c **** {
227 .loc 1 206 1 is_stmt 1 view -0
228 .cfi_startproc
229 @ args = 0, pretend = 0, frame = 0
230 @ frame_needed = 0, uses_anonymous_args = 0
231 0000 08B5 push {r3, lr}
232 .LCFI1:
233 .cfi_def_cfa_offset 8
234 .cfi_offset 3, -8
235 .cfi_offset 14, -4
207:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN EXTI0_IRQn 0 */
208:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_start_DMA_N = ADC_BUFF_SIZE - hdma_adc1.Instance->NDTR;
236 .loc 1 208 3 view .LVU30
237 .loc 1 208 64 is_stmt 0 view .LVU31
238 0002 0C4B ldr r3, .L20
239 0004 1B68 ldr r3, [r3]
240 .loc 1 208 73 view .LVU32
241 0006 5B68 ldr r3, [r3, #4]
242 .loc 1 208 53 view .LVU33
243 0008 C3F14003 rsb r3, r3, #64
244 .loc 1 208 37 view .LVU34
245 000c 0A4A ldr r2, .L20+4
246 000e 9360 str r3, [r2, #8]
209:Core/Src/stm32f4xx_it.c **** if (Sweep_state.curr_step_start_DMA_N < ADC_BUFF_SIZE/2) {
247 .loc 1 209 3 is_stmt 1 view .LVU35
248 .loc 1 209 18 is_stmt 0 view .LVU36
249 0010 9368 ldr r3, [r2, #8]
250 .loc 1 209 6 view .LVU37
251 0012 1F2B cmp r3, #31
252 0014 0AD8 bhi .L17
210:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag =1; // first half DMA buffer
253 .loc 1 210 5 is_stmt 1 view .LVU38
254 .loc 1 210 40 is_stmt 0 view .LVU39
255 0016 1346 mov r3, r2
256 0018 0122 movs r2, #1
257 001a 1A71 strb r2, [r3, #4]
258 .L18:
211:Core/Src/stm32f4xx_it.c **** } else{
212:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag =2; // second half DMA buffer
ARM GAS /tmp/cc7eGm0R.s page 9
213:Core/Src/stm32f4xx_it.c **** }
214:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_N++;
259 .loc 1 214 3 is_stmt 1 view .LVU40
260 .loc 1 214 14 is_stmt 0 view .LVU41
261 001c 064A ldr r2, .L20+4
262 001e 1368 ldr r3, [r2]
263 .loc 1 214 26 view .LVU42
264 0020 0133 adds r3, r3, #1
265 0022 1360 str r3, [r2]
215:Core/Src/stm32f4xx_it.c **** /* USER CODE END EXTI0_IRQn 0 */
216:Core/Src/stm32f4xx_it.c **** HAL_GPIO_EXTI_IRQHandler(CURR_STEP_START_TRG_Pin);
266 .loc 1 216 3 is_stmt 1 view .LVU43
267 0024 0120 movs r0, #1
268 0026 FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler
269 .LVL1:
217:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN EXTI0_IRQn 1 */
218:Core/Src/stm32f4xx_it.c ****
219:Core/Src/stm32f4xx_it.c **** /* USER CODE END EXTI0_IRQn 1 */
220:Core/Src/stm32f4xx_it.c **** }
270 .loc 1 220 1 is_stmt 0 view .LVU44
271 002a 08BD pop {r3, pc}
272 .L17:
212:Core/Src/stm32f4xx_it.c **** }
273 .loc 1 212 5 is_stmt 1 view .LVU45
212:Core/Src/stm32f4xx_it.c **** }
274 .loc 1 212 40 is_stmt 0 view .LVU46
275 002c 024B ldr r3, .L20+4
276 002e 0222 movs r2, #2
277 0030 1A71 strb r2, [r3, #4]
278 0032 F3E7 b .L18
279 .L21:
280 .align 2
281 .L20:
282 0034 00000000 .word hdma_adc1
283 0038 00000000 .word Sweep_state
284 .cfi_endproc
285 .LFE248:
287 .section .text.EXTI3_IRQHandler,"ax",%progbits
288 .align 1
289 .global EXTI3_IRQHandler
290 .syntax unified
291 .thumb
292 .thumb_func
294 EXTI3_IRQHandler:
295 .LFB249:
221:Core/Src/stm32f4xx_it.c ****
222:Core/Src/stm32f4xx_it.c **** /**
223:Core/Src/stm32f4xx_it.c **** * @brief This function handles EXTI line3 interrupt.
224:Core/Src/stm32f4xx_it.c **** */
225:Core/Src/stm32f4xx_it.c **** void EXTI3_IRQHandler(void)
226:Core/Src/stm32f4xx_it.c **** {
296 .loc 1 226 1 is_stmt 1 view -0
297 .cfi_startproc
298 @ args = 0, pretend = 0, frame = 0
299 @ frame_needed = 0, uses_anonymous_args = 0
300 0000 08B5 push {r3, lr}
301 .LCFI2:
ARM GAS /tmp/cc7eGm0R.s page 10
302 .cfi_def_cfa_offset 8
303 .cfi_offset 3, -8
304 .cfi_offset 14, -4
227:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN EXTI3_IRQn 0 */
228:Core/Src/stm32f4xx_it.c **** Sweep_state.sweep_cycle_started_flag = 1; //sweep cycle started
305 .loc 1 228 3 view .LVU48
306 .loc 1 228 40 is_stmt 0 view .LVU49
307 0002 044B ldr r3, .L24
308 0004 0122 movs r2, #1
309 0006 1A73 strb r2, [r3, #12]
229:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_N = 0;
310 .loc 1 229 3 is_stmt 1 view .LVU50
311 .loc 1 229 27 is_stmt 0 view .LVU51
312 0008 0022 movs r2, #0
313 000a 1A60 str r2, [r3]
230:Core/Src/stm32f4xx_it.c **** /* USER CODE END EXTI3_IRQn 0 */
231:Core/Src/stm32f4xx_it.c **** HAL_GPIO_EXTI_IRQHandler(SWEEP_CYCLE_START_TRG_Pin);
314 .loc 1 231 3 is_stmt 1 view .LVU52
315 000c 0820 movs r0, #8
316 000e FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler
317 .LVL2:
232:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN EXTI3_IRQn 1 */
233:Core/Src/stm32f4xx_it.c ****
234:Core/Src/stm32f4xx_it.c **** /* USER CODE END EXTI3_IRQn 1 */
235:Core/Src/stm32f4xx_it.c **** }
318 .loc 1 235 1 is_stmt 0 view .LVU53
319 0012 08BD pop {r3, pc}
320 .L25:
321 .align 2
322 .L24:
323 0014 00000000 .word Sweep_state
324 .cfi_endproc
325 .LFE249:
327 .section .text.DMA2_Stream0_IRQHandler,"ax",%progbits
328 .align 1
329 .global DMA2_Stream0_IRQHandler
330 .syntax unified
331 .thumb
332 .thumb_func
334 DMA2_Stream0_IRQHandler:
335 .LFB250:
236:Core/Src/stm32f4xx_it.c ****
237:Core/Src/stm32f4xx_it.c **** /**
238:Core/Src/stm32f4xx_it.c **** * @brief This function handles DMA2 stream0 global interrupt.
239:Core/Src/stm32f4xx_it.c **** */
240:Core/Src/stm32f4xx_it.c **** void DMA2_Stream0_IRQHandler(void)
241:Core/Src/stm32f4xx_it.c **** {
336 .loc 1 241 1 is_stmt 1 view -0
337 .cfi_startproc
338 @ args = 0, pretend = 0, frame = 0
339 @ frame_needed = 0, uses_anonymous_args = 0
340 0000 08B5 push {r3, lr}
341 .LCFI3:
342 .cfi_def_cfa_offset 8
343 .cfi_offset 3, -8
344 .cfi_offset 14, -4
242:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN DMA2_Stream0_IRQn 0 */
ARM GAS /tmp/cc7eGm0R.s page 11
243:Core/Src/stm32f4xx_it.c ****
244:Core/Src/stm32f4xx_it.c **** /* USER CODE END DMA2_Stream0_IRQn 0 */
245:Core/Src/stm32f4xx_it.c **** HAL_DMA_IRQHandler(&hdma_adc1);
345 .loc 1 245 3 view .LVU55
346 0002 0248 ldr r0, .L28
347 0004 FFF7FEFF bl HAL_DMA_IRQHandler
348 .LVL3:
246:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN DMA2_Stream0_IRQn 1 */
247:Core/Src/stm32f4xx_it.c ****
248:Core/Src/stm32f4xx_it.c **** /* USER CODE END DMA2_Stream0_IRQn 1 */
249:Core/Src/stm32f4xx_it.c **** }
349 .loc 1 249 1 is_stmt 0 view .LVU56
350 0008 08BD pop {r3, pc}
351 .L29:
352 000a 00BF .align 2
353 .L28:
354 000c 00000000 .word hdma_adc1
355 .cfi_endproc
356 .LFE250:
358 .section .text.OTG_FS_IRQHandler,"ax",%progbits
359 .align 1
360 .global OTG_FS_IRQHandler
361 .syntax unified
362 .thumb
363 .thumb_func
365 OTG_FS_IRQHandler:
366 .LFB251:
250:Core/Src/stm32f4xx_it.c ****
251:Core/Src/stm32f4xx_it.c **** /**
252:Core/Src/stm32f4xx_it.c **** * @brief This function handles USB On The Go FS global interrupt.
253:Core/Src/stm32f4xx_it.c **** */
254:Core/Src/stm32f4xx_it.c **** void OTG_FS_IRQHandler(void)
255:Core/Src/stm32f4xx_it.c **** {
367 .loc 1 255 1 is_stmt 1 view -0
368 .cfi_startproc
369 @ args = 0, pretend = 0, frame = 0
370 @ frame_needed = 0, uses_anonymous_args = 0
371 0000 08B5 push {r3, lr}
372 .LCFI4:
373 .cfi_def_cfa_offset 8
374 .cfi_offset 3, -8
375 .cfi_offset 14, -4
256:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN OTG_FS_IRQn 0 */
257:Core/Src/stm32f4xx_it.c ****
258:Core/Src/stm32f4xx_it.c **** /* USER CODE END OTG_FS_IRQn 0 */
259:Core/Src/stm32f4xx_it.c **** HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS);
376 .loc 1 259 3 view .LVU58
377 0002 0248 ldr r0, .L32
378 0004 FFF7FEFF bl HAL_PCD_IRQHandler
379 .LVL4:
260:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN OTG_FS_IRQn 1 */
261:Core/Src/stm32f4xx_it.c ****
262:Core/Src/stm32f4xx_it.c **** /* USER CODE END OTG_FS_IRQn 1 */
263:Core/Src/stm32f4xx_it.c **** }
380 .loc 1 263 1 is_stmt 0 view .LVU59
381 0008 08BD pop {r3, pc}
382 .L33:
ARM GAS /tmp/cc7eGm0R.s page 12
383 000a 00BF .align 2
384 .L32:
385 000c 00000000 .word hpcd_USB_OTG_FS
386 .cfi_endproc
387 .LFE251:
389 .section .text.HAL_ADC_ConvCpltCallback,"ax",%progbits
390 .align 1
391 .global HAL_ADC_ConvCpltCallback
392 .syntax unified
393 .thumb
394 .thumb_func
396 HAL_ADC_ConvCpltCallback:
397 .LVL5:
398 .LFB252:
264:Core/Src/stm32f4xx_it.c ****
265:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN 1 */
266:Core/Src/stm32f4xx_it.c ****
267:Core/Src/stm32f4xx_it.c **** #ifdef SYNC_DET_ON
268:Core/Src/stm32f4xx_it.c ****
269:Core/Src/stm32f4xx_it.c ****
270:Core/Src/stm32f4xx_it.c ****
271:Core/Src/stm32f4xx_it.c ****
272:Core/Src/stm32f4xx_it.c **** void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
273:Core/Src/stm32f4xx_it.c **** {
399 .loc 1 273 1 is_stmt 1 view -0
400 .cfi_startproc
401 @ args = 0, pretend = 0, frame = 0
402 @ frame_needed = 0, uses_anonymous_args = 0
403 .loc 1 273 1 is_stmt 0 view .LVU61
404 0000 08B5 push {r3, lr}
405 .LCFI5:
406 .cfi_def_cfa_offset 8
407 .cfi_offset 3, -8
408 .cfi_offset 14, -4
274:Core/Src/stm32f4xx_it.c **** HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_SET);
409 .loc 1 274 3 is_stmt 1 view .LVU62
410 0002 0122 movs r2, #1
411 0004 8021 movs r1, #128
412 0006 4C48 ldr r0, .L55
413 .LVL6:
414 .loc 1 274 3 is_stmt 0 view .LVU63
415 0008 FFF7FEFF bl HAL_GPIO_WritePin
416 .LVL7:
275:Core/Src/stm32f4xx_it.c ****
276:Core/Src/stm32f4xx_it.c **** if (Sweep_state.curr_step_started_flag == 2) {
417 .loc 1 276 3 is_stmt 1 view .LVU64
418 .loc 1 276 18 is_stmt 0 view .LVU65
419 000c 4B4B ldr r3, .L55+4
420 000e 1B79 ldrb r3, [r3, #4] @ zero_extendqisi2
421 0010 DBB2 uxtb r3, r3
422 .loc 1 276 6 view .LVU66
423 0012 022B cmp r3, #2
424 0014 01D0 beq .L51
425 .LBB2:
277:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag = 0; // reset flag after processing second half
278:Core/Src/stm32f4xx_it.c **** for (uint32_t i = ADC_BUFF_SIZE/2; i < Sweep_state.curr_step_start_DMA_N; i++) {
279:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
ARM GAS /tmp/cc7eGm0R.s page 13
280:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
281:Core/Src/stm32f4xx_it.c **** }else{
282:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF += ADC1_buff_circular[i];
283:Core/Src/stm32f4xx_it.c **** }
284:Core/Src/stm32f4xx_it.c **** }
285:Core/Src/stm32f4xx_it.c ****
286:Core/Src/stm32f4xx_it.c **** ADC_proc.N += (Sweep_state.curr_step_start_DMA_N - ADC_BUFF_SIZE/2)/2;
287:Core/Src/stm32f4xx_it.c ****
288:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_ON = ADC_proc.sum_ON;
289:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
290:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
291:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
292:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
293:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
294:Core/Src/stm32f4xx_it.c ****
295:Core/Src/stm32f4xx_it.c ****
296:Core/Src/stm32f4xx_it.c **** ADC_proc.sum = 0;
297:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON = 0;
298:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF = 0;
299:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0;
300:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_ON = 0;
301:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_OFF = 0;
302:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data
303:Core/Src/stm32f4xx_it.c ****
304:Core/Src/stm32f4xx_it.c **** for (uint32_t i = Sweep_state.curr_step_start_DMA_N; i < ADC_BUFF_SIZE; i++) {
305:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
306:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
307:Core/Src/stm32f4xx_it.c **** }else{
308:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF += ADC1_buff_circular[i];
309:Core/Src/stm32f4xx_it.c **** }
310:Core/Src/stm32f4xx_it.c **** }
311:Core/Src/stm32f4xx_it.c **** ADC_proc.N = (ADC_BUFF_SIZE - Sweep_state.curr_step_start_DMA_N)/2;
312:Core/Src/stm32f4xx_it.c ****
313:Core/Src/stm32f4xx_it.c ****
314:Core/Src/stm32f4xx_it.c **** }else{
315:Core/Src/stm32f4xx_it.c **** for (uint32_t i = ADC_BUFF_SIZE/2; i < ADC_BUFF_SIZE; i++) {
426 .loc 1 315 19 view .LVU67
427 0016 2023 movs r3, #32
428 0018 60E0 b .L35
429 .L51:
430 .LBE2:
277:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag = 0; // reset flag after processing second half
431 .loc 1 277 5 is_stmt 1 view .LVU68
277:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag = 0; // reset flag after processing second half
432 .loc 1 277 40 is_stmt 0 view .LVU69
433 001a 484B ldr r3, .L55+4
434 001c 0022 movs r2, #0
435 001e 1A71 strb r2, [r3, #4]
278:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
436 .loc 1 278 5 is_stmt 1 view .LVU70
437 .LBB3:
278:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
438 .loc 1 278 10 view .LVU71
439 .LVL8:
278:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
440 .loc 1 278 19 is_stmt 0 view .LVU72
441 0020 2023 movs r3, #32
ARM GAS /tmp/cc7eGm0R.s page 14
278:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
442 .loc 1 278 5 view .LVU73
443 0022 07E0 b .L36
444 .LVL9:
445 .L37:
282:Core/Src/stm32f4xx_it.c **** }
446 .loc 1 282 9 is_stmt 1 view .LVU74
282:Core/Src/stm32f4xx_it.c **** }
447 .loc 1 282 17 is_stmt 0 view .LVU75
448 0024 4649 ldr r1, .L55+8
449 0026 CA68 ldr r2, [r1, #12]
282:Core/Src/stm32f4xx_it.c **** }
450 .loc 1 282 47 view .LVU76
451 0028 4648 ldr r0, .L55+12
452 002a 30F81300 ldrh r0, [r0, r3, lsl #1]
282:Core/Src/stm32f4xx_it.c **** }
453 .loc 1 282 26 view .LVU77
454 002e 0244 add r2, r2, r0
455 0030 CA60 str r2, [r1, #12]
456 .L38:
278:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
457 .loc 1 278 80 is_stmt 1 discriminator 2 view .LVU78
458 0032 0133 adds r3, r3, #1
459 .LVL10:
460 .L36:
278:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
461 .loc 1 278 42 discriminator 1 view .LVU79
278:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
462 .loc 1 278 55 is_stmt 0 discriminator 1 view .LVU80
463 0034 414A ldr r2, .L55+4
464 0036 9268 ldr r2, [r2, #8]
278:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
465 .loc 1 278 42 discriminator 1 view .LVU81
466 0038 9A42 cmp r2, r3
467 003a 0AD9 bls .L52
279:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
468 .loc 1 279 7 is_stmt 1 view .LVU82
279:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
469 .loc 1 279 10 is_stmt 0 view .LVU83
470 003c 13F0010F tst r3, #1
471 0040 F0D0 beq .L37
280:Core/Src/stm32f4xx_it.c **** }else{
472 .loc 1 280 9 is_stmt 1 view .LVU84
280:Core/Src/stm32f4xx_it.c **** }else{
473 .loc 1 280 17 is_stmt 0 view .LVU85
474 0042 3F49 ldr r1, .L55+8
475 0044 8A68 ldr r2, [r1, #8]
280:Core/Src/stm32f4xx_it.c **** }else{
476 .loc 1 280 46 view .LVU86
477 0046 3F48 ldr r0, .L55+12
478 0048 30F81300 ldrh r0, [r0, r3, lsl #1]
280:Core/Src/stm32f4xx_it.c **** }else{
479 .loc 1 280 25 view .LVU87
480 004c 0244 add r2, r2, r0
481 004e 8A60 str r2, [r1, #8]
482 0050 EFE7 b .L38
483 .L52:
ARM GAS /tmp/cc7eGm0R.s page 15
484 .LBE3:
286:Core/Src/stm32f4xx_it.c ****
485 .loc 1 286 5 is_stmt 1 view .LVU88
286:Core/Src/stm32f4xx_it.c ****
486 .loc 1 286 31 is_stmt 0 view .LVU89
487 0052 3A48 ldr r0, .L55+4
488 0054 8168 ldr r1, [r0, #8]
286:Core/Src/stm32f4xx_it.c ****
489 .loc 1 286 54 view .LVU90
490 0056 2039 subs r1, r1, #32
286:Core/Src/stm32f4xx_it.c ****
491 .loc 1 286 13 view .LVU91
492 0058 394B ldr r3, .L55+8
493 .LVL11:
286:Core/Src/stm32f4xx_it.c ****
494 .loc 1 286 13 view .LVU92
495 005a 9A69 ldr r2, [r3, #24]
286:Core/Src/stm32f4xx_it.c ****
496 .loc 1 286 16 view .LVU93
497 005c 02EB5102 add r2, r2, r1, lsr #1
498 0060 9A61 str r2, [r3, #24]
288:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
499 .loc 1 288 5 is_stmt 1 view .LVU94
288:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
500 .loc 1 288 38 is_stmt 0 view .LVU95
501 0062 9968 ldr r1, [r3, #8]
288:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
502 .loc 1 288 28 view .LVU96
503 0064 384A ldr r2, .L55+16
504 0066 9160 str r1, [r2, #8]
289:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
505 .loc 1 289 5 is_stmt 1 view .LVU97
289:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
506 .loc 1 289 39 is_stmt 0 view .LVU98
507 0068 D968 ldr r1, [r3, #12]
289:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
508 .loc 1 289 29 view .LVU99
509 006a D160 str r1, [r2, #12]
290:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
510 .loc 1 290 5 is_stmt 1 view .LVU100
290:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
511 .loc 1 290 38 is_stmt 0 view .LVU101
512 006c 1969 ldr r1, [r3, #16]
290:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
513 .loc 1 290 28 view .LVU102
514 006e 1161 str r1, [r2, #16]
291:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
515 .loc 1 291 5 is_stmt 1 view .LVU103
291:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
516 .loc 1 291 39 is_stmt 0 view .LVU104
517 0070 5969 ldr r1, [r3, #20]
291:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
518 .loc 1 291 29 view .LVU105
519 0072 5161 str r1, [r2, #20]
292:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
520 .loc 1 292 5 is_stmt 1 view .LVU106
292:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
ARM GAS /tmp/cc7eGm0R.s page 16
521 .loc 1 292 33 is_stmt 0 view .LVU107
522 0074 9969 ldr r1, [r3, #24]
292:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
523 .loc 1 292 23 view .LVU108
524 0076 9161 str r1, [r2, #24]
293:Core/Src/stm32f4xx_it.c ****
525 .loc 1 293 5 is_stmt 1 view .LVU109
293:Core/Src/stm32f4xx_it.c ****
526 .loc 1 293 28 is_stmt 0 view .LVU110
527 0078 0221 movs r1, #2
528 007a 1170 strb r1, [r2]
296:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON = 0;
529 .loc 1 296 5 is_stmt 1 view .LVU111
296:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON = 0;
530 .loc 1 296 18 is_stmt 0 view .LVU112
531 007c 0022 movs r2, #0
532 007e 5A60 str r2, [r3, #4]
297:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF = 0;
533 .loc 1 297 5 is_stmt 1 view .LVU113
297:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF = 0;
534 .loc 1 297 21 is_stmt 0 view .LVU114
535 0080 9A60 str r2, [r3, #8]
298:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0;
536 .loc 1 298 5 is_stmt 1 view .LVU115
298:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0;
537 .loc 1 298 22 is_stmt 0 view .LVU116
538 0082 DA60 str r2, [r3, #12]
299:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_ON = 0;
539 .loc 1 299 5 is_stmt 1 view .LVU117
299:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_ON = 0;
540 .loc 1 299 16 is_stmt 0 view .LVU118
541 0084 9A61 str r2, [r3, #24]
300:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_OFF = 0;
542 .loc 1 300 5 is_stmt 1 view .LVU119
300:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_OFF = 0;
543 .loc 1 300 21 is_stmt 0 view .LVU120
544 0086 1A61 str r2, [r3, #16]
301:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data
545 .loc 1 301 5 is_stmt 1 view .LVU121
301:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data
546 .loc 1 301 22 is_stmt 0 view .LVU122
547 0088 5A61 str r2, [r3, #20]
302:Core/Src/stm32f4xx_it.c ****
548 .loc 1 302 5 is_stmt 1 view .LVU123
302:Core/Src/stm32f4xx_it.c ****
549 .loc 1 302 21 is_stmt 0 view .LVU124
550 008a 0122 movs r2, #1
551 008c 1A70 strb r2, [r3]
304:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
552 .loc 1 304 5 is_stmt 1 view .LVU125
553 .LBB4:
304:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
554 .loc 1 304 10 view .LVU126
304:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
555 .loc 1 304 19 is_stmt 0 view .LVU127
556 008e 8368 ldr r3, [r0, #8]
557 .LVL12:
ARM GAS /tmp/cc7eGm0R.s page 17
304:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
558 .loc 1 304 5 view .LVU128
559 0090 07E0 b .L40
560 .L41:
308:Core/Src/stm32f4xx_it.c **** }
561 .loc 1 308 9 is_stmt 1 view .LVU129
308:Core/Src/stm32f4xx_it.c **** }
562 .loc 1 308 17 is_stmt 0 view .LVU130
563 0092 2B49 ldr r1, .L55+8
564 0094 CA68 ldr r2, [r1, #12]
308:Core/Src/stm32f4xx_it.c **** }
565 .loc 1 308 47 view .LVU131
566 0096 2B48 ldr r0, .L55+12
567 0098 30F81300 ldrh r0, [r0, r3, lsl #1]
308:Core/Src/stm32f4xx_it.c **** }
568 .loc 1 308 26 view .LVU132
569 009c 0244 add r2, r2, r0
570 009e CA60 str r2, [r1, #12]
571 .L42:
304:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
572 .loc 1 304 78 is_stmt 1 discriminator 2 view .LVU133
573 00a0 0133 adds r3, r3, #1
574 .LVL13:
575 .L40:
304:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
576 .loc 1 304 60 discriminator 1 view .LVU134
577 00a2 3F2B cmp r3, #63
578 00a4 0AD8 bhi .L53
305:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
579 .loc 1 305 7 view .LVU135
305:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
580 .loc 1 305 10 is_stmt 0 view .LVU136
581 00a6 13F0010F tst r3, #1
582 00aa F2D0 beq .L41
306:Core/Src/stm32f4xx_it.c **** }else{
583 .loc 1 306 9 is_stmt 1 view .LVU137
306:Core/Src/stm32f4xx_it.c **** }else{
584 .loc 1 306 17 is_stmt 0 view .LVU138
585 00ac 2449 ldr r1, .L55+8
586 00ae 8A68 ldr r2, [r1, #8]
306:Core/Src/stm32f4xx_it.c **** }else{
587 .loc 1 306 46 view .LVU139
588 00b0 2448 ldr r0, .L55+12
589 00b2 30F81300 ldrh r0, [r0, r3, lsl #1]
306:Core/Src/stm32f4xx_it.c **** }else{
590 .loc 1 306 25 view .LVU140
591 00b6 0244 add r2, r2, r0
592 00b8 8A60 str r2, [r1, #8]
593 00ba F1E7 b .L42
594 .L53:
595 .LBE4:
311:Core/Src/stm32f4xx_it.c ****
596 .loc 1 311 5 is_stmt 1 view .LVU141
311:Core/Src/stm32f4xx_it.c ****
597 .loc 1 311 46 is_stmt 0 view .LVU142
598 00bc 1F4B ldr r3, .L55+4
599 .LVL14:
ARM GAS /tmp/cc7eGm0R.s page 18
311:Core/Src/stm32f4xx_it.c ****
600 .loc 1 311 46 view .LVU143
601 00be 9B68 ldr r3, [r3, #8]
311:Core/Src/stm32f4xx_it.c ****
602 .loc 1 311 33 view .LVU144
603 00c0 C3F14003 rsb r3, r3, #64
311:Core/Src/stm32f4xx_it.c ****
604 .loc 1 311 69 view .LVU145
605 00c4 5B08 lsrs r3, r3, #1
311:Core/Src/stm32f4xx_it.c ****
606 .loc 1 311 16 view .LVU146
607 00c6 1E4A ldr r2, .L55+8
608 00c8 9361 str r3, [r2, #24]
609 00ca 18E0 b .L44
610 .LVL15:
611 .L45:
612 .LBB5:
316:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
317:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
318:Core/Src/stm32f4xx_it.c **** }else{
319:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF += ADC1_buff_circular[i];
613 .loc 1 319 9 is_stmt 1 view .LVU147
614 .loc 1 319 17 is_stmt 0 view .LVU148
615 00cc 1C49 ldr r1, .L55+8
616 00ce CA68 ldr r2, [r1, #12]
617 .loc 1 319 47 view .LVU149
618 00d0 1C48 ldr r0, .L55+12
619 00d2 30F81300 ldrh r0, [r0, r3, lsl #1]
620 .loc 1 319 26 view .LVU150
621 00d6 0244 add r2, r2, r0
622 00d8 CA60 str r2, [r1, #12]
623 .L46:
315:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
624 .loc 1 315 60 is_stmt 1 discriminator 2 view .LVU151
625 00da 0133 adds r3, r3, #1
626 .LVL16:
627 .L35:
315:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
628 .loc 1 315 42 discriminator 1 view .LVU152
629 00dc 3F2B cmp r3, #63
630 00de 0AD8 bhi .L54
316:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
631 .loc 1 316 7 view .LVU153
316:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
632 .loc 1 316 10 is_stmt 0 view .LVU154
633 00e0 13F0010F tst r3, #1
634 00e4 F2D0 beq .L45
317:Core/Src/stm32f4xx_it.c **** }else{
635 .loc 1 317 9 is_stmt 1 view .LVU155
317:Core/Src/stm32f4xx_it.c **** }else{
636 .loc 1 317 17 is_stmt 0 view .LVU156
637 00e6 1649 ldr r1, .L55+8
638 00e8 8A68 ldr r2, [r1, #8]
317:Core/Src/stm32f4xx_it.c **** }else{
639 .loc 1 317 46 view .LVU157
640 00ea 1648 ldr r0, .L55+12
641 00ec 30F81300 ldrh r0, [r0, r3, lsl #1]
ARM GAS /tmp/cc7eGm0R.s page 19
317:Core/Src/stm32f4xx_it.c **** }else{
642 .loc 1 317 25 view .LVU158
643 00f0 0244 add r2, r2, r0
644 00f2 8A60 str r2, [r1, #8]
645 00f4 F1E7 b .L46
646 .L54:
647 .LBE5:
320:Core/Src/stm32f4xx_it.c **** }
321:Core/Src/stm32f4xx_it.c **** }
322:Core/Src/stm32f4xx_it.c **** ADC_proc.N += (ADC_BUFF_SIZE - ADC_BUFF_SIZE/2)/2;
648 .loc 1 322 5 is_stmt 1 view .LVU159
649 .loc 1 322 13 is_stmt 0 view .LVU160
650 00f6 124A ldr r2, .L55+8
651 00f8 9369 ldr r3, [r2, #24]
652 .LVL17:
653 .loc 1 322 16 view .LVU161
654 00fa 1033 adds r3, r3, #16
655 00fc 9361 str r3, [r2, #24]
656 .LVL18:
657 .L44:
323:Core/Src/stm32f4xx_it.c **** }
324:Core/Src/stm32f4xx_it.c ****
325:Core/Src/stm32f4xx_it.c **** //if (0){
326:Core/Src/stm32f4xx_it.c **** if (ADC_proc.N >= ADC_BUFF_SIZE*100){
658 .loc 1 326 3 is_stmt 1 view .LVU162
659 .loc 1 326 15 is_stmt 0 view .LVU163
660 00fe 104B ldr r3, .L55+8
661 0100 9B69 ldr r3, [r3, #24]
662 .loc 1 326 6 view .LVU164
663 0102 B3F5C85F cmp r3, #6400
664 0106 15D3 bcc .L34
327:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
665 .loc 1 327 5 is_stmt 1 view .LVU165
666 .loc 1 327 39 is_stmt 0 view .LVU166
667 0108 0D4B ldr r3, .L55+8
668 010a D968 ldr r1, [r3, #12]
669 .loc 1 327 29 view .LVU167
670 010c 0E4A ldr r2, .L55+16
671 010e D160 str r1, [r2, #12]
328:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_ON = ADC_proc.sum_ON;
672 .loc 1 328 5 is_stmt 1 view .LVU168
673 .loc 1 328 38 is_stmt 0 view .LVU169
674 0110 9968 ldr r1, [r3, #8]
675 .loc 1 328 28 view .LVU170
676 0112 9160 str r1, [r2, #8]
329:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
677 .loc 1 329 5 is_stmt 1 view .LVU171
678 .loc 1 329 38 is_stmt 0 view .LVU172
679 0114 1969 ldr r1, [r3, #16]
680 .loc 1 329 28 view .LVU173
681 0116 1161 str r1, [r2, #16]
330:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
682 .loc 1 330 5 is_stmt 1 view .LVU174
683 .loc 1 330 39 is_stmt 0 view .LVU175
684 0118 5969 ldr r1, [r3, #20]
685 .loc 1 330 29 view .LVU176
686 011a 5161 str r1, [r2, #20]
ARM GAS /tmp/cc7eGm0R.s page 20
331:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
687 .loc 1 331 5 is_stmt 1 view .LVU177
688 .loc 1 331 33 is_stmt 0 view .LVU178
689 011c 9969 ldr r1, [r3, #24]
690 .loc 1 331 23 view .LVU179
691 011e 9161 str r1, [r2, #24]
332:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
692 .loc 1 332 5 is_stmt 1 view .LVU180
693 .loc 1 332 28 is_stmt 0 view .LVU181
694 0120 0221 movs r1, #2
695 0122 1170 strb r1, [r2]
333:Core/Src/stm32f4xx_it.c ****
334:Core/Src/stm32f4xx_it.c ****
335:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF = 0;
696 .loc 1 335 5 is_stmt 1 view .LVU182
697 .loc 1 335 22 is_stmt 0 view .LVU183
698 0124 0022 movs r2, #0
699 0126 DA60 str r2, [r3, #12]
336:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON = 0;
700 .loc 1 336 5 is_stmt 1 view .LVU184
701 .loc 1 336 21 is_stmt 0 view .LVU185
702 0128 9A60 str r2, [r3, #8]
337:Core/Src/stm32f4xx_it.c ****
338:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0;
703 .loc 1 338 5 is_stmt 1 view .LVU186
704 .loc 1 338 16 is_stmt 0 view .LVU187
705 012a 9A61 str r2, [r3, #24]
339:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_ON = 0;
706 .loc 1 339 5 is_stmt 1 view .LVU188
707 .loc 1 339 21 is_stmt 0 view .LVU189
708 012c 1A61 str r2, [r3, #16]
340:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_OFF = 0;
709 .loc 1 340 5 is_stmt 1 view .LVU190
710 .loc 1 340 22 is_stmt 0 view .LVU191
711 012e 5A61 str r2, [r3, #20]
341:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data
712 .loc 1 341 5 is_stmt 1 view .LVU192
713 .loc 1 341 21 is_stmt 0 view .LVU193
714 0130 0122 movs r2, #1
715 0132 1A70 strb r2, [r3]
716 .L34:
342:Core/Src/stm32f4xx_it.c **** }
343:Core/Src/stm32f4xx_it.c **** // This function is called when the first half of the ADC buffer is filled
344:Core/Src/stm32f4xx_it.c **** // You can process the first half of ADC1_buff_circular here
345:Core/Src/stm32f4xx_it.c **** }
717 .loc 1 345 1 view .LVU194
718 0134 08BD pop {r3, pc}
719 .L56:
720 0136 00BF .align 2
721 .L55:
722 0138 00040240 .word 1073873920
723 013c 00000000 .word Sweep_state
724 0140 00000000 .word ADC_proc
725 0144 00000000 .word ADC1_buff_circular
726 0148 00000000 .word ADC_proc_shadow
727 .cfi_endproc
728 .LFE252:
ARM GAS /tmp/cc7eGm0R.s page 21
730 .section .text.HAL_ADC_ConvHalfCpltCallback,"ax",%progbits
731 .align 1
732 .global HAL_ADC_ConvHalfCpltCallback
733 .syntax unified
734 .thumb
735 .thumb_func
737 HAL_ADC_ConvHalfCpltCallback:
738 .LVL19:
739 .LFB253:
346:Core/Src/stm32f4xx_it.c ****
347:Core/Src/stm32f4xx_it.c **** void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
348:Core/Src/stm32f4xx_it.c **** {
740 .loc 1 348 1 is_stmt 1 view -0
741 .cfi_startproc
742 @ args = 0, pretend = 0, frame = 0
743 @ frame_needed = 0, uses_anonymous_args = 0
744 .loc 1 348 1 is_stmt 0 view .LVU196
745 0000 08B5 push {r3, lr}
746 .LCFI6:
747 .cfi_def_cfa_offset 8
748 .cfi_offset 3, -8
749 .cfi_offset 14, -4
349:Core/Src/stm32f4xx_it.c **** //HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_RESET);
350:Core/Src/stm32f4xx_it.c ****
351:Core/Src/stm32f4xx_it.c **** HAL_GPIO_TogglePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin);
750 .loc 1 351 3 is_stmt 1 view .LVU197
751 0002 8021 movs r1, #128
752 0004 3D48 ldr r0, .L77
753 .LVL20:
754 .loc 1 351 3 is_stmt 0 view .LVU198
755 0006 FFF7FEFF bl HAL_GPIO_TogglePin
756 .LVL21:
352:Core/Src/stm32f4xx_it.c **** if (Sweep_state.curr_step_started_flag == 1) {
757 .loc 1 352 3 is_stmt 1 view .LVU199
758 .loc 1 352 18 is_stmt 0 view .LVU200
759 000a 3D4B ldr r3, .L77+4
760 000c 1B79 ldrb r3, [r3, #4] @ zero_extendqisi2
761 000e DBB2 uxtb r3, r3
762 .loc 1 352 6 view .LVU201
763 0010 012B cmp r3, #1
764 0012 01D0 beq .L73
765 .LBB6:
353:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag = 0;
354:Core/Src/stm32f4xx_it.c **** for (uint32_t i = 0; i < Sweep_state.curr_step_start_DMA_N; i++) {
355:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
356:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
357:Core/Src/stm32f4xx_it.c **** }else{
358:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF += ADC1_buff_circular[i];
359:Core/Src/stm32f4xx_it.c **** }
360:Core/Src/stm32f4xx_it.c **** }
361:Core/Src/stm32f4xx_it.c ****
362:Core/Src/stm32f4xx_it.c **** ADC_proc.N += (Sweep_state.curr_step_start_DMA_N)/2;
363:Core/Src/stm32f4xx_it.c ****
364:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_ON = ADC_proc.sum_ON;
365:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
366:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
367:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
ARM GAS /tmp/cc7eGm0R.s page 22
368:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
369:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
370:Core/Src/stm32f4xx_it.c ****
371:Core/Src/stm32f4xx_it.c ****
372:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON = 0;
373:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF = 0;
374:Core/Src/stm32f4xx_it.c **** ADC_proc.sum = 0;
375:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0;
376:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_OFF = 0;
377:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_ON = 0;
378:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data
379:Core/Src/stm32f4xx_it.c ****
380:Core/Src/stm32f4xx_it.c **** for (uint32_t i = Sweep_state.curr_step_start_DMA_N; i < ADC_BUFF_SIZE/2; i++) {
381:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
382:Core/Src/stm32f4xx_it.c ****
383:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
384:Core/Src/stm32f4xx_it.c **** }else{
385:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF += ADC1_buff_circular[i];
386:Core/Src/stm32f4xx_it.c **** }
387:Core/Src/stm32f4xx_it.c **** }
388:Core/Src/stm32f4xx_it.c **** ADC_proc.N = (ADC_BUFF_SIZE/2 - Sweep_state.curr_step_start_DMA_N)/2;
389:Core/Src/stm32f4xx_it.c ****
390:Core/Src/stm32f4xx_it.c **** }else{
391:Core/Src/stm32f4xx_it.c **** for (uint32_t i = 0; i < ADC_BUFF_SIZE/2; i++) {
766 .loc 1 391 19 view .LVU202
767 0014 0023 movs r3, #0
768 0016 5EE0 b .L58
769 .L73:
770 .LBE6:
353:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag = 0;
771 .loc 1 353 5 is_stmt 1 view .LVU203
353:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag = 0;
772 .loc 1 353 40 is_stmt 0 view .LVU204
773 0018 0023 movs r3, #0
774 001a 394A ldr r2, .L77+4
775 001c 1371 strb r3, [r2, #4]
354:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
776 .loc 1 354 5 is_stmt 1 view .LVU205
777 .LBB7:
354:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
778 .loc 1 354 10 view .LVU206
779 .LVL22:
354:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
780 .loc 1 354 5 is_stmt 0 view .LVU207
781 001e 07E0 b .L59
782 .LVL23:
783 .L60:
358:Core/Src/stm32f4xx_it.c **** }
784 .loc 1 358 9 is_stmt 1 view .LVU208
358:Core/Src/stm32f4xx_it.c **** }
785 .loc 1 358 17 is_stmt 0 view .LVU209
786 0020 3849 ldr r1, .L77+8
787 0022 CA68 ldr r2, [r1, #12]
358:Core/Src/stm32f4xx_it.c **** }
788 .loc 1 358 47 view .LVU210
789 0024 3848 ldr r0, .L77+12
790 0026 30F81300 ldrh r0, [r0, r3, lsl #1]
ARM GAS /tmp/cc7eGm0R.s page 23
358:Core/Src/stm32f4xx_it.c **** }
791 .loc 1 358 26 view .LVU211
792 002a 0244 add r2, r2, r0
793 002c CA60 str r2, [r1, #12]
794 .L61:
354:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
795 .loc 1 354 66 is_stmt 1 discriminator 2 view .LVU212
796 002e 0133 adds r3, r3, #1
797 .LVL24:
798 .L59:
354:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
799 .loc 1 354 28 discriminator 1 view .LVU213
354:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
800 .loc 1 354 41 is_stmt 0 discriminator 1 view .LVU214
801 0030 334A ldr r2, .L77+4
802 0032 9268 ldr r2, [r2, #8]
354:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
803 .loc 1 354 28 discriminator 1 view .LVU215
804 0034 9A42 cmp r2, r3
805 0036 0AD9 bls .L74
355:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
806 .loc 1 355 7 is_stmt 1 view .LVU216
355:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
807 .loc 1 355 10 is_stmt 0 view .LVU217
808 0038 13F0010F tst r3, #1
809 003c F0D0 beq .L60
356:Core/Src/stm32f4xx_it.c **** }else{
810 .loc 1 356 9 is_stmt 1 view .LVU218
356:Core/Src/stm32f4xx_it.c **** }else{
811 .loc 1 356 17 is_stmt 0 view .LVU219
812 003e 3149 ldr r1, .L77+8
813 0040 8A68 ldr r2, [r1, #8]
356:Core/Src/stm32f4xx_it.c **** }else{
814 .loc 1 356 46 view .LVU220
815 0042 3148 ldr r0, .L77+12
816 0044 30F81300 ldrh r0, [r0, r3, lsl #1]
356:Core/Src/stm32f4xx_it.c **** }else{
817 .loc 1 356 25 view .LVU221
818 0048 0244 add r2, r2, r0
819 004a 8A60 str r2, [r1, #8]
820 004c EFE7 b .L61
821 .L74:
822 .LBE7:
362:Core/Src/stm32f4xx_it.c ****
823 .loc 1 362 5 is_stmt 1 view .LVU222
362:Core/Src/stm32f4xx_it.c ****
824 .loc 1 362 31 is_stmt 0 view .LVU223
825 004e 2C49 ldr r1, .L77+4
826 0050 8868 ldr r0, [r1, #8]
362:Core/Src/stm32f4xx_it.c ****
827 .loc 1 362 13 view .LVU224
828 0052 2C4B ldr r3, .L77+8
829 .LVL25:
362:Core/Src/stm32f4xx_it.c ****
830 .loc 1 362 13 view .LVU225
831 0054 9A69 ldr r2, [r3, #24]
362:Core/Src/stm32f4xx_it.c ****
ARM GAS /tmp/cc7eGm0R.s page 24
832 .loc 1 362 16 view .LVU226
833 0056 02EB5002 add r2, r2, r0, lsr #1
834 005a 9A61 str r2, [r3, #24]
364:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
835 .loc 1 364 5 is_stmt 1 view .LVU227
364:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
836 .loc 1 364 38 is_stmt 0 view .LVU228
837 005c 9868 ldr r0, [r3, #8]
364:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
838 .loc 1 364 28 view .LVU229
839 005e 2B4A ldr r2, .L77+16
840 0060 9060 str r0, [r2, #8]
365:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
841 .loc 1 365 5 is_stmt 1 view .LVU230
365:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
842 .loc 1 365 38 is_stmt 0 view .LVU231
843 0062 1869 ldr r0, [r3, #16]
365:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
844 .loc 1 365 28 view .LVU232
845 0064 1061 str r0, [r2, #16]
366:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
846 .loc 1 366 5 is_stmt 1 view .LVU233
366:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
847 .loc 1 366 39 is_stmt 0 view .LVU234
848 0066 D868 ldr r0, [r3, #12]
366:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
849 .loc 1 366 29 view .LVU235
850 0068 D060 str r0, [r2, #12]
367:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
851 .loc 1 367 5 is_stmt 1 view .LVU236
367:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
852 .loc 1 367 39 is_stmt 0 view .LVU237
853 006a 5869 ldr r0, [r3, #20]
367:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
854 .loc 1 367 29 view .LVU238
855 006c 5061 str r0, [r2, #20]
368:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
856 .loc 1 368 5 is_stmt 1 view .LVU239
368:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
857 .loc 1 368 33 is_stmt 0 view .LVU240
858 006e 9869 ldr r0, [r3, #24]
368:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
859 .loc 1 368 23 view .LVU241
860 0070 9061 str r0, [r2, #24]
369:Core/Src/stm32f4xx_it.c ****
861 .loc 1 369 5 is_stmt 1 view .LVU242
369:Core/Src/stm32f4xx_it.c ****
862 .loc 1 369 28 is_stmt 0 view .LVU243
863 0072 0220 movs r0, #2
864 0074 1070 strb r0, [r2]
372:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF = 0;
865 .loc 1 372 5 is_stmt 1 view .LVU244
372:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF = 0;
866 .loc 1 372 21 is_stmt 0 view .LVU245
867 0076 0022 movs r2, #0
868 0078 9A60 str r2, [r3, #8]
373:Core/Src/stm32f4xx_it.c **** ADC_proc.sum = 0;
ARM GAS /tmp/cc7eGm0R.s page 25
869 .loc 1 373 5 is_stmt 1 view .LVU246
373:Core/Src/stm32f4xx_it.c **** ADC_proc.sum = 0;
870 .loc 1 373 22 is_stmt 0 view .LVU247
871 007a DA60 str r2, [r3, #12]
374:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0;
872 .loc 1 374 5 is_stmt 1 view .LVU248
374:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0;
873 .loc 1 374 18 is_stmt 0 view .LVU249
874 007c 5A60 str r2, [r3, #4]
375:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_OFF = 0;
875 .loc 1 375 5 is_stmt 1 view .LVU250
375:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_OFF = 0;
876 .loc 1 375 16 is_stmt 0 view .LVU251
877 007e 9A61 str r2, [r3, #24]
376:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_ON = 0;
878 .loc 1 376 5 is_stmt 1 view .LVU252
376:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_ON = 0;
879 .loc 1 376 22 is_stmt 0 view .LVU253
880 0080 5A61 str r2, [r3, #20]
377:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data
881 .loc 1 377 5 is_stmt 1 view .LVU254
377:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data
882 .loc 1 377 21 is_stmt 0 view .LVU255
883 0082 1A61 str r2, [r3, #16]
378:Core/Src/stm32f4xx_it.c ****
884 .loc 1 378 5 is_stmt 1 view .LVU256
378:Core/Src/stm32f4xx_it.c ****
885 .loc 1 378 21 is_stmt 0 view .LVU257
886 0084 0122 movs r2, #1
887 0086 1A70 strb r2, [r3]
380:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
888 .loc 1 380 5 is_stmt 1 view .LVU258
889 .LBB8:
380:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
890 .loc 1 380 10 view .LVU259
380:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
891 .loc 1 380 19 is_stmt 0 view .LVU260
892 0088 8B68 ldr r3, [r1, #8]
893 .LVL26:
380:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
894 .loc 1 380 5 view .LVU261
895 008a 07E0 b .L63
896 .L64:
385:Core/Src/stm32f4xx_it.c **** }
897 .loc 1 385 9 is_stmt 1 view .LVU262
385:Core/Src/stm32f4xx_it.c **** }
898 .loc 1 385 17 is_stmt 0 view .LVU263
899 008c 1D49 ldr r1, .L77+8
900 008e CA68 ldr r2, [r1, #12]
385:Core/Src/stm32f4xx_it.c **** }
901 .loc 1 385 47 view .LVU264
902 0090 1D48 ldr r0, .L77+12
903 0092 30F81300 ldrh r0, [r0, r3, lsl #1]
385:Core/Src/stm32f4xx_it.c **** }
904 .loc 1 385 26 view .LVU265
905 0096 0244 add r2, r2, r0
906 0098 CA60 str r2, [r1, #12]
ARM GAS /tmp/cc7eGm0R.s page 26
907 .L65:
380:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
908 .loc 1 380 80 is_stmt 1 discriminator 2 view .LVU266
909 009a 0133 adds r3, r3, #1
910 .LVL27:
911 .L63:
380:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
912 .loc 1 380 60 discriminator 1 view .LVU267
913 009c 1F2B cmp r3, #31
914 009e 0AD8 bhi .L75
381:Core/Src/stm32f4xx_it.c ****
915 .loc 1 381 7 view .LVU268
381:Core/Src/stm32f4xx_it.c ****
916 .loc 1 381 10 is_stmt 0 view .LVU269
917 00a0 13F0010F tst r3, #1
918 00a4 F2D0 beq .L64
383:Core/Src/stm32f4xx_it.c **** }else{
919 .loc 1 383 9 is_stmt 1 view .LVU270
383:Core/Src/stm32f4xx_it.c **** }else{
920 .loc 1 383 17 is_stmt 0 view .LVU271
921 00a6 1749 ldr r1, .L77+8
922 00a8 8A68 ldr r2, [r1, #8]
383:Core/Src/stm32f4xx_it.c **** }else{
923 .loc 1 383 46 view .LVU272
924 00aa 1748 ldr r0, .L77+12
925 00ac 30F81300 ldrh r0, [r0, r3, lsl #1]
383:Core/Src/stm32f4xx_it.c **** }else{
926 .loc 1 383 25 view .LVU273
927 00b0 0244 add r2, r2, r0
928 00b2 8A60 str r2, [r1, #8]
929 00b4 F1E7 b .L65
930 .L75:
931 .LBE8:
388:Core/Src/stm32f4xx_it.c ****
932 .loc 1 388 5 is_stmt 1 view .LVU274
388:Core/Src/stm32f4xx_it.c ****
933 .loc 1 388 48 is_stmt 0 view .LVU275
934 00b6 124B ldr r3, .L77+4
935 .LVL28:
388:Core/Src/stm32f4xx_it.c ****
936 .loc 1 388 48 view .LVU276
937 00b8 9B68 ldr r3, [r3, #8]
388:Core/Src/stm32f4xx_it.c ****
938 .loc 1 388 35 view .LVU277
939 00ba C3F12003 rsb r3, r3, #32
388:Core/Src/stm32f4xx_it.c ****
940 .loc 1 388 71 view .LVU278
941 00be 5B08 lsrs r3, r3, #1
388:Core/Src/stm32f4xx_it.c ****
942 .loc 1 388 16 view .LVU279
943 00c0 104A ldr r2, .L77+8
944 00c2 9361 str r3, [r2, #24]
945 00c4 18E0 b .L57
946 .LVL29:
947 .L68:
948 .LBB9:
392:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
ARM GAS /tmp/cc7eGm0R.s page 27
393:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
394:Core/Src/stm32f4xx_it.c **** }else{
395:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF += ADC1_buff_circular[i];
949 .loc 1 395 9 is_stmt 1 view .LVU280
950 .loc 1 395 17 is_stmt 0 view .LVU281
951 00c6 0F49 ldr r1, .L77+8
952 00c8 CA68 ldr r2, [r1, #12]
953 .loc 1 395 47 view .LVU282
954 00ca 0F48 ldr r0, .L77+12
955 00cc 30F81300 ldrh r0, [r0, r3, lsl #1]
956 .loc 1 395 26 view .LVU283
957 00d0 0244 add r2, r2, r0
958 00d2 CA60 str r2, [r1, #12]
959 .L69:
391:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
960 .loc 1 391 48 is_stmt 1 discriminator 2 view .LVU284
961 00d4 0133 adds r3, r3, #1
962 .LVL30:
963 .L58:
391:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
964 .loc 1 391 28 discriminator 1 view .LVU285
965 00d6 1F2B cmp r3, #31
966 00d8 0AD8 bhi .L76
392:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
967 .loc 1 392 7 view .LVU286
392:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
968 .loc 1 392 10 is_stmt 0 view .LVU287
969 00da 13F0010F tst r3, #1
970 00de F2D0 beq .L68
393:Core/Src/stm32f4xx_it.c **** }else{
971 .loc 1 393 9 is_stmt 1 view .LVU288
393:Core/Src/stm32f4xx_it.c **** }else{
972 .loc 1 393 17 is_stmt 0 view .LVU289
973 00e0 0849 ldr r1, .L77+8
974 00e2 8A68 ldr r2, [r1, #8]
393:Core/Src/stm32f4xx_it.c **** }else{
975 .loc 1 393 46 view .LVU290
976 00e4 0848 ldr r0, .L77+12
977 00e6 30F81300 ldrh r0, [r0, r3, lsl #1]
393:Core/Src/stm32f4xx_it.c **** }else{
978 .loc 1 393 25 view .LVU291
979 00ea 0244 add r2, r2, r0
980 00ec 8A60 str r2, [r1, #8]
981 00ee F1E7 b .L69
982 .L76:
983 .LBE9:
396:Core/Src/stm32f4xx_it.c **** }
397:Core/Src/stm32f4xx_it.c **** }
398:Core/Src/stm32f4xx_it.c **** ADC_proc.N += (ADC_BUFF_SIZE/2)/2;
984 .loc 1 398 5 is_stmt 1 view .LVU292
985 .loc 1 398 13 is_stmt 0 view .LVU293
986 00f0 044A ldr r2, .L77+8
987 00f2 9369 ldr r3, [r2, #24]
988 .LVL31:
989 .loc 1 398 16 view .LVU294
990 00f4 1033 adds r3, r3, #16
991 00f6 9361 str r3, [r2, #24]
ARM GAS /tmp/cc7eGm0R.s page 28
992 .LVL32:
993 .L57:
399:Core/Src/stm32f4xx_it.c **** }
400:Core/Src/stm32f4xx_it.c **** // This function is called when the first half of the ADC buffer is filled
401:Core/Src/stm32f4xx_it.c **** // You can process the first half of ADC1_buff_circular here
402:Core/Src/stm32f4xx_it.c **** }
994 .loc 1 402 1 view .LVU295
995 00f8 08BD pop {r3, pc}
996 .L78:
997 00fa 00BF .align 2
998 .L77:
999 00fc 00040240 .word 1073873920
1000 0100 00000000 .word Sweep_state
1001 0104 00000000 .word ADC_proc
1002 0108 00000000 .word ADC1_buff_circular
1003 010c 00000000 .word ADC_proc_shadow
1004 .cfi_endproc
1005 .LFE253:
1007 .text
1008 .Letext0:
1009 .file 2 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h"
1010 .file 3 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h"
1011 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
1012 .file 5 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h"
1013 .file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h"
1014 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h"
1015 .file 8 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h"
1016 .file 9 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h"
1017 .file 10 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h"
1018 .file 11 "Core/Inc/main.h"
1019 .file 12 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h"
ARM GAS /tmp/cc7eGm0R.s page 29
DEFINED SYMBOLS
*ABS*:00000000 stm32f4xx_it.c
/tmp/cc7eGm0R.s:21 .text.NMI_Handler:00000000 $t
/tmp/cc7eGm0R.s:27 .text.NMI_Handler:00000000 NMI_Handler
/tmp/cc7eGm0R.s:44 .text.HardFault_Handler:00000000 $t
/tmp/cc7eGm0R.s:50 .text.HardFault_Handler:00000000 HardFault_Handler
/tmp/cc7eGm0R.s:67 .text.MemManage_Handler:00000000 $t
/tmp/cc7eGm0R.s:73 .text.MemManage_Handler:00000000 MemManage_Handler
/tmp/cc7eGm0R.s:90 .text.BusFault_Handler:00000000 $t
/tmp/cc7eGm0R.s:96 .text.BusFault_Handler:00000000 BusFault_Handler
/tmp/cc7eGm0R.s:113 .text.UsageFault_Handler:00000000 $t
/tmp/cc7eGm0R.s:119 .text.UsageFault_Handler:00000000 UsageFault_Handler
/tmp/cc7eGm0R.s:136 .text.SVC_Handler:00000000 $t
/tmp/cc7eGm0R.s:142 .text.SVC_Handler:00000000 SVC_Handler
/tmp/cc7eGm0R.s:155 .text.DebugMon_Handler:00000000 $t
/tmp/cc7eGm0R.s:161 .text.DebugMon_Handler:00000000 DebugMon_Handler
/tmp/cc7eGm0R.s:174 .text.PendSV_Handler:00000000 $t
/tmp/cc7eGm0R.s:180 .text.PendSV_Handler:00000000 PendSV_Handler
/tmp/cc7eGm0R.s:193 .text.SysTick_Handler:00000000 $t
/tmp/cc7eGm0R.s:199 .text.SysTick_Handler:00000000 SysTick_Handler
/tmp/cc7eGm0R.s:219 .text.EXTI0_IRQHandler:00000000 $t
/tmp/cc7eGm0R.s:225 .text.EXTI0_IRQHandler:00000000 EXTI0_IRQHandler
/tmp/cc7eGm0R.s:282 .text.EXTI0_IRQHandler:00000034 $d
/tmp/cc7eGm0R.s:288 .text.EXTI3_IRQHandler:00000000 $t
/tmp/cc7eGm0R.s:294 .text.EXTI3_IRQHandler:00000000 EXTI3_IRQHandler
/tmp/cc7eGm0R.s:323 .text.EXTI3_IRQHandler:00000014 $d
/tmp/cc7eGm0R.s:328 .text.DMA2_Stream0_IRQHandler:00000000 $t
/tmp/cc7eGm0R.s:334 .text.DMA2_Stream0_IRQHandler:00000000 DMA2_Stream0_IRQHandler
/tmp/cc7eGm0R.s:354 .text.DMA2_Stream0_IRQHandler:0000000c $d
/tmp/cc7eGm0R.s:359 .text.OTG_FS_IRQHandler:00000000 $t
/tmp/cc7eGm0R.s:365 .text.OTG_FS_IRQHandler:00000000 OTG_FS_IRQHandler
/tmp/cc7eGm0R.s:385 .text.OTG_FS_IRQHandler:0000000c $d
/tmp/cc7eGm0R.s:390 .text.HAL_ADC_ConvCpltCallback:00000000 $t
/tmp/cc7eGm0R.s:396 .text.HAL_ADC_ConvCpltCallback:00000000 HAL_ADC_ConvCpltCallback
/tmp/cc7eGm0R.s:722 .text.HAL_ADC_ConvCpltCallback:00000138 $d
/tmp/cc7eGm0R.s:731 .text.HAL_ADC_ConvHalfCpltCallback:00000000 $t
/tmp/cc7eGm0R.s:737 .text.HAL_ADC_ConvHalfCpltCallback:00000000 HAL_ADC_ConvHalfCpltCallback
/tmp/cc7eGm0R.s:999 .text.HAL_ADC_ConvHalfCpltCallback:000000fc $d
UNDEFINED SYMBOLS
HAL_IncTick
HAL_GPIO_EXTI_IRQHandler
hdma_adc1
Sweep_state
HAL_DMA_IRQHandler
HAL_PCD_IRQHandler
hpcd_USB_OTG_FS
HAL_GPIO_WritePin
ADC_proc
ADC1_buff_circular
ADC_proc_shadow
HAL_GPIO_TogglePin
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