ChTheo/RFG_stm32_ADC_STM32F429
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RFG_stm32_ADC_STM32F429/build/main.lst

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ARM GAS /tmp/cc6ou28t.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "main.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .file 1 "Core/Src/main.c"
20 .section .text.MX_GPIO_Init,"ax",%progbits
21 .align 1
22 .syntax unified
23 .thumb
24 .thumb_func
26 MX_GPIO_Init:
27 .LFB247:
1:Core/Src/main.c **** /* USER CODE BEGIN Header */
2:Core/Src/main.c **** /**
3:Core/Src/main.c **** ******************************************************************************
4:Core/Src/main.c **** * @file : main.c
5:Core/Src/main.c **** * @brief : Main program body
6:Core/Src/main.c **** ******************************************************************************
7:Core/Src/main.c **** * @attention
8:Core/Src/main.c **** *
9:Core/Src/main.c **** * Copyright (c) 2025 STMicroelectronics.
10:Core/Src/main.c **** * All rights reserved.
11:Core/Src/main.c **** *
12:Core/Src/main.c **** * This software is licensed under terms that can be found in the LICENSE file
13:Core/Src/main.c **** * in the root directory of this software component.
14:Core/Src/main.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
15:Core/Src/main.c **** *
16:Core/Src/main.c **** ******************************************************************************
17:Core/Src/main.c **** */
18:Core/Src/main.c **** /* USER CODE END Header */
19:Core/Src/main.c **** /* Includes ------------------------------------------------------------------*/
20:Core/Src/main.c **** #include "main.h"
21:Core/Src/main.c **** #include "usb_device.h"
22:Core/Src/main.c ****
23:Core/Src/main.c **** /* Private includes ----------------------------------------------------------*/
24:Core/Src/main.c **** /* USER CODE BEGIN Includes */
25:Core/Src/main.c ****
26:Core/Src/main.c **** /* USER CODE END Includes */
27:Core/Src/main.c ****
28:Core/Src/main.c **** /* Private typedef -----------------------------------------------------------*/
29:Core/Src/main.c **** /* USER CODE BEGIN PTD */
30:Core/Src/main.c ****
31:Core/Src/main.c **** /* USER CODE END PTD */
ARM GAS /tmp/cc6ou28t.s page 2
32:Core/Src/main.c ****
33:Core/Src/main.c **** /* Private define ------------------------------------------------------------*/
34:Core/Src/main.c **** /* USER CODE BEGIN PD */
35:Core/Src/main.c ****
36:Core/Src/main.c **** /* USER CODE END PD */
37:Core/Src/main.c ****
38:Core/Src/main.c **** /* Private macro -------------------------------------------------------------*/
39:Core/Src/main.c **** /* USER CODE BEGIN PM */
40:Core/Src/main.c ****
41:Core/Src/main.c **** /* USER CODE END PM */
42:Core/Src/main.c ****
43:Core/Src/main.c **** /* Private variables ---------------------------------------------------------*/
44:Core/Src/main.c **** ADC_HandleTypeDef hadc1;
45:Core/Src/main.c **** DMA_HandleTypeDef hdma_adc1;
46:Core/Src/main.c ****
47:Core/Src/main.c **** /* USER CODE BEGIN PV */
48:Core/Src/main.c ****
49:Core/Src/main.c **** /* USER CODE END PV */
50:Core/Src/main.c ****
51:Core/Src/main.c **** /* Private function prototypes -----------------------------------------------*/
52:Core/Src/main.c **** void SystemClock_Config(void);
53:Core/Src/main.c **** static void MX_GPIO_Init(void);
54:Core/Src/main.c **** static void MX_DMA_Init(void);
55:Core/Src/main.c **** static void MX_ADC1_Init(void);
56:Core/Src/main.c **** /* USER CODE BEGIN PFP */
57:Core/Src/main.c ****
58:Core/Src/main.c **** /* USER CODE END PFP */
59:Core/Src/main.c ****
60:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/
61:Core/Src/main.c **** /* USER CODE BEGIN 0 */
62:Core/Src/main.c **** /* adc_process definition is provided here; structure is declared in main.h */
63:Core/Src/main.c **** struct ADC_proc adc_process;
64:Core/Src/main.c ****
65:Core/Src/main.c **** /* ADC1 circular DMA buffer definition */
66:Core/Src/main.c **** uint16_t ADC1_buff_circular[ADC_BUFF_SIZE];
67:Core/Src/main.c **** char ADC_msg[] = "Received ADC value: ??????????\r\n";
68:Core/Src/main.c **** #define ADC_msg_len 32
69:Core/Src/main.c **** #define ADC_msg_val_pos 20
70:Core/Src/main.c **** /* USER CODE END 0 */
71:Core/Src/main.c ****
72:Core/Src/main.c **** /**
73:Core/Src/main.c **** * @brief The application entry point.
74:Core/Src/main.c **** * @retval int
75:Core/Src/main.c **** */
76:Core/Src/main.c **** int main(void)
77:Core/Src/main.c **** {
78:Core/Src/main.c ****
79:Core/Src/main.c **** /* USER CODE BEGIN 1 */
80:Core/Src/main.c ****
81:Core/Src/main.c **** /* USER CODE END 1 */
82:Core/Src/main.c ****
83:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/
84:Core/Src/main.c ****
85:Core/Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
86:Core/Src/main.c **** HAL_Init();
87:Core/Src/main.c ****
88:Core/Src/main.c **** /* USER CODE BEGIN Init */
ARM GAS /tmp/cc6ou28t.s page 3
89:Core/Src/main.c ****
90:Core/Src/main.c **** /* USER CODE END Init */
91:Core/Src/main.c ****
92:Core/Src/main.c **** /* Configure the system clock */
93:Core/Src/main.c **** SystemClock_Config();
94:Core/Src/main.c ****
95:Core/Src/main.c **** /* USER CODE BEGIN SysInit */
96:Core/Src/main.c ****
97:Core/Src/main.c **** /* USER CODE END SysInit */
98:Core/Src/main.c ****
99:Core/Src/main.c **** /* Initialize all configured peripherals */
100:Core/Src/main.c **** MX_GPIO_Init();
101:Core/Src/main.c **** MX_DMA_Init();
102:Core/Src/main.c **** MX_ADC1_Init();
103:Core/Src/main.c **** MX_USB_DEVICE_Init();
104:Core/Src/main.c **** /* USER CODE BEGIN 2 */
105:Core/Src/main.c **** HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_SET);
106:Core/Src/main.c **** HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADC1_buff_circular, ADC_BUFF_SIZE);
107:Core/Src/main.c **** adc_process.status = 0; // ADC started
108:Core/Src/main.c **** adc_process.N = 0;
109:Core/Src/main.c **** adc_process.sum = 0;
110:Core/Src/main.c **** adc_process.avg = 0;
111:Core/Src/main.c ****
112:Core/Src/main.c **** /* USER CODE END 2 */
113:Core/Src/main.c ****
114:Core/Src/main.c **** /* Infinite loop */
115:Core/Src/main.c **** /* USER CODE BEGIN WHILE */
116:Core/Src/main.c **** while (1)
117:Core/Src/main.c **** {
118:Core/Src/main.c **** HAL_GPIO_TogglePin(LED_RED_GPIO_Port, LED_RED_Pin);
119:Core/Src/main.c **** //HAL_Delay(100);
120:Core/Src/main.c ****
121:Core/Src/main.c **** if (adc_process.status == 2) {
122:Core/Src/main.c **** adc_process.avg = adc_process.sum / adc_process.N;
123:Core/Src/main.c **** adc_process.status = 1; // reset for next accumulation
124:Core/Src/main.c **** adc_process.sum = 0;
125:Core/Src/main.c **** adc_process.N = 0;
126:Core/Src/main.c ****
127:Core/Src/main.c ****
128:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 0] = (adc_process.avg / 10000000000) % 10 + '0';
129:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 1] = (adc_process.avg / 1000000000) % 10 + '0';
130:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 2] = (adc_process.avg / 10000000) % 10 + '0';
131:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 3] = (adc_process.avg / 1000000) % 10 + '0';
132:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 4] = (adc_process.avg / 100000) % 10 + '0';
133:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 5] = (adc_process.avg / 10000) % 10 + '0';
134:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 6] = (adc_process.avg / 1000) % 10 + '0';
135:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 7] = (adc_process.avg / 100) % 10 + '0';
136:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 8] = (adc_process.avg / 10) % 10 + '0';
137:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 9] = (adc_process.avg / 1) % 10 + '0';
138:Core/Src/main.c **** CDC_Transmit_FS((uint8_t *)ADC_msg, ADC_msg_len);
139:Core/Src/main.c ****
140:Core/Src/main.c **** }
141:Core/Src/main.c **** //CDC_Transmit_FS((uint8_t *)"Hello from STM32!\r\n", 19);
142:Core/Src/main.c ****
143:Core/Src/main.c **** /* USER CODE END WHILE */
144:Core/Src/main.c ****
145:Core/Src/main.c **** /* USER CODE BEGIN 3 */
ARM GAS /tmp/cc6ou28t.s page 4
146:Core/Src/main.c **** }
147:Core/Src/main.c **** /* USER CODE END 3 */
148:Core/Src/main.c **** }
149:Core/Src/main.c ****
150:Core/Src/main.c **** /**
151:Core/Src/main.c **** * @brief System Clock Configuration
152:Core/Src/main.c **** * @retval None
153:Core/Src/main.c **** */
154:Core/Src/main.c **** void SystemClock_Config(void)
155:Core/Src/main.c **** {
156:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0};
157:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
158:Core/Src/main.c ****
159:Core/Src/main.c **** /** Configure the main internal regulator output voltage
160:Core/Src/main.c **** */
161:Core/Src/main.c **** __HAL_RCC_PWR_CLK_ENABLE();
162:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
163:Core/Src/main.c ****
164:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters
165:Core/Src/main.c **** * in the RCC_OscInitTypeDef structure.
166:Core/Src/main.c **** */
167:Core/Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
168:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON;
169:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
170:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
171:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 8;
172:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 336;
173:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
174:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 7;
175:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
176:Core/Src/main.c **** {
177:Core/Src/main.c **** Error_Handler();
178:Core/Src/main.c **** }
179:Core/Src/main.c ****
180:Core/Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks
181:Core/Src/main.c **** */
182:Core/Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
183:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
184:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
185:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
186:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
187:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
188:Core/Src/main.c ****
189:Core/Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
190:Core/Src/main.c **** {
191:Core/Src/main.c **** Error_Handler();
192:Core/Src/main.c **** }
193:Core/Src/main.c **** }
194:Core/Src/main.c ****
195:Core/Src/main.c **** /**
196:Core/Src/main.c **** * @brief ADC1 Initialization Function
197:Core/Src/main.c **** * @param None
198:Core/Src/main.c **** * @retval None
199:Core/Src/main.c **** */
200:Core/Src/main.c **** static void MX_ADC1_Init(void)
201:Core/Src/main.c **** {
202:Core/Src/main.c ****
ARM GAS /tmp/cc6ou28t.s page 5
203:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 0 */
204:Core/Src/main.c ****
205:Core/Src/main.c **** /* USER CODE END ADC1_Init 0 */
206:Core/Src/main.c ****
207:Core/Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0};
208:Core/Src/main.c ****
209:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 1 */
210:Core/Src/main.c ****
211:Core/Src/main.c **** /* USER CODE END ADC1_Init 1 */
212:Core/Src/main.c ****
213:Core/Src/main.c **** /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of con
214:Core/Src/main.c **** */
215:Core/Src/main.c **** hadc1.Instance = ADC1;
216:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
217:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B;
218:Core/Src/main.c **** hadc1.Init.ScanConvMode = DISABLE;
219:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE;
220:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE;
221:Core/Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
222:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_Ext_IT11;
223:Core/Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
224:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1;
225:Core/Src/main.c **** hadc1.Init.DMAContinuousRequests = ENABLE;
226:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
227:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK)
228:Core/Src/main.c **** {
229:Core/Src/main.c **** Error_Handler();
230:Core/Src/main.c **** }
231:Core/Src/main.c ****
232:Core/Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it
233:Core/Src/main.c **** */
234:Core/Src/main.c **** sConfig.Channel = ADC_CHANNEL_3;
235:Core/Src/main.c **** sConfig.Rank = 1;
236:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
237:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
238:Core/Src/main.c **** {
239:Core/Src/main.c **** Error_Handler();
240:Core/Src/main.c **** }
241:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 2 */
242:Core/Src/main.c ****
243:Core/Src/main.c **** /* USER CODE END ADC1_Init 2 */
244:Core/Src/main.c ****
245:Core/Src/main.c **** }
246:Core/Src/main.c ****
247:Core/Src/main.c **** /**
248:Core/Src/main.c **** * Enable DMA controller clock
249:Core/Src/main.c **** */
250:Core/Src/main.c **** static void MX_DMA_Init(void)
251:Core/Src/main.c **** {
252:Core/Src/main.c ****
253:Core/Src/main.c **** /* DMA controller clock enable */
254:Core/Src/main.c **** __HAL_RCC_DMA2_CLK_ENABLE();
255:Core/Src/main.c ****
256:Core/Src/main.c **** /* DMA interrupt init */
257:Core/Src/main.c **** /* DMA2_Stream0_IRQn interrupt configuration */
258:Core/Src/main.c **** HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 0, 0);
259:Core/Src/main.c **** HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn);
ARM GAS /tmp/cc6ou28t.s page 6
260:Core/Src/main.c ****
261:Core/Src/main.c **** }
262:Core/Src/main.c ****
263:Core/Src/main.c **** /**
264:Core/Src/main.c **** * @brief GPIO Initialization Function
265:Core/Src/main.c **** * @param None
266:Core/Src/main.c **** * @retval None
267:Core/Src/main.c **** */
268:Core/Src/main.c **** static void MX_GPIO_Init(void)
269:Core/Src/main.c **** {
28 .loc 1 269 1 view -0
29 .cfi_startproc
30 @ args = 0, pretend = 0, frame = 40
31 @ frame_needed = 0, uses_anonymous_args = 0
32 0000 30B5 push {r4, r5, lr}
33 .LCFI0:
34 .cfi_def_cfa_offset 12
35 .cfi_offset 4, -12
36 .cfi_offset 5, -8
37 .cfi_offset 14, -4
38 0002 8BB0 sub sp, sp, #44
39 .LCFI1:
40 .cfi_def_cfa_offset 56
270:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
41 .loc 1 270 3 view .LVU1
42 .loc 1 270 20 is_stmt 0 view .LVU2
43 0004 0024 movs r4, #0
44 0006 0594 str r4, [sp, #20]
45 0008 0694 str r4, [sp, #24]
46 000a 0794 str r4, [sp, #28]
47 000c 0894 str r4, [sp, #32]
48 000e 0994 str r4, [sp, #36]
271:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */
272:Core/Src/main.c ****
273:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_1 */
274:Core/Src/main.c ****
275:Core/Src/main.c **** /* GPIO Ports Clock Enable */
276:Core/Src/main.c **** __HAL_RCC_GPIOH_CLK_ENABLE();
49 .loc 1 276 3 is_stmt 1 view .LVU3
50 .LBB4:
51 .loc 1 276 3 view .LVU4
52 0010 0094 str r4, [sp]
53 .loc 1 276 3 view .LVU5
54 0012 2B4B ldr r3, .L3
55 0014 1A6B ldr r2, [r3, #48]
56 0016 42F08002 orr r2, r2, #128
57 001a 1A63 str r2, [r3, #48]
58 .loc 1 276 3 view .LVU6
59 001c 1A6B ldr r2, [r3, #48]
60 001e 02F08002 and r2, r2, #128
61 0022 0092 str r2, [sp]
62 .loc 1 276 3 view .LVU7
63 0024 009A ldr r2, [sp]
64 .LBE4:
65 .loc 1 276 3 view .LVU8
277:Core/Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE();
66 .loc 1 277 3 view .LVU9
ARM GAS /tmp/cc6ou28t.s page 7
67 .LBB5:
68 .loc 1 277 3 view .LVU10
69 0026 0194 str r4, [sp, #4]
70 .loc 1 277 3 view .LVU11
71 0028 1A6B ldr r2, [r3, #48]
72 002a 42F00402 orr r2, r2, #4
73 002e 1A63 str r2, [r3, #48]
74 .loc 1 277 3 view .LVU12
75 0030 1A6B ldr r2, [r3, #48]
76 0032 02F00402 and r2, r2, #4
77 0036 0192 str r2, [sp, #4]
78 .loc 1 277 3 view .LVU13
79 0038 019A ldr r2, [sp, #4]
80 .LBE5:
81 .loc 1 277 3 view .LVU14
278:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
82 .loc 1 278 3 view .LVU15
83 .LBB6:
84 .loc 1 278 3 view .LVU16
85 003a 0294 str r4, [sp, #8]
86 .loc 1 278 3 view .LVU17
87 003c 1A6B ldr r2, [r3, #48]
88 003e 42F00102 orr r2, r2, #1
89 0042 1A63 str r2, [r3, #48]
90 .loc 1 278 3 view .LVU18
91 0044 1A6B ldr r2, [r3, #48]
92 0046 02F00102 and r2, r2, #1
93 004a 0292 str r2, [sp, #8]
94 .loc 1 278 3 view .LVU19
95 004c 029A ldr r2, [sp, #8]
96 .LBE6:
97 .loc 1 278 3 view .LVU20
279:Core/Src/main.c **** __HAL_RCC_GPIOF_CLK_ENABLE();
98 .loc 1 279 3 view .LVU21
99 .LBB7:
100 .loc 1 279 3 view .LVU22
101 004e 0394 str r4, [sp, #12]
102 .loc 1 279 3 view .LVU23
103 0050 1A6B ldr r2, [r3, #48]
104 0052 42F02002 orr r2, r2, #32
105 0056 1A63 str r2, [r3, #48]
106 .loc 1 279 3 view .LVU24
107 0058 1A6B ldr r2, [r3, #48]
108 005a 02F02002 and r2, r2, #32
109 005e 0392 str r2, [sp, #12]
110 .loc 1 279 3 view .LVU25
111 0060 039A ldr r2, [sp, #12]
112 .LBE7:
113 .loc 1 279 3 view .LVU26
280:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
114 .loc 1 280 3 view .LVU27
115 .LBB8:
116 .loc 1 280 3 view .LVU28
117 0062 0494 str r4, [sp, #16]
118 .loc 1 280 3 view .LVU29
119 0064 1A6B ldr r2, [r3, #48]
120 0066 42F00202 orr r2, r2, #2
ARM GAS /tmp/cc6ou28t.s page 8
121 006a 1A63 str r2, [r3, #48]
122 .loc 1 280 3 view .LVU30
123 006c 1B6B ldr r3, [r3, #48]
124 006e 03F00203 and r3, r3, #2
125 0072 0493 str r3, [sp, #16]
126 .loc 1 280 3 view .LVU31
127 0074 049B ldr r3, [sp, #16]
128 .LBE8:
129 .loc 1 280 3 view .LVU32
281:Core/Src/main.c ****
282:Core/Src/main.c **** /*Configure GPIO pin Output Level */
283:Core/Src/main.c **** HAL_GPIO_WritePin(LED_RED_GPIO_Port, LED_RED_Pin, GPIO_PIN_RESET);
130 .loc 1 283 3 view .LVU33
131 0076 134D ldr r5, .L3+4
132 0078 2246 mov r2, r4
133 007a 4FF48041 mov r1, #16384
134 007e 2846 mov r0, r5
135 0080 FFF7FEFF bl HAL_GPIO_WritePin
136 .LVL0:
284:Core/Src/main.c ****
285:Core/Src/main.c **** /*Configure GPIO pin Output Level */
286:Core/Src/main.c **** HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_SET);
137 .loc 1 286 3 view .LVU34
138 0084 0122 movs r2, #1
139 0086 8021 movs r1, #128
140 0088 2846 mov r0, r5
141 008a FFF7FEFF bl HAL_GPIO_WritePin
142 .LVL1:
287:Core/Src/main.c ****
288:Core/Src/main.c **** /*Configure GPIO pin : PF11 */
289:Core/Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_11;
143 .loc 1 289 3 view .LVU35
144 .loc 1 289 23 is_stmt 0 view .LVU36
145 008e 4FF40063 mov r3, #2048
146 0092 0593 str r3, [sp, #20]
290:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
147 .loc 1 290 3 is_stmt 1 view .LVU37
148 .loc 1 290 24 is_stmt 0 view .LVU38
149 0094 4FF48813 mov r3, #1114112
150 0098 0693 str r3, [sp, #24]
291:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
151 .loc 1 291 3 is_stmt 1 view .LVU39
152 .loc 1 291 24 is_stmt 0 view .LVU40
153 009a 0794 str r4, [sp, #28]
292:Core/Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
154 .loc 1 292 3 is_stmt 1 view .LVU41
155 009c 05A9 add r1, sp, #20
156 009e 0A48 ldr r0, .L3+8
157 00a0 FFF7FEFF bl HAL_GPIO_Init
158 .LVL2:
293:Core/Src/main.c ****
294:Core/Src/main.c **** /*Configure GPIO pins : LED_RED_Pin LED_BLUE_Pin */
295:Core/Src/main.c **** GPIO_InitStruct.Pin = LED_RED_Pin|LED_BLUE_Pin;
159 .loc 1 295 3 view .LVU42
160 .loc 1 295 23 is_stmt 0 view .LVU43
161 00a4 4FF48143 mov r3, #16512
162 00a8 0593 str r3, [sp, #20]
ARM GAS /tmp/cc6ou28t.s page 9
296:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
163 .loc 1 296 3 is_stmt 1 view .LVU44
164 .loc 1 296 24 is_stmt 0 view .LVU45
165 00aa 0123 movs r3, #1
166 00ac 0693 str r3, [sp, #24]
297:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
167 .loc 1 297 3 is_stmt 1 view .LVU46
168 .loc 1 297 24 is_stmt 0 view .LVU47
169 00ae 0794 str r4, [sp, #28]
298:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
170 .loc 1 298 3 is_stmt 1 view .LVU48
171 .loc 1 298 25 is_stmt 0 view .LVU49
172 00b0 0894 str r4, [sp, #32]
299:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
173 .loc 1 299 3 is_stmt 1 view .LVU50
174 00b2 05A9 add r1, sp, #20
175 00b4 2846 mov r0, r5
176 00b6 FFF7FEFF bl HAL_GPIO_Init
177 .LVL3:
300:Core/Src/main.c ****
301:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_2 */
302:Core/Src/main.c ****
303:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_2 */
304:Core/Src/main.c **** }
178 .loc 1 304 1 is_stmt 0 view .LVU51
179 00ba 0BB0 add sp, sp, #44
180 .LCFI2:
181 .cfi_def_cfa_offset 12
182 @ sp needed
183 00bc 30BD pop {r4, r5, pc}
184 .L4:
185 00be 00BF .align 2
186 .L3:
187 00c0 00380240 .word 1073887232
188 00c4 00040240 .word 1073873920
189 00c8 00140240 .word 1073878016
190 .cfi_endproc
191 .LFE247:
193 .section .text.MX_DMA_Init,"ax",%progbits
194 .align 1
195 .syntax unified
196 .thumb
197 .thumb_func
199 MX_DMA_Init:
200 .LFB246:
251:Core/Src/main.c ****
201 .loc 1 251 1 is_stmt 1 view -0
202 .cfi_startproc
203 @ args = 0, pretend = 0, frame = 8
204 @ frame_needed = 0, uses_anonymous_args = 0
205 0000 00B5 push {lr}
206 .LCFI3:
207 .cfi_def_cfa_offset 4
208 .cfi_offset 14, -4
209 0002 83B0 sub sp, sp, #12
210 .LCFI4:
211 .cfi_def_cfa_offset 16
ARM GAS /tmp/cc6ou28t.s page 10
254:Core/Src/main.c ****
212 .loc 1 254 3 view .LVU53
213 .LBB9:
254:Core/Src/main.c ****
214 .loc 1 254 3 view .LVU54
215 0004 0021 movs r1, #0
216 0006 0191 str r1, [sp, #4]
254:Core/Src/main.c ****
217 .loc 1 254 3 view .LVU55
218 0008 094B ldr r3, .L7
219 000a 1A6B ldr r2, [r3, #48]
220 000c 42F48002 orr r2, r2, #4194304
221 0010 1A63 str r2, [r3, #48]
254:Core/Src/main.c ****
222 .loc 1 254 3 view .LVU56
223 0012 1B6B ldr r3, [r3, #48]
224 0014 03F48003 and r3, r3, #4194304
225 0018 0193 str r3, [sp, #4]
254:Core/Src/main.c ****
226 .loc 1 254 3 view .LVU57
227 001a 019B ldr r3, [sp, #4]
228 .LBE9:
254:Core/Src/main.c ****
229 .loc 1 254 3 view .LVU58
258:Core/Src/main.c **** HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn);
230 .loc 1 258 3 view .LVU59
231 001c 0A46 mov r2, r1
232 001e 3820 movs r0, #56
233 0020 FFF7FEFF bl HAL_NVIC_SetPriority
234 .LVL4:
259:Core/Src/main.c ****
235 .loc 1 259 3 view .LVU60
236 0024 3820 movs r0, #56
237 0026 FFF7FEFF bl HAL_NVIC_EnableIRQ
238 .LVL5:
261:Core/Src/main.c ****
239 .loc 1 261 1 is_stmt 0 view .LVU61
240 002a 03B0 add sp, sp, #12
241 .LCFI5:
242 .cfi_def_cfa_offset 4
243 @ sp needed
244 002c 5DF804FB ldr pc, [sp], #4
245 .L8:
246 .align 2
247 .L7:
248 0030 00380240 .word 1073887232
249 .cfi_endproc
250 .LFE246:
252 .section .text.Error_Handler,"ax",%progbits
253 .align 1
254 .global Error_Handler
255 .syntax unified
256 .thumb
257 .thumb_func
259 Error_Handler:
260 .LFB248:
305:Core/Src/main.c ****
ARM GAS /tmp/cc6ou28t.s page 11
306:Core/Src/main.c **** /* USER CODE BEGIN 4 */
307:Core/Src/main.c ****
308:Core/Src/main.c **** /* USER CODE END 4 */
309:Core/Src/main.c ****
310:Core/Src/main.c **** /**
311:Core/Src/main.c **** * @brief This function is executed in case of error occurrence.
312:Core/Src/main.c **** * @retval None
313:Core/Src/main.c **** */
314:Core/Src/main.c **** void Error_Handler(void)
315:Core/Src/main.c **** {
261 .loc 1 315 1 is_stmt 1 view -0
262 .cfi_startproc
263 @ Volatile: function does not return.
264 @ args = 0, pretend = 0, frame = 0
265 @ frame_needed = 0, uses_anonymous_args = 0
266 @ link register save eliminated.
316:Core/Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */
317:Core/Src/main.c **** /* User can add his own implementation to report the HAL error return state */
318:Core/Src/main.c **** __disable_irq();
267 .loc 1 318 3 view .LVU63
268 .LBB10:
269 .LBI10:
270 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h
3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file
4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.4.1
5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 27. May 2021
6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/
7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
9:Drivers/CMSIS/Include/cmsis_gcc.h **** *
10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0
11:Drivers/CMSIS/Include/cmsis_gcc.h **** *
12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may
13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License.
14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at
15:Drivers/CMSIS/Include/cmsis_gcc.h **** *
16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0
17:Drivers/CMSIS/Include/cmsis_gcc.h **** *
18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software
19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and
22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License.
23:Drivers/CMSIS/Include/cmsis_gcc.h **** */
24:Drivers/CMSIS/Include/cmsis_gcc.h ****
25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
27:Drivers/CMSIS/Include/cmsis_gcc.h ****
28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
33:Drivers/CMSIS/Include/cmsis_gcc.h ****
34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
ARM GAS /tmp/cc6ou28t.s page 12
35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0)
37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
38:Drivers/CMSIS/Include/cmsis_gcc.h ****
39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM
41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm
42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE
44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline
45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE
47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline
48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE
50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN
53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__))
54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED
56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used))
57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK
59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak))
60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED
62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1)))
63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT
65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION
68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1)))
69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */
71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; };
75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE
79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ
87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
ARM GAS /tmp/cc6ou28t.s page 13
92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add
93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE
95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ
103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add
109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED
111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x)))
112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT
114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict
115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __COMPILER_BARRIER
117:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
119:Drivers/CMSIS/Include/cmsis_gcc.h ****
120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ######################### Startup and Lowlevel Init ######################## */
121:Drivers/CMSIS/Include/cmsis_gcc.h ****
122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START
123:Drivers/CMSIS/Include/cmsis_gcc.h ****
124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Initializes data and bss sections
126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details This default implementations initialized all data and additional bss
127:Drivers/CMSIS/Include/cmsis_gcc.h **** sections relying on .copy.table and .zero.table specified properly
128:Drivers/CMSIS/Include/cmsis_gcc.h **** in the used linker script.
129:Drivers/CMSIS/Include/cmsis_gcc.h ****
130:Drivers/CMSIS/Include/cmsis_gcc.h **** */
131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
132:Drivers/CMSIS/Include/cmsis_gcc.h **** {
133:Drivers/CMSIS/Include/cmsis_gcc.h **** extern void _start(void) __NO_RETURN;
134:Drivers/CMSIS/Include/cmsis_gcc.h ****
135:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct {
136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t const* src;
137:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest;
138:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen;
139:Drivers/CMSIS/Include/cmsis_gcc.h **** } __copy_table_t;
140:Drivers/CMSIS/Include/cmsis_gcc.h ****
141:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct {
142:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest;
143:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen;
144:Drivers/CMSIS/Include/cmsis_gcc.h **** } __zero_table_t;
145:Drivers/CMSIS/Include/cmsis_gcc.h ****
146:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_start__;
147:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_end__;
148:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_start__;
ARM GAS /tmp/cc6ou28t.s page 14
149:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_end__;
150:Drivers/CMSIS/Include/cmsis_gcc.h ****
151:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
152:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; i<pTable->wlen; ++i) {
153:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = pTable->src[i];
154:Drivers/CMSIS/Include/cmsis_gcc.h **** }
155:Drivers/CMSIS/Include/cmsis_gcc.h **** }
156:Drivers/CMSIS/Include/cmsis_gcc.h ****
157:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
158:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; i<pTable->wlen; ++i) {
159:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = 0u;
160:Drivers/CMSIS/Include/cmsis_gcc.h **** }
161:Drivers/CMSIS/Include/cmsis_gcc.h **** }
162:Drivers/CMSIS/Include/cmsis_gcc.h ****
163:Drivers/CMSIS/Include/cmsis_gcc.h **** _start();
164:Drivers/CMSIS/Include/cmsis_gcc.h **** }
165:Drivers/CMSIS/Include/cmsis_gcc.h ****
166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START __cmsis_start
167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
168:Drivers/CMSIS/Include/cmsis_gcc.h ****
169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP
170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP __StackTop
171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
172:Drivers/CMSIS/Include/cmsis_gcc.h ****
173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT
174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT __StackLimit
175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
176:Drivers/CMSIS/Include/cmsis_gcc.h ****
177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE __Vectors
179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
180:Drivers/CMSIS/Include/cmsis_gcc.h ****
181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors")))
183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
184:Drivers/CMSIS/Include/cmsis_gcc.h ****
185:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
186:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_SEAL
187:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_SEAL __StackSeal
188:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
189:Drivers/CMSIS/Include/cmsis_gcc.h ****
190:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_SIZE
191:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __TZ_STACK_SEAL_SIZE 8U
192:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
193:Drivers/CMSIS/Include/cmsis_gcc.h ****
194:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_VALUE
195:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
196:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
197:Drivers/CMSIS/Include/cmsis_gcc.h ****
198:Drivers/CMSIS/Include/cmsis_gcc.h ****
199:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
200:Drivers/CMSIS/Include/cmsis_gcc.h **** *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
201:Drivers/CMSIS/Include/cmsis_gcc.h **** }
202:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
203:Drivers/CMSIS/Include/cmsis_gcc.h ****
204:Drivers/CMSIS/Include/cmsis_gcc.h ****
205:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */
ARM GAS /tmp/cc6ou28t.s page 15
206:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
207:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions
208:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
209:Drivers/CMSIS/Include/cmsis_gcc.h **** */
210:Drivers/CMSIS/Include/cmsis_gcc.h ****
211:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
212:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l"
213:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */
214:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
215:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
216:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
217:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
218:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
219:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
220:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
221:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
222:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
223:Drivers/CMSIS/Include/cmsis_gcc.h ****
224:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
225:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation
226:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes.
227:Drivers/CMSIS/Include/cmsis_gcc.h **** */
228:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop")
229:Drivers/CMSIS/Include/cmsis_gcc.h ****
230:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
231:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt
232:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
233:Drivers/CMSIS/Include/cmsis_gcc.h **** */
234:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi":::"memory")
235:Drivers/CMSIS/Include/cmsis_gcc.h ****
236:Drivers/CMSIS/Include/cmsis_gcc.h ****
237:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
238:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event
239:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter
240:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs.
241:Drivers/CMSIS/Include/cmsis_gcc.h **** */
242:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe":::"memory")
243:Drivers/CMSIS/Include/cmsis_gcc.h ****
244:Drivers/CMSIS/Include/cmsis_gcc.h ****
245:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
246:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event
247:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
248:Drivers/CMSIS/Include/cmsis_gcc.h **** */
249:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev")
250:Drivers/CMSIS/Include/cmsis_gcc.h ****
251:Drivers/CMSIS/Include/cmsis_gcc.h ****
252:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
253:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier
254:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor,
255:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory,
256:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed.
257:Drivers/CMSIS/Include/cmsis_gcc.h **** */
258:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
259:Drivers/CMSIS/Include/cmsis_gcc.h **** {
260:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory");
261:Drivers/CMSIS/Include/cmsis_gcc.h **** }
262:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS /tmp/cc6ou28t.s page 16
263:Drivers/CMSIS/Include/cmsis_gcc.h ****
264:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
265:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier
266:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier.
267:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete.
268:Drivers/CMSIS/Include/cmsis_gcc.h **** */
269:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
270:Drivers/CMSIS/Include/cmsis_gcc.h **** {
271:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory");
272:Drivers/CMSIS/Include/cmsis_gcc.h **** }
273:Drivers/CMSIS/Include/cmsis_gcc.h ****
274:Drivers/CMSIS/Include/cmsis_gcc.h ****
275:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
276:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier
277:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before
278:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion.
279:Drivers/CMSIS/Include/cmsis_gcc.h **** */
280:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
281:Drivers/CMSIS/Include/cmsis_gcc.h **** {
282:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory");
283:Drivers/CMSIS/Include/cmsis_gcc.h **** }
284:Drivers/CMSIS/Include/cmsis_gcc.h ****
285:Drivers/CMSIS/Include/cmsis_gcc.h ****
286:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
287:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit)
288:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785
289:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse
290:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value
291:Drivers/CMSIS/Include/cmsis_gcc.h **** */
292:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
293:Drivers/CMSIS/Include/cmsis_gcc.h **** {
294:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
295:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value);
296:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
297:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
298:Drivers/CMSIS/Include/cmsis_gcc.h ****
299:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
300:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
301:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
302:Drivers/CMSIS/Include/cmsis_gcc.h **** }
303:Drivers/CMSIS/Include/cmsis_gcc.h ****
304:Drivers/CMSIS/Include/cmsis_gcc.h ****
305:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
306:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit)
307:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes
308:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse
309:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value
310:Drivers/CMSIS/Include/cmsis_gcc.h **** */
311:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
312:Drivers/CMSIS/Include/cmsis_gcc.h **** {
313:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
314:Drivers/CMSIS/Include/cmsis_gcc.h ****
315:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
316:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
317:Drivers/CMSIS/Include/cmsis_gcc.h **** }
318:Drivers/CMSIS/Include/cmsis_gcc.h ****
319:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS /tmp/cc6ou28t.s page 17
320:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
321:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit)
322:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam
323:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse
324:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value
325:Drivers/CMSIS/Include/cmsis_gcc.h **** */
326:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
327:Drivers/CMSIS/Include/cmsis_gcc.h **** {
328:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
329:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value);
330:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
331:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result;
332:Drivers/CMSIS/Include/cmsis_gcc.h ****
333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
334:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
335:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
336:Drivers/CMSIS/Include/cmsis_gcc.h **** }
337:Drivers/CMSIS/Include/cmsis_gcc.h ****
338:Drivers/CMSIS/Include/cmsis_gcc.h ****
339:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
340:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit)
341:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
342:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate
343:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate
344:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value
345:Drivers/CMSIS/Include/cmsis_gcc.h **** */
346:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
347:Drivers/CMSIS/Include/cmsis_gcc.h **** {
348:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U;
349:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U)
350:Drivers/CMSIS/Include/cmsis_gcc.h **** {
351:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1;
352:Drivers/CMSIS/Include/cmsis_gcc.h **** }
353:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2));
354:Drivers/CMSIS/Include/cmsis_gcc.h **** }
355:Drivers/CMSIS/Include/cmsis_gcc.h ****
356:Drivers/CMSIS/Include/cmsis_gcc.h ****
357:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
358:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint
359:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state.
360:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula
361:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor.
362:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break
363:Drivers/CMSIS/Include/cmsis_gcc.h **** */
364:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value)
365:Drivers/CMSIS/Include/cmsis_gcc.h ****
366:Drivers/CMSIS/Include/cmsis_gcc.h ****
367:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
368:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value
369:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value.
370:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse
371:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value
372:Drivers/CMSIS/Include/cmsis_gcc.h **** */
373:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
374:Drivers/CMSIS/Include/cmsis_gcc.h **** {
375:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
376:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS /tmp/cc6ou28t.s page 18
377:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
378:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
379:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
380:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
381:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
382:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
383:Drivers/CMSIS/Include/cmsis_gcc.h ****
384:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */
385:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U)
386:Drivers/CMSIS/Include/cmsis_gcc.h **** {
387:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U;
388:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U;
389:Drivers/CMSIS/Include/cmsis_gcc.h **** s--;
390:Drivers/CMSIS/Include/cmsis_gcc.h **** }
391:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */
392:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
393:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
394:Drivers/CMSIS/Include/cmsis_gcc.h **** }
395:Drivers/CMSIS/Include/cmsis_gcc.h ****
396:Drivers/CMSIS/Include/cmsis_gcc.h ****
397:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
398:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Count leading zeros
399:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Counts the number of leading zeros of a data value.
400:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to count the leading zeros
401:Drivers/CMSIS/Include/cmsis_gcc.h **** \return number of leading zeros in value
402:Drivers/CMSIS/Include/cmsis_gcc.h **** */
403:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
404:Drivers/CMSIS/Include/cmsis_gcc.h **** {
405:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
406:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_clz(0) is undefined behaviour, so handle this case specially.
407:Drivers/CMSIS/Include/cmsis_gcc.h **** This guarantees ARM-compatible results if happening to compile on a non-ARM
408:Drivers/CMSIS/Include/cmsis_gcc.h **** target, and ensures the compiler doesn't decide to activate any
409:Drivers/CMSIS/Include/cmsis_gcc.h **** optimisations using the logic "value was passed to __builtin_clz, so it
410:Drivers/CMSIS/Include/cmsis_gcc.h **** is non-zero".
411:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
412:Drivers/CMSIS/Include/cmsis_gcc.h **** single CLZ instruction.
413:Drivers/CMSIS/Include/cmsis_gcc.h **** */
414:Drivers/CMSIS/Include/cmsis_gcc.h **** if (value == 0U)
415:Drivers/CMSIS/Include/cmsis_gcc.h **** {
416:Drivers/CMSIS/Include/cmsis_gcc.h **** return 32U;
417:Drivers/CMSIS/Include/cmsis_gcc.h **** }
418:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_clz(value);
419:Drivers/CMSIS/Include/cmsis_gcc.h **** }
420:Drivers/CMSIS/Include/cmsis_gcc.h ****
421:Drivers/CMSIS/Include/cmsis_gcc.h ****
422:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
423:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
424:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
425:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
426:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
427:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (8 bit)
428:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 8 bit value.
429:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data
430:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr)
431:Drivers/CMSIS/Include/cmsis_gcc.h **** */
432:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
433:Drivers/CMSIS/Include/cmsis_gcc.h **** {
ARM GAS /tmp/cc6ou28t.s page 19
434:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
435:Drivers/CMSIS/Include/cmsis_gcc.h ****
436:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
437:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
438:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
439:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
440:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern.
441:Drivers/CMSIS/Include/cmsis_gcc.h **** */
442:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
443:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
444:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); /* Add explicit type cast here */
445:Drivers/CMSIS/Include/cmsis_gcc.h **** }
446:Drivers/CMSIS/Include/cmsis_gcc.h ****
447:Drivers/CMSIS/Include/cmsis_gcc.h ****
448:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
449:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (16 bit)
450:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 16 bit values.
451:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data
452:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr)
453:Drivers/CMSIS/Include/cmsis_gcc.h **** */
454:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
455:Drivers/CMSIS/Include/cmsis_gcc.h **** {
456:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
457:Drivers/CMSIS/Include/cmsis_gcc.h ****
458:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
459:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
460:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
461:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
462:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern.
463:Drivers/CMSIS/Include/cmsis_gcc.h **** */
464:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
465:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
466:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); /* Add explicit type cast here */
467:Drivers/CMSIS/Include/cmsis_gcc.h **** }
468:Drivers/CMSIS/Include/cmsis_gcc.h ****
469:Drivers/CMSIS/Include/cmsis_gcc.h ****
470:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
471:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (32 bit)
472:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 32 bit values.
473:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data
474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr)
475:Drivers/CMSIS/Include/cmsis_gcc.h **** */
476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
477:Drivers/CMSIS/Include/cmsis_gcc.h **** {
478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
479:Drivers/CMSIS/Include/cmsis_gcc.h ****
480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
483:Drivers/CMSIS/Include/cmsis_gcc.h ****
484:Drivers/CMSIS/Include/cmsis_gcc.h ****
485:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
486:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (8 bit)
487:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 8 bit values.
488:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store
489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location
490:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded
ARM GAS /tmp/cc6ou28t.s page 20
491:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed
492:Drivers/CMSIS/Include/cmsis_gcc.h **** */
493:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
494:Drivers/CMSIS/Include/cmsis_gcc.h **** {
495:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
496:Drivers/CMSIS/Include/cmsis_gcc.h ****
497:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
498:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
499:Drivers/CMSIS/Include/cmsis_gcc.h **** }
500:Drivers/CMSIS/Include/cmsis_gcc.h ****
501:Drivers/CMSIS/Include/cmsis_gcc.h ****
502:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
503:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (16 bit)
504:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 16 bit values.
505:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store
506:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location
507:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded
508:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed
509:Drivers/CMSIS/Include/cmsis_gcc.h **** */
510:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
511:Drivers/CMSIS/Include/cmsis_gcc.h **** {
512:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
513:Drivers/CMSIS/Include/cmsis_gcc.h ****
514:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
515:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
516:Drivers/CMSIS/Include/cmsis_gcc.h **** }
517:Drivers/CMSIS/Include/cmsis_gcc.h ****
518:Drivers/CMSIS/Include/cmsis_gcc.h ****
519:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
520:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (32 bit)
521:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 32 bit values.
522:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store
523:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location
524:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded
525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed
526:Drivers/CMSIS/Include/cmsis_gcc.h **** */
527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
528:Drivers/CMSIS/Include/cmsis_gcc.h **** {
529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
530:Drivers/CMSIS/Include/cmsis_gcc.h ****
531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
533:Drivers/CMSIS/Include/cmsis_gcc.h **** }
534:Drivers/CMSIS/Include/cmsis_gcc.h ****
535:Drivers/CMSIS/Include/cmsis_gcc.h ****
536:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
537:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Remove the exclusive lock
538:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Removes the exclusive lock which is created by LDREX.
539:Drivers/CMSIS/Include/cmsis_gcc.h **** */
540:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __CLREX(void)
541:Drivers/CMSIS/Include/cmsis_gcc.h **** {
542:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("clrex" ::: "memory");
543:Drivers/CMSIS/Include/cmsis_gcc.h **** }
544:Drivers/CMSIS/Include/cmsis_gcc.h ****
545:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
546:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
547:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
ARM GAS /tmp/cc6ou28t.s page 21
548:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
549:Drivers/CMSIS/Include/cmsis_gcc.h ****
550:Drivers/CMSIS/Include/cmsis_gcc.h ****
551:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
552:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
553:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
554:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
555:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Signed Saturate
556:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Saturates a signed value.
557:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ARG1 Value to be saturated
558:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ARG2 Bit position to saturate to (1..32)
559:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Saturated value
560:Drivers/CMSIS/Include/cmsis_gcc.h **** */
561:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SSAT(ARG1, ARG2) \
562:Drivers/CMSIS/Include/cmsis_gcc.h **** __extension__ \
563:Drivers/CMSIS/Include/cmsis_gcc.h **** ({ \
564:Drivers/CMSIS/Include/cmsis_gcc.h **** int32_t __RES, __ARG1 = (ARG1); \
565:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
566:Drivers/CMSIS/Include/cmsis_gcc.h **** __RES; \
567:Drivers/CMSIS/Include/cmsis_gcc.h **** })
568:Drivers/CMSIS/Include/cmsis_gcc.h ****
569:Drivers/CMSIS/Include/cmsis_gcc.h ****
570:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
571:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Unsigned Saturate
572:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Saturates an unsigned value.
573:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ARG1 Value to be saturated
574:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ARG2 Bit position to saturate to (0..31)
575:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Saturated value
576:Drivers/CMSIS/Include/cmsis_gcc.h **** */
577:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USAT(ARG1, ARG2) \
578:Drivers/CMSIS/Include/cmsis_gcc.h **** __extension__ \
579:Drivers/CMSIS/Include/cmsis_gcc.h **** ({ \
580:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t __RES, __ARG1 = (ARG1); \
581:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
582:Drivers/CMSIS/Include/cmsis_gcc.h **** __RES; \
583:Drivers/CMSIS/Include/cmsis_gcc.h **** })
584:Drivers/CMSIS/Include/cmsis_gcc.h ****
585:Drivers/CMSIS/Include/cmsis_gcc.h ****
586:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
587:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right with Extend (32 bit)
588:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Moves each bit of a bitstring right by one bit.
589:Drivers/CMSIS/Include/cmsis_gcc.h **** The carry input is shifted in at the left end of the bitstring.
590:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to rotate
591:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value
592:Drivers/CMSIS/Include/cmsis_gcc.h **** */
593:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
594:Drivers/CMSIS/Include/cmsis_gcc.h **** {
595:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
596:Drivers/CMSIS/Include/cmsis_gcc.h ****
597:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
598:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
599:Drivers/CMSIS/Include/cmsis_gcc.h **** }
600:Drivers/CMSIS/Include/cmsis_gcc.h ****
601:Drivers/CMSIS/Include/cmsis_gcc.h ****
602:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
603:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDRT Unprivileged (8 bit)
604:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged LDRT instruction for 8 bit value.
ARM GAS /tmp/cc6ou28t.s page 22
605:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data
606:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr)
607:Drivers/CMSIS/Include/cmsis_gcc.h **** */
608:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
609:Drivers/CMSIS/Include/cmsis_gcc.h **** {
610:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
611:Drivers/CMSIS/Include/cmsis_gcc.h ****
612:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
613:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
614:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
615:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
616:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern.
617:Drivers/CMSIS/Include/cmsis_gcc.h **** */
618:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
619:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
620:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); /* Add explicit type cast here */
621:Drivers/CMSIS/Include/cmsis_gcc.h **** }
622:Drivers/CMSIS/Include/cmsis_gcc.h ****
623:Drivers/CMSIS/Include/cmsis_gcc.h ****
624:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
625:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDRT Unprivileged (16 bit)
626:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged LDRT instruction for 16 bit values.
627:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data
628:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr)
629:Drivers/CMSIS/Include/cmsis_gcc.h **** */
630:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
631:Drivers/CMSIS/Include/cmsis_gcc.h **** {
632:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
633:Drivers/CMSIS/Include/cmsis_gcc.h ****
634:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
635:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
636:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
637:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
638:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern.
639:Drivers/CMSIS/Include/cmsis_gcc.h **** */
640:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
641:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
642:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); /* Add explicit type cast here */
643:Drivers/CMSIS/Include/cmsis_gcc.h **** }
644:Drivers/CMSIS/Include/cmsis_gcc.h ****
645:Drivers/CMSIS/Include/cmsis_gcc.h ****
646:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
647:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDRT Unprivileged (32 bit)
648:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged LDRT instruction for 32 bit values.
649:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data
650:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr)
651:Drivers/CMSIS/Include/cmsis_gcc.h **** */
652:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
653:Drivers/CMSIS/Include/cmsis_gcc.h **** {
654:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
655:Drivers/CMSIS/Include/cmsis_gcc.h ****
656:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
657:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
658:Drivers/CMSIS/Include/cmsis_gcc.h **** }
659:Drivers/CMSIS/Include/cmsis_gcc.h ****
660:Drivers/CMSIS/Include/cmsis_gcc.h ****
661:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
ARM GAS /tmp/cc6ou28t.s page 23
662:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STRT Unprivileged (8 bit)
663:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged STRT instruction for 8 bit values.
664:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store
665:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location
666:Drivers/CMSIS/Include/cmsis_gcc.h **** */
667:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
668:Drivers/CMSIS/Include/cmsis_gcc.h **** {
669:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
670:Drivers/CMSIS/Include/cmsis_gcc.h **** }
671:Drivers/CMSIS/Include/cmsis_gcc.h ****
672:Drivers/CMSIS/Include/cmsis_gcc.h ****
673:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
674:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STRT Unprivileged (16 bit)
675:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged STRT instruction for 16 bit values.
676:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store
677:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location
678:Drivers/CMSIS/Include/cmsis_gcc.h **** */
679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
680:Drivers/CMSIS/Include/cmsis_gcc.h **** {
681:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
682:Drivers/CMSIS/Include/cmsis_gcc.h **** }
683:Drivers/CMSIS/Include/cmsis_gcc.h ****
684:Drivers/CMSIS/Include/cmsis_gcc.h ****
685:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
686:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STRT Unprivileged (32 bit)
687:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged STRT instruction for 32 bit values.
688:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store
689:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location
690:Drivers/CMSIS/Include/cmsis_gcc.h **** */
691:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
692:Drivers/CMSIS/Include/cmsis_gcc.h **** {
693:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
694:Drivers/CMSIS/Include/cmsis_gcc.h **** }
695:Drivers/CMSIS/Include/cmsis_gcc.h ****
696:Drivers/CMSIS/Include/cmsis_gcc.h **** #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
697:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
698:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
699:Drivers/CMSIS/Include/cmsis_gcc.h ****
700:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
701:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Signed Saturate
702:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Saturates a signed value.
703:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to be saturated
704:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] sat Bit position to saturate to (1..32)
705:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Saturated value
706:Drivers/CMSIS/Include/cmsis_gcc.h **** */
707:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
708:Drivers/CMSIS/Include/cmsis_gcc.h **** {
709:Drivers/CMSIS/Include/cmsis_gcc.h **** if ((sat >= 1U) && (sat <= 32U))
710:Drivers/CMSIS/Include/cmsis_gcc.h **** {
711:Drivers/CMSIS/Include/cmsis_gcc.h **** const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
712:Drivers/CMSIS/Include/cmsis_gcc.h **** const int32_t min = -1 - max ;
713:Drivers/CMSIS/Include/cmsis_gcc.h **** if (val > max)
714:Drivers/CMSIS/Include/cmsis_gcc.h **** {
715:Drivers/CMSIS/Include/cmsis_gcc.h **** return max;
716:Drivers/CMSIS/Include/cmsis_gcc.h **** }
717:Drivers/CMSIS/Include/cmsis_gcc.h **** else if (val < min)
718:Drivers/CMSIS/Include/cmsis_gcc.h **** {
ARM GAS /tmp/cc6ou28t.s page 24
719:Drivers/CMSIS/Include/cmsis_gcc.h **** return min;
720:Drivers/CMSIS/Include/cmsis_gcc.h **** }
721:Drivers/CMSIS/Include/cmsis_gcc.h **** }
722:Drivers/CMSIS/Include/cmsis_gcc.h **** return val;
723:Drivers/CMSIS/Include/cmsis_gcc.h **** }
724:Drivers/CMSIS/Include/cmsis_gcc.h ****
725:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
726:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Unsigned Saturate
727:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Saturates an unsigned value.
728:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to be saturated
729:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] sat Bit position to saturate to (0..31)
730:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Saturated value
731:Drivers/CMSIS/Include/cmsis_gcc.h **** */
732:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
733:Drivers/CMSIS/Include/cmsis_gcc.h **** {
734:Drivers/CMSIS/Include/cmsis_gcc.h **** if (sat <= 31U)
735:Drivers/CMSIS/Include/cmsis_gcc.h **** {
736:Drivers/CMSIS/Include/cmsis_gcc.h **** const uint32_t max = ((1U << sat) - 1U);
737:Drivers/CMSIS/Include/cmsis_gcc.h **** if (val > (int32_t)max)
738:Drivers/CMSIS/Include/cmsis_gcc.h **** {
739:Drivers/CMSIS/Include/cmsis_gcc.h **** return max;
740:Drivers/CMSIS/Include/cmsis_gcc.h **** }
741:Drivers/CMSIS/Include/cmsis_gcc.h **** else if (val < 0)
742:Drivers/CMSIS/Include/cmsis_gcc.h **** {
743:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
744:Drivers/CMSIS/Include/cmsis_gcc.h **** }
745:Drivers/CMSIS/Include/cmsis_gcc.h **** }
746:Drivers/CMSIS/Include/cmsis_gcc.h **** return (uint32_t)val;
747:Drivers/CMSIS/Include/cmsis_gcc.h **** }
748:Drivers/CMSIS/Include/cmsis_gcc.h ****
749:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
750:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
751:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
752:Drivers/CMSIS/Include/cmsis_gcc.h ****
753:Drivers/CMSIS/Include/cmsis_gcc.h ****
754:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
755:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
756:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
757:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire (8 bit)
758:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDAB instruction for 8 bit value.
759:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data
760:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr)
761:Drivers/CMSIS/Include/cmsis_gcc.h **** */
762:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
763:Drivers/CMSIS/Include/cmsis_gcc.h **** {
764:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
765:Drivers/CMSIS/Include/cmsis_gcc.h ****
766:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
767:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result);
768:Drivers/CMSIS/Include/cmsis_gcc.h **** }
769:Drivers/CMSIS/Include/cmsis_gcc.h ****
770:Drivers/CMSIS/Include/cmsis_gcc.h ****
771:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
772:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire (16 bit)
773:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDAH instruction for 16 bit values.
774:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data
775:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr)
ARM GAS /tmp/cc6ou28t.s page 25
776:Drivers/CMSIS/Include/cmsis_gcc.h **** */
777:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
778:Drivers/CMSIS/Include/cmsis_gcc.h **** {
779:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
780:Drivers/CMSIS/Include/cmsis_gcc.h ****
781:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
782:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result);
783:Drivers/CMSIS/Include/cmsis_gcc.h **** }
784:Drivers/CMSIS/Include/cmsis_gcc.h ****
785:Drivers/CMSIS/Include/cmsis_gcc.h ****
786:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
787:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire (32 bit)
788:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDA instruction for 32 bit values.
789:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data
790:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr)
791:Drivers/CMSIS/Include/cmsis_gcc.h **** */
792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
794:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
795:Drivers/CMSIS/Include/cmsis_gcc.h ****
796:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
797:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
798:Drivers/CMSIS/Include/cmsis_gcc.h **** }
799:Drivers/CMSIS/Include/cmsis_gcc.h ****
800:Drivers/CMSIS/Include/cmsis_gcc.h ****
801:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
802:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release (8 bit)
803:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STLB instruction for 8 bit values.
804:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store
805:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location
806:Drivers/CMSIS/Include/cmsis_gcc.h **** */
807:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
808:Drivers/CMSIS/Include/cmsis_gcc.h **** {
809:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
810:Drivers/CMSIS/Include/cmsis_gcc.h **** }
811:Drivers/CMSIS/Include/cmsis_gcc.h ****
812:Drivers/CMSIS/Include/cmsis_gcc.h ****
813:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
814:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release (16 bit)
815:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STLH instruction for 16 bit values.
816:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store
817:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location
818:Drivers/CMSIS/Include/cmsis_gcc.h **** */
819:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
820:Drivers/CMSIS/Include/cmsis_gcc.h **** {
821:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
822:Drivers/CMSIS/Include/cmsis_gcc.h **** }
823:Drivers/CMSIS/Include/cmsis_gcc.h ****
824:Drivers/CMSIS/Include/cmsis_gcc.h ****
825:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
826:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release (32 bit)
827:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STL instruction for 32 bit values.
828:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store
829:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location
830:Drivers/CMSIS/Include/cmsis_gcc.h **** */
831:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
832:Drivers/CMSIS/Include/cmsis_gcc.h **** {
ARM GAS /tmp/cc6ou28t.s page 26
833:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
834:Drivers/CMSIS/Include/cmsis_gcc.h **** }
835:Drivers/CMSIS/Include/cmsis_gcc.h ****
836:Drivers/CMSIS/Include/cmsis_gcc.h ****
837:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
838:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire Exclusive (8 bit)
839:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDAB exclusive instruction for 8 bit value.
840:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data
841:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr)
842:Drivers/CMSIS/Include/cmsis_gcc.h **** */
843:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
844:Drivers/CMSIS/Include/cmsis_gcc.h **** {
845:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
846:Drivers/CMSIS/Include/cmsis_gcc.h ****
847:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
848:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result);
849:Drivers/CMSIS/Include/cmsis_gcc.h **** }
850:Drivers/CMSIS/Include/cmsis_gcc.h ****
851:Drivers/CMSIS/Include/cmsis_gcc.h ****
852:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
853:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire Exclusive (16 bit)
854:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDAH exclusive instruction for 16 bit values.
855:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data
856:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr)
857:Drivers/CMSIS/Include/cmsis_gcc.h **** */
858:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
859:Drivers/CMSIS/Include/cmsis_gcc.h **** {
860:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
861:Drivers/CMSIS/Include/cmsis_gcc.h ****
862:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
863:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result);
864:Drivers/CMSIS/Include/cmsis_gcc.h **** }
865:Drivers/CMSIS/Include/cmsis_gcc.h ****
866:Drivers/CMSIS/Include/cmsis_gcc.h ****
867:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
868:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire Exclusive (32 bit)
869:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDA exclusive instruction for 32 bit values.
870:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data
871:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr)
872:Drivers/CMSIS/Include/cmsis_gcc.h **** */
873:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
874:Drivers/CMSIS/Include/cmsis_gcc.h **** {
875:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
876:Drivers/CMSIS/Include/cmsis_gcc.h ****
877:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
878:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
879:Drivers/CMSIS/Include/cmsis_gcc.h **** }
880:Drivers/CMSIS/Include/cmsis_gcc.h ****
881:Drivers/CMSIS/Include/cmsis_gcc.h ****
882:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
883:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release Exclusive (8 bit)
884:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STLB exclusive instruction for 8 bit values.
885:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store
886:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location
887:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded
888:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed
889:Drivers/CMSIS/Include/cmsis_gcc.h **** */
ARM GAS /tmp/cc6ou28t.s page 27
890:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
891:Drivers/CMSIS/Include/cmsis_gcc.h **** {
892:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
893:Drivers/CMSIS/Include/cmsis_gcc.h ****
894:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem
895:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
896:Drivers/CMSIS/Include/cmsis_gcc.h **** }
897:Drivers/CMSIS/Include/cmsis_gcc.h ****
898:Drivers/CMSIS/Include/cmsis_gcc.h ****
899:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
900:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release Exclusive (16 bit)
901:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STLH exclusive instruction for 16 bit values.
902:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store
903:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location
904:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded
905:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed
906:Drivers/CMSIS/Include/cmsis_gcc.h **** */
907:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
908:Drivers/CMSIS/Include/cmsis_gcc.h **** {
909:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
910:Drivers/CMSIS/Include/cmsis_gcc.h ****
911:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem
912:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
913:Drivers/CMSIS/Include/cmsis_gcc.h **** }
914:Drivers/CMSIS/Include/cmsis_gcc.h ****
915:Drivers/CMSIS/Include/cmsis_gcc.h ****
916:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
917:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release Exclusive (32 bit)
918:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STL exclusive instruction for 32 bit values.
919:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store
920:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location
921:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded
922:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed
923:Drivers/CMSIS/Include/cmsis_gcc.h **** */
924:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
925:Drivers/CMSIS/Include/cmsis_gcc.h **** {
926:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
927:Drivers/CMSIS/Include/cmsis_gcc.h ****
928:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memo
929:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
930:Drivers/CMSIS/Include/cmsis_gcc.h **** }
931:Drivers/CMSIS/Include/cmsis_gcc.h ****
932:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
933:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
934:Drivers/CMSIS/Include/cmsis_gcc.h ****
935:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
936:Drivers/CMSIS/Include/cmsis_gcc.h ****
937:Drivers/CMSIS/Include/cmsis_gcc.h ****
938:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */
939:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface
940:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
941:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
942:Drivers/CMSIS/Include/cmsis_gcc.h **** */
943:Drivers/CMSIS/Include/cmsis_gcc.h ****
944:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
945:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts
946:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
ARM GAS /tmp/cc6ou28t.s page 28
947:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
948:Drivers/CMSIS/Include/cmsis_gcc.h **** */
949:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
950:Drivers/CMSIS/Include/cmsis_gcc.h **** {
951:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory");
952:Drivers/CMSIS/Include/cmsis_gcc.h **** }
953:Drivers/CMSIS/Include/cmsis_gcc.h ****
954:Drivers/CMSIS/Include/cmsis_gcc.h ****
955:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
956:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts
957:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
958:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
959:Drivers/CMSIS/Include/cmsis_gcc.h **** */
960:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
271 .loc 2 960 27 view .LVU64
272 .LBB11:
961:Drivers/CMSIS/Include/cmsis_gcc.h **** {
962:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory");
273 .loc 2 962 3 view .LVU65
274 .syntax unified
275 @ 962 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
276 0000 72B6 cpsid i
277 @ 0 "" 2
278 .thumb
279 .syntax unified
280 .L10:
281 .LBE11:
282 .LBE10:
319:Core/Src/main.c **** while (1)
283 .loc 1 319 3 view .LVU66
320:Core/Src/main.c **** {
321:Core/Src/main.c **** }
284 .loc 1 321 3 view .LVU67
319:Core/Src/main.c **** while (1)
285 .loc 1 319 9 view .LVU68
286 0002 FEE7 b .L10
287 .cfi_endproc
288 .LFE248:
290 .section .text.MX_ADC1_Init,"ax",%progbits
291 .align 1
292 .syntax unified
293 .thumb
294 .thumb_func
296 MX_ADC1_Init:
297 .LFB245:
201:Core/Src/main.c ****
298 .loc 1 201 1 view -0
299 .cfi_startproc
300 @ args = 0, pretend = 0, frame = 16
301 @ frame_needed = 0, uses_anonymous_args = 0
302 0000 00B5 push {lr}
303 .LCFI6:
304 .cfi_def_cfa_offset 4
305 .cfi_offset 14, -4
306 0002 85B0 sub sp, sp, #20
307 .LCFI7:
308 .cfi_def_cfa_offset 24
ARM GAS /tmp/cc6ou28t.s page 29
207:Core/Src/main.c ****
309 .loc 1 207 3 view .LVU70
207:Core/Src/main.c ****
310 .loc 1 207 26 is_stmt 0 view .LVU71
311 0004 0023 movs r3, #0
312 0006 0093 str r3, [sp]
313 0008 0193 str r3, [sp, #4]
314 000a 0293 str r3, [sp, #8]
315 000c 0393 str r3, [sp, #12]
215:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
316 .loc 1 215 3 is_stmt 1 view .LVU72
215:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
317 .loc 1 215 18 is_stmt 0 view .LVU73
318 000e 1648 ldr r0, .L17
319 0010 164A ldr r2, .L17+4
320 0012 0260 str r2, [r0]
216:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B;
321 .loc 1 216 3 is_stmt 1 view .LVU74
216:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B;
322 .loc 1 216 29 is_stmt 0 view .LVU75
323 0014 4FF48032 mov r2, #65536
324 0018 4260 str r2, [r0, #4]
217:Core/Src/main.c **** hadc1.Init.ScanConvMode = DISABLE;
325 .loc 1 217 3 is_stmt 1 view .LVU76
217:Core/Src/main.c **** hadc1.Init.ScanConvMode = DISABLE;
326 .loc 1 217 25 is_stmt 0 view .LVU77
327 001a 8360 str r3, [r0, #8]
218:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE;
328 .loc 1 218 3 is_stmt 1 view .LVU78
218:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE;
329 .loc 1 218 27 is_stmt 0 view .LVU79
330 001c 0361 str r3, [r0, #16]
219:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE;
331 .loc 1 219 3 is_stmt 1 view .LVU80
219:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE;
332 .loc 1 219 33 is_stmt 0 view .LVU81
333 001e 0376 strb r3, [r0, #24]
220:Core/Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
334 .loc 1 220 3 is_stmt 1 view .LVU82
220:Core/Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
335 .loc 1 220 36 is_stmt 0 view .LVU83
336 0020 80F82030 strb r3, [r0, #32]
221:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_Ext_IT11;
337 .loc 1 221 3 is_stmt 1 view .LVU84
221:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_Ext_IT11;
338 .loc 1 221 35 is_stmt 0 view .LVU85
339 0024 4FF08052 mov r2, #268435456
340 0028 C262 str r2, [r0, #44]
222:Core/Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
341 .loc 1 222 3 is_stmt 1 view .LVU86
222:Core/Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
342 .loc 1 222 31 is_stmt 0 view .LVU87
343 002a 4FF07062 mov r2, #251658240
344 002e 8262 str r2, [r0, #40]
223:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1;
345 .loc 1 223 3 is_stmt 1 view .LVU88
223:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1;
ARM GAS /tmp/cc6ou28t.s page 30
346 .loc 1 223 24 is_stmt 0 view .LVU89
347 0030 C360 str r3, [r0, #12]
224:Core/Src/main.c **** hadc1.Init.DMAContinuousRequests = ENABLE;
348 .loc 1 224 3 is_stmt 1 view .LVU90
224:Core/Src/main.c **** hadc1.Init.DMAContinuousRequests = ENABLE;
349 .loc 1 224 30 is_stmt 0 view .LVU91
350 0032 0123 movs r3, #1
351 0034 C361 str r3, [r0, #28]
225:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
352 .loc 1 225 3 is_stmt 1 view .LVU92
225:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
353 .loc 1 225 36 is_stmt 0 view .LVU93
354 0036 80F83030 strb r3, [r0, #48]
226:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK)
355 .loc 1 226 3 is_stmt 1 view .LVU94
226:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK)
356 .loc 1 226 27 is_stmt 0 view .LVU95
357 003a 4361 str r3, [r0, #20]
227:Core/Src/main.c **** {
358 .loc 1 227 3 is_stmt 1 view .LVU96
227:Core/Src/main.c **** {
359 .loc 1 227 7 is_stmt 0 view .LVU97
360 003c FFF7FEFF bl HAL_ADC_Init
361 .LVL6:
227:Core/Src/main.c **** {
362 .loc 1 227 6 discriminator 1 view .LVU98
363 0040 68B9 cbnz r0, .L15
234:Core/Src/main.c **** sConfig.Rank = 1;
364 .loc 1 234 3 is_stmt 1 view .LVU99
234:Core/Src/main.c **** sConfig.Rank = 1;
365 .loc 1 234 19 is_stmt 0 view .LVU100
366 0042 0323 movs r3, #3
367 0044 0093 str r3, [sp]
235:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
368 .loc 1 235 3 is_stmt 1 view .LVU101
235:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
369 .loc 1 235 16 is_stmt 0 view .LVU102
370 0046 0123 movs r3, #1
371 0048 0193 str r3, [sp, #4]
236:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
372 .loc 1 236 3 is_stmt 1 view .LVU103
236:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
373 .loc 1 236 24 is_stmt 0 view .LVU104
374 004a 0023 movs r3, #0
375 004c 0293 str r3, [sp, #8]
237:Core/Src/main.c **** {
376 .loc 1 237 3 is_stmt 1 view .LVU105
237:Core/Src/main.c **** {
377 .loc 1 237 7 is_stmt 0 view .LVU106
378 004e 6946 mov r1, sp
379 0050 0548 ldr r0, .L17
380 0052 FFF7FEFF bl HAL_ADC_ConfigChannel
381 .LVL7:
237:Core/Src/main.c **** {
382 .loc 1 237 6 discriminator 1 view .LVU107
383 0056 20B9 cbnz r0, .L16
245:Core/Src/main.c ****
ARM GAS /tmp/cc6ou28t.s page 31
384 .loc 1 245 1 view .LVU108
385 0058 05B0 add sp, sp, #20
386 .LCFI8:
387 .cfi_remember_state
388 .cfi_def_cfa_offset 4
389 @ sp needed
390 005a 5DF804FB ldr pc, [sp], #4
391 .L15:
392 .LCFI9:
393 .cfi_restore_state
229:Core/Src/main.c **** }
394 .loc 1 229 5 is_stmt 1 view .LVU109
395 005e FFF7FEFF bl Error_Handler
396 .LVL8:
397 .L16:
239:Core/Src/main.c **** }
398 .loc 1 239 5 view .LVU110
399 0062 FFF7FEFF bl Error_Handler
400 .LVL9:
401 .L18:
402 0066 00BF .align 2
403 .L17:
404 0068 00000000 .word hadc1
405 006c 00200140 .word 1073815552
406 .cfi_endproc
407 .LFE245:
409 .section .text.SystemClock_Config,"ax",%progbits
410 .align 1
411 .global SystemClock_Config
412 .syntax unified
413 .thumb
414 .thumb_func
416 SystemClock_Config:
417 .LFB244:
155:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0};
418 .loc 1 155 1 view -0
419 .cfi_startproc
420 @ args = 0, pretend = 0, frame = 80
421 @ frame_needed = 0, uses_anonymous_args = 0
422 0000 00B5 push {lr}
423 .LCFI10:
424 .cfi_def_cfa_offset 4
425 .cfi_offset 14, -4
426 0002 95B0 sub sp, sp, #84
427 .LCFI11:
428 .cfi_def_cfa_offset 88
156:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
429 .loc 1 156 3 view .LVU112
156:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
430 .loc 1 156 22 is_stmt 0 view .LVU113
431 0004 3022 movs r2, #48
432 0006 0021 movs r1, #0
433 0008 08A8 add r0, sp, #32
434 000a FFF7FEFF bl memset
435 .LVL10:
157:Core/Src/main.c ****
436 .loc 1 157 3 is_stmt 1 view .LVU114
ARM GAS /tmp/cc6ou28t.s page 32
157:Core/Src/main.c ****
437 .loc 1 157 22 is_stmt 0 view .LVU115
438 000e 0023 movs r3, #0
439 0010 0393 str r3, [sp, #12]
440 0012 0493 str r3, [sp, #16]
441 0014 0593 str r3, [sp, #20]
442 0016 0693 str r3, [sp, #24]
443 0018 0793 str r3, [sp, #28]
161:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
444 .loc 1 161 3 is_stmt 1 view .LVU116
445 .LBB12:
161:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
446 .loc 1 161 3 view .LVU117
447 001a 0193 str r3, [sp, #4]
161:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
448 .loc 1 161 3 view .LVU118
449 001c 214A ldr r2, .L25
450 001e 116C ldr r1, [r2, #64]
451 0020 41F08051 orr r1, r1, #268435456
452 0024 1164 str r1, [r2, #64]
161:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
453 .loc 1 161 3 view .LVU119
454 0026 126C ldr r2, [r2, #64]
455 0028 02F08052 and r2, r2, #268435456
456 002c 0192 str r2, [sp, #4]
161:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
457 .loc 1 161 3 view .LVU120
458 002e 019A ldr r2, [sp, #4]
459 .LBE12:
161:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
460 .loc 1 161 3 view .LVU121
162:Core/Src/main.c ****
461 .loc 1 162 3 view .LVU122
462 .LBB13:
162:Core/Src/main.c ****
463 .loc 1 162 3 view .LVU123
464 0030 0293 str r3, [sp, #8]
162:Core/Src/main.c ****
465 .loc 1 162 3 view .LVU124
466 0032 1D4B ldr r3, .L25+4
467 0034 1A68 ldr r2, [r3]
468 0036 42F44042 orr r2, r2, #49152
469 003a 1A60 str r2, [r3]
162:Core/Src/main.c ****
470 .loc 1 162 3 view .LVU125
471 003c 1B68 ldr r3, [r3]
472 003e 03F44043 and r3, r3, #49152
473 0042 0293 str r3, [sp, #8]
162:Core/Src/main.c ****
474 .loc 1 162 3 view .LVU126
475 0044 029B ldr r3, [sp, #8]
476 .LBE13:
162:Core/Src/main.c ****
477 .loc 1 162 3 view .LVU127
167:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON;
478 .loc 1 167 3 view .LVU128
167:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON;
ARM GAS /tmp/cc6ou28t.s page 33
479 .loc 1 167 36 is_stmt 0 view .LVU129
480 0046 0123 movs r3, #1
481 0048 0893 str r3, [sp, #32]
168:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
482 .loc 1 168 3 is_stmt 1 view .LVU130
168:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
483 .loc 1 168 30 is_stmt 0 view .LVU131
484 004a 4FF48033 mov r3, #65536
485 004e 0993 str r3, [sp, #36]
169:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
486 .loc 1 169 3 is_stmt 1 view .LVU132
169:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
487 .loc 1 169 34 is_stmt 0 view .LVU133
488 0050 0223 movs r3, #2
489 0052 0E93 str r3, [sp, #56]
170:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 8;
490 .loc 1 170 3 is_stmt 1 view .LVU134
170:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 8;
491 .loc 1 170 35 is_stmt 0 view .LVU135
492 0054 4FF48002 mov r2, #4194304
493 0058 0F92 str r2, [sp, #60]
171:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 336;
494 .loc 1 171 3 is_stmt 1 view .LVU136
171:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 336;
495 .loc 1 171 30 is_stmt 0 view .LVU137
496 005a 0822 movs r2, #8
497 005c 1092 str r2, [sp, #64]
172:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
498 .loc 1 172 3 is_stmt 1 view .LVU138
172:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
499 .loc 1 172 30 is_stmt 0 view .LVU139
500 005e 4FF4A872 mov r2, #336
501 0062 1192 str r2, [sp, #68]
173:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 7;
502 .loc 1 173 3 is_stmt 1 view .LVU140
173:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 7;
503 .loc 1 173 30 is_stmt 0 view .LVU141
504 0064 1293 str r3, [sp, #72]
174:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
505 .loc 1 174 3 is_stmt 1 view .LVU142
174:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
506 .loc 1 174 30 is_stmt 0 view .LVU143
507 0066 0723 movs r3, #7
508 0068 1393 str r3, [sp, #76]
175:Core/Src/main.c **** {
509 .loc 1 175 3 is_stmt 1 view .LVU144
175:Core/Src/main.c **** {
510 .loc 1 175 7 is_stmt 0 view .LVU145
511 006a 08A8 add r0, sp, #32
512 006c FFF7FEFF bl HAL_RCC_OscConfig
513 .LVL11:
175:Core/Src/main.c **** {
514 .loc 1 175 6 discriminator 1 view .LVU146
515 0070 98B9 cbnz r0, .L23
182:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
516 .loc 1 182 3 is_stmt 1 view .LVU147
182:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
ARM GAS /tmp/cc6ou28t.s page 34
517 .loc 1 182 31 is_stmt 0 view .LVU148
518 0072 0F23 movs r3, #15
519 0074 0393 str r3, [sp, #12]
184:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
520 .loc 1 184 3 is_stmt 1 view .LVU149
184:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
521 .loc 1 184 34 is_stmt 0 view .LVU150
522 0076 0223 movs r3, #2
523 0078 0493 str r3, [sp, #16]
185:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
524 .loc 1 185 3 is_stmt 1 view .LVU151
185:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
525 .loc 1 185 35 is_stmt 0 view .LVU152
526 007a 0023 movs r3, #0
527 007c 0593 str r3, [sp, #20]
186:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
528 .loc 1 186 3 is_stmt 1 view .LVU153
186:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
529 .loc 1 186 36 is_stmt 0 view .LVU154
530 007e 4FF4A053 mov r3, #5120
531 0082 0693 str r3, [sp, #24]
187:Core/Src/main.c ****
532 .loc 1 187 3 is_stmt 1 view .LVU155
187:Core/Src/main.c ****
533 .loc 1 187 36 is_stmt 0 view .LVU156
534 0084 4FF48053 mov r3, #4096
535 0088 0793 str r3, [sp, #28]
189:Core/Src/main.c **** {
536 .loc 1 189 3 is_stmt 1 view .LVU157
189:Core/Src/main.c **** {
537 .loc 1 189 7 is_stmt 0 view .LVU158
538 008a 0521 movs r1, #5
539 008c 03A8 add r0, sp, #12
540 008e FFF7FEFF bl HAL_RCC_ClockConfig
541 .LVL12:
189:Core/Src/main.c **** {
542 .loc 1 189 6 discriminator 1 view .LVU159
543 0092 20B9 cbnz r0, .L24
193:Core/Src/main.c ****
544 .loc 1 193 1 view .LVU160
545 0094 15B0 add sp, sp, #84
546 .LCFI12:
547 .cfi_remember_state
548 .cfi_def_cfa_offset 4
549 @ sp needed
550 0096 5DF804FB ldr pc, [sp], #4
551 .L23:
552 .LCFI13:
553 .cfi_restore_state
177:Core/Src/main.c **** }
554 .loc 1 177 5 is_stmt 1 view .LVU161
555 009a FFF7FEFF bl Error_Handler
556 .LVL13:
557 .L24:
191:Core/Src/main.c **** }
558 .loc 1 191 5 view .LVU162
559 009e FFF7FEFF bl Error_Handler
ARM GAS /tmp/cc6ou28t.s page 35
560 .LVL14:
561 .L26:
562 00a2 00BF .align 2
563 .L25:
564 00a4 00380240 .word 1073887232
565 00a8 00700040 .word 1073770496
566 .cfi_endproc
567 .LFE244:
569 .global __aeabi_ldivmod
570 .section .text.main,"ax",%progbits
571 .align 1
572 .global main
573 .syntax unified
574 .thumb
575 .thumb_func
577 main:
578 .LFB243:
77:Core/Src/main.c ****
579 .loc 1 77 1 view -0
580 .cfi_startproc
581 @ Volatile: function does not return.
582 @ args = 0, pretend = 0, frame = 0
583 @ frame_needed = 0, uses_anonymous_args = 0
584 0000 08B5 push {r3, lr}
585 .LCFI14:
586 .cfi_def_cfa_offset 8
587 .cfi_offset 3, -8
588 .cfi_offset 14, -4
86:Core/Src/main.c ****
589 .loc 1 86 3 view .LVU164
590 0002 FFF7FEFF bl HAL_Init
591 .LVL15:
93:Core/Src/main.c ****
592 .loc 1 93 3 view .LVU165
593 0006 FFF7FEFF bl SystemClock_Config
594 .LVL16:
100:Core/Src/main.c **** MX_DMA_Init();
595 .loc 1 100 3 view .LVU166
596 000a FFF7FEFF bl MX_GPIO_Init
597 .LVL17:
101:Core/Src/main.c **** MX_ADC1_Init();
598 .loc 1 101 3 view .LVU167
599 000e FFF7FEFF bl MX_DMA_Init
600 .LVL18:
102:Core/Src/main.c **** MX_USB_DEVICE_Init();
601 .loc 1 102 3 view .LVU168
602 0012 FFF7FEFF bl MX_ADC1_Init
603 .LVL19:
103:Core/Src/main.c **** /* USER CODE BEGIN 2 */
604 .loc 1 103 3 view .LVU169
605 0016 FFF7FEFF bl MX_USB_DEVICE_Init
606 .LVL20:
105:Core/Src/main.c **** HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADC1_buff_circular, ADC_BUFF_SIZE);
607 .loc 1 105 3 view .LVU170
608 001a 0122 movs r2, #1
609 001c 8021 movs r1, #128
610 001e 6848 ldr r0, .L32+8
ARM GAS /tmp/cc6ou28t.s page 36
611 0020 FFF7FEFF bl HAL_GPIO_WritePin
612 .LVL21:
106:Core/Src/main.c **** adc_process.status = 0; // ADC started
613 .loc 1 106 3 view .LVU171
614 0024 6422 movs r2, #100
615 0026 6749 ldr r1, .L32+12
616 0028 6748 ldr r0, .L32+16
617 002a FFF7FEFF bl HAL_ADC_Start_DMA
618 .LVL22:
107:Core/Src/main.c **** adc_process.N = 0;
619 .loc 1 107 3 view .LVU172
107:Core/Src/main.c **** adc_process.N = 0;
620 .loc 1 107 22 is_stmt 0 view .LVU173
621 002e 674B ldr r3, .L32+20
622 0030 0022 movs r2, #0
623 0032 1A70 strb r2, [r3]
108:Core/Src/main.c **** adc_process.sum = 0;
624 .loc 1 108 3 is_stmt 1 view .LVU174
108:Core/Src/main.c **** adc_process.sum = 0;
625 .loc 1 108 17 is_stmt 0 view .LVU175
626 0034 DA60 str r2, [r3, #12]
109:Core/Src/main.c **** adc_process.avg = 0;
627 .loc 1 109 3 is_stmt 1 view .LVU176
109:Core/Src/main.c **** adc_process.avg = 0;
628 .loc 1 109 19 is_stmt 0 view .LVU177
629 0036 5A60 str r2, [r3, #4]
110:Core/Src/main.c ****
630 .loc 1 110 3 is_stmt 1 view .LVU178
110:Core/Src/main.c ****
631 .loc 1 110 19 is_stmt 0 view .LVU179
632 0038 9A60 str r2, [r3, #8]
633 .L28:
116:Core/Src/main.c **** {
634 .loc 1 116 3 is_stmt 1 view .LVU180
118:Core/Src/main.c **** //HAL_Delay(100);
635 .loc 1 118 5 view .LVU181
636 003a 4FF48041 mov r1, #16384
637 003e 6048 ldr r0, .L32+8
638 0040 FFF7FEFF bl HAL_GPIO_TogglePin
639 .LVL23:
121:Core/Src/main.c **** adc_process.avg = adc_process.sum / adc_process.N;
640 .loc 1 121 5 view .LVU182
121:Core/Src/main.c **** adc_process.avg = adc_process.sum / adc_process.N;
641 .loc 1 121 20 is_stmt 0 view .LVU183
642 0044 614B ldr r3, .L32+20
643 0046 1B78 ldrb r3, [r3] @ zero_extendqisi2
121:Core/Src/main.c **** adc_process.avg = adc_process.sum / adc_process.N;
644 .loc 1 121 8 view .LVU184
645 0048 022B cmp r3, #2
646 004a F6D1 bne .L28
647 .LBB14:
122:Core/Src/main.c **** adc_process.status = 1; // reset for next accumulation
648 .loc 1 122 7 is_stmt 1 view .LVU185
122:Core/Src/main.c **** adc_process.status = 1; // reset for next accumulation
649 .loc 1 122 36 is_stmt 0 view .LVU186
650 004c 5F4B ldr r3, .L32+20
651 004e 5C68 ldr r4, [r3, #4]
ARM GAS /tmp/cc6ou28t.s page 37
122:Core/Src/main.c **** adc_process.status = 1; // reset for next accumulation
652 .loc 1 122 54 view .LVU187
653 0050 DA68 ldr r2, [r3, #12]
122:Core/Src/main.c **** adc_process.status = 1; // reset for next accumulation
654 .loc 1 122 41 view .LVU188
655 0052 B4FBF2F4 udiv r4, r4, r2
122:Core/Src/main.c **** adc_process.status = 1; // reset for next accumulation
656 .loc 1 122 23 view .LVU189
657 0056 9C60 str r4, [r3, #8]
123:Core/Src/main.c **** adc_process.sum = 0;
658 .loc 1 123 7 is_stmt 1 view .LVU190
123:Core/Src/main.c **** adc_process.sum = 0;
659 .loc 1 123 26 is_stmt 0 view .LVU191
660 0058 0122 movs r2, #1
661 005a 1A70 strb r2, [r3]
124:Core/Src/main.c **** adc_process.N = 0;
662 .loc 1 124 7 is_stmt 1 view .LVU192
124:Core/Src/main.c **** adc_process.N = 0;
663 .loc 1 124 23 is_stmt 0 view .LVU193
664 005c 0021 movs r1, #0
665 005e 5960 str r1, [r3, #4]
125:Core/Src/main.c ****
666 .loc 1 125 7 is_stmt 1 view .LVU194
125:Core/Src/main.c ****
667 .loc 1 125 21 is_stmt 0 view .LVU195
668 0060 D960 str r1, [r3, #12]
128:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 1] = (adc_process.avg / 1000000000) % 10 + '0';
669 .loc 1 128 7 is_stmt 1 view .LVU196
128:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 1] = (adc_process.avg / 1000000000) % 10 + '0';
670 .loc 1 128 55 is_stmt 0 view .LVU197
671 0062 55A3 adr r3, .L32
672 0064 D3E90023 ldrd r2, [r3]
673 0068 2046 mov r0, r4
674 006a FFF7FEFF bl __aeabi_ldivmod
675 .LVL24:
676 006e 8446 mov ip, r0
128:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 1] = (adc_process.avg / 1000000000) % 10 + '0';
677 .loc 1 128 70 view .LVU198
678 0070 4FEAE17E asr lr, r1, #31
679 0074 0EF00302 and r2, lr, #3
680 0078 20F07043 bic r3, r0, #-268435456
681 007c 000F lsrs r0, r0, #28
682 007e 40EA0110 orr r0, r0, r1, lsl #4
683 0082 20F07040 bic r0, r0, #-268435456
684 0086 0344 add r3, r3, r0
685 0088 03EB1163 add r3, r3, r1, lsr #24
686 008c 1344 add r3, r3, r2
687 008e 504A ldr r2, .L32+24
688 0090 A2FB0305 umull r0, r5, r2, r3
689 0094 25F00300 bic r0, r5, #3
690 0098 00EB9500 add r0, r0, r5, lsr #2
691 009c 1B1A subs r3, r3, r0
692 009e 2EF0030E bic lr, lr, #3
693 00a2 7344 add r3, r3, lr
694 00a4 BCEB0300 subs r0, ip, r3
695 00a8 61EBE371 sbc r1, r1, r3, asr #31
696 00ac 4FF0CC33 mov r3, #-858993460
ARM GAS /tmp/cc6ou28t.s page 38
697 00b0 00FB03F3 mul r3, r0, r3
698 00b4 02FB0133 mla r3, r2, r1, r3
699 00b8 A0FB0202 umull r0, r2, r0, r2
700 00bc 1A44 add r2, r2, r3
701 00be D30F lsrs r3, r2, #31
702 00c0 1B18 adds r3, r3, r0
703 00c2 42F10002 adc r2, r2, #0
704 00c6 5B08 lsrs r3, r3, #1
705 00c8 43EAC273 orr r3, r3, r2, lsl #31
706 00cc 03EB8303 add r3, r3, r3, lsl #2
707 00d0 ACEB430C sub ip, ip, r3, lsl #1
128:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 1] = (adc_process.avg / 1000000000) % 10 + '0';
708 .loc 1 128 75 view .LVU199
709 00d4 0CF1300C add ip, ip, #48
128:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 1] = (adc_process.avg / 1000000000) % 10 + '0';
710 .loc 1 128 36 view .LVU200
711 00d8 3E48 ldr r0, .L32+28
712 00da 80F814C0 strb ip, [r0, #20]
129:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 2] = (adc_process.avg / 10000000) % 10 + '0';
713 .loc 1 129 7 is_stmt 1 view .LVU201
129:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 2] = (adc_process.avg / 10000000) % 10 + '0';
714 .loc 1 129 55 is_stmt 0 view .LVU202
715 00de 620A lsrs r2, r4, #9
716 00e0 3D4B ldr r3, .L32+32
717 00e2 A3FB0232 umull r3, r2, r3, r2
129:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 2] = (adc_process.avg / 10000000) % 10 + '0';
718 .loc 1 129 69 view .LVU203
719 00e6 3A4B ldr r3, .L32+24
720 00e8 D209 lsrs r2, r2, #7
129:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 2] = (adc_process.avg / 10000000) % 10 + '0';
721 .loc 1 129 74 view .LVU204
722 00ea 3032 adds r2, r2, #48
129:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 2] = (adc_process.avg / 10000000) % 10 + '0';
723 .loc 1 129 36 view .LVU205
724 00ec 4275 strb r2, [r0, #21]
130:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 3] = (adc_process.avg / 1000000) % 10 + '0';
725 .loc 1 130 7 is_stmt 1 view .LVU206
130:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 3] = (adc_process.avg / 1000000) % 10 + '0';
726 .loc 1 130 55 is_stmt 0 view .LVU207
727 00ee 3B49 ldr r1, .L32+36
728 00f0 A1FB0421 umull r2, r1, r1, r4
729 00f4 890D lsrs r1, r1, #22
130:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 3] = (adc_process.avg / 1000000) % 10 + '0';
730 .loc 1 130 67 view .LVU208
731 00f6 A3FB0152 umull r5, r2, r3, r1
732 00fa D208 lsrs r2, r2, #3
733 00fc 02EB8202 add r2, r2, r2, lsl #2
734 0100 A1EB4202 sub r2, r1, r2, lsl #1
130:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 3] = (adc_process.avg / 1000000) % 10 + '0';
735 .loc 1 130 72 view .LVU209
736 0104 3032 adds r2, r2, #48
130:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 3] = (adc_process.avg / 1000000) % 10 + '0';
737 .loc 1 130 36 view .LVU210
738 0106 8275 strb r2, [r0, #22]
131:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 4] = (adc_process.avg / 100000) % 10 + '0';
739 .loc 1 131 7 is_stmt 1 view .LVU211
131:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 4] = (adc_process.avg / 100000) % 10 + '0';
ARM GAS /tmp/cc6ou28t.s page 39
740 .loc 1 131 55 is_stmt 0 view .LVU212
741 0108 3549 ldr r1, .L32+40
742 010a A1FB0421 umull r2, r1, r1, r4
743 010e 890C lsrs r1, r1, #18
131:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 4] = (adc_process.avg / 100000) % 10 + '0';
744 .loc 1 131 66 view .LVU213
745 0110 A3FB0152 umull r5, r2, r3, r1
746 0114 D208 lsrs r2, r2, #3
747 0116 02EB8202 add r2, r2, r2, lsl #2
748 011a A1EB4202 sub r2, r1, r2, lsl #1
131:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 4] = (adc_process.avg / 100000) % 10 + '0';
749 .loc 1 131 71 view .LVU214
750 011e 3032 adds r2, r2, #48
131:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 4] = (adc_process.avg / 100000) % 10 + '0';
751 .loc 1 131 36 view .LVU215
752 0120 C275 strb r2, [r0, #23]
132:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 5] = (adc_process.avg / 10000) % 10 + '0';
753 .loc 1 132 7 is_stmt 1 view .LVU216
132:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 5] = (adc_process.avg / 10000) % 10 + '0';
754 .loc 1 132 55 is_stmt 0 view .LVU217
755 0122 6109 lsrs r1, r4, #5
756 0124 2F4A ldr r2, .L32+44
757 0126 A2FB0121 umull r2, r1, r2, r1
758 012a C909 lsrs r1, r1, #7
132:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 5] = (adc_process.avg / 10000) % 10 + '0';
759 .loc 1 132 65 view .LVU218
760 012c A3FB0152 umull r5, r2, r3, r1
761 0130 D208 lsrs r2, r2, #3
762 0132 02EB8202 add r2, r2, r2, lsl #2
763 0136 A1EB4202 sub r2, r1, r2, lsl #1
132:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 5] = (adc_process.avg / 10000) % 10 + '0';
764 .loc 1 132 70 view .LVU219
765 013a 3032 adds r2, r2, #48
132:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 5] = (adc_process.avg / 10000) % 10 + '0';
766 .loc 1 132 36 view .LVU220
767 013c 0276 strb r2, [r0, #24]
133:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 6] = (adc_process.avg / 1000) % 10 + '0';
768 .loc 1 133 7 is_stmt 1 view .LVU221
133:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 6] = (adc_process.avg / 1000) % 10 + '0';
769 .loc 1 133 55 is_stmt 0 view .LVU222
770 013e 2A49 ldr r1, .L32+48
771 0140 A1FB0421 umull r2, r1, r1, r4
772 0144 490B lsrs r1, r1, #13
133:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 6] = (adc_process.avg / 1000) % 10 + '0';
773 .loc 1 133 64 view .LVU223
774 0146 A3FB0152 umull r5, r2, r3, r1
775 014a D208 lsrs r2, r2, #3
776 014c 02EB8202 add r2, r2, r2, lsl #2
777 0150 A1EB4202 sub r2, r1, r2, lsl #1
133:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 6] = (adc_process.avg / 1000) % 10 + '0';
778 .loc 1 133 69 view .LVU224
779 0154 3032 adds r2, r2, #48
133:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 6] = (adc_process.avg / 1000) % 10 + '0';
780 .loc 1 133 36 view .LVU225
781 0156 4276 strb r2, [r0, #25]
134:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 7] = (adc_process.avg / 100) % 10 + '0';
782 .loc 1 134 7 is_stmt 1 view .LVU226
ARM GAS /tmp/cc6ou28t.s page 40
134:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 7] = (adc_process.avg / 100) % 10 + '0';
783 .loc 1 134 55 is_stmt 0 view .LVU227
784 0158 2449 ldr r1, .L32+52
785 015a A1FB0421 umull r2, r1, r1, r4
786 015e 8909 lsrs r1, r1, #6
134:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 7] = (adc_process.avg / 100) % 10 + '0';
787 .loc 1 134 63 view .LVU228
788 0160 A3FB0152 umull r5, r2, r3, r1
789 0164 D208 lsrs r2, r2, #3
790 0166 02EB8202 add r2, r2, r2, lsl #2
791 016a A1EB4202 sub r2, r1, r2, lsl #1
134:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 7] = (adc_process.avg / 100) % 10 + '0';
792 .loc 1 134 68 view .LVU229
793 016e 3032 adds r2, r2, #48
134:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 7] = (adc_process.avg / 100) % 10 + '0';
794 .loc 1 134 36 view .LVU230
795 0170 8276 strb r2, [r0, #26]
135:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 8] = (adc_process.avg / 10) % 10 + '0';
796 .loc 1 135 7 is_stmt 1 view .LVU231
135:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 8] = (adc_process.avg / 10) % 10 + '0';
797 .loc 1 135 55 is_stmt 0 view .LVU232
798 0172 1F49 ldr r1, .L32+56
799 0174 A1FB0421 umull r2, r1, r1, r4
800 0178 4909 lsrs r1, r1, #5
135:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 8] = (adc_process.avg / 10) % 10 + '0';
801 .loc 1 135 62 view .LVU233
802 017a A3FB0152 umull r5, r2, r3, r1
803 017e D208 lsrs r2, r2, #3
804 0180 02EB8202 add r2, r2, r2, lsl #2
805 0184 A1EB4202 sub r2, r1, r2, lsl #1
135:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 8] = (adc_process.avg / 10) % 10 + '0';
806 .loc 1 135 67 view .LVU234
807 0188 3032 adds r2, r2, #48
135:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 8] = (adc_process.avg / 10) % 10 + '0';
808 .loc 1 135 36 view .LVU235
809 018a C276 strb r2, [r0, #27]
136:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 9] = (adc_process.avg / 1) % 10 + '0';
810 .loc 1 136 7 is_stmt 1 view .LVU236
136:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 9] = (adc_process.avg / 1) % 10 + '0';
811 .loc 1 136 55 is_stmt 0 view .LVU237
812 018c A3FB0412 umull r1, r2, r3, r4
813 0190 D208 lsrs r2, r2, #3
136:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 9] = (adc_process.avg / 1) % 10 + '0';
814 .loc 1 136 61 view .LVU238
815 0192 A3FB0213 umull r1, r3, r3, r2
816 0196 DB08 lsrs r3, r3, #3
817 0198 03EB8303 add r3, r3, r3, lsl #2
818 019c A2EB4303 sub r3, r2, r3, lsl #1
136:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 9] = (adc_process.avg / 1) % 10 + '0';
819 .loc 1 136 66 view .LVU239
820 01a0 3033 adds r3, r3, #48
136:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 9] = (adc_process.avg / 1) % 10 + '0';
821 .loc 1 136 36 view .LVU240
822 01a2 0377 strb r3, [r0, #28]
137:Core/Src/main.c **** CDC_Transmit_FS((uint8_t *)ADC_msg, ADC_msg_len);
823 .loc 1 137 7 is_stmt 1 view .LVU241
137:Core/Src/main.c **** CDC_Transmit_FS((uint8_t *)ADC_msg, ADC_msg_len);
ARM GAS /tmp/cc6ou28t.s page 41
824 .loc 1 137 60 is_stmt 0 view .LVU242
825 01a4 02EB8202 add r2, r2, r2, lsl #2
826 01a8 A4EB4204 sub r4, r4, r2, lsl #1
137:Core/Src/main.c **** CDC_Transmit_FS((uint8_t *)ADC_msg, ADC_msg_len);
827 .loc 1 137 65 view .LVU243
828 01ac 3034 adds r4, r4, #48
137:Core/Src/main.c **** CDC_Transmit_FS((uint8_t *)ADC_msg, ADC_msg_len);
829 .loc 1 137 36 view .LVU244
830 01ae 4477 strb r4, [r0, #29]
138:Core/Src/main.c ****
831 .loc 1 138 7 is_stmt 1 view .LVU245
832 01b0 2021 movs r1, #32
833 01b2 FFF7FEFF bl CDC_Transmit_FS
834 .LVL25:
835 01b6 40E7 b .L28
836 .L33:
837 .align 3
838 .L32:
839 01b8 00E40B54 .word 1410065408
840 01bc 02000000 .word 2
841 01c0 00040240 .word 1073873920
842 01c4 00000000 .word ADC1_buff_circular
843 01c8 00000000 .word hadc1
844 01cc 00000000 .word adc_process
845 01d0 CDCCCCCC .word -858993459
846 01d4 00000000 .word ADC_msg
847 01d8 834B0400 .word 281475
848 01dc 6BCA5F6B .word 1801439851
849 01e0 83DE1B43 .word 1125899907
850 01e4 C55A7C0A .word 175921861
851 01e8 5917B7D1 .word -776530087
852 01ec D34D6210 .word 274877907
853 01f0 1F85EB51 .word 1374389535
854 .LBE14:
855 .cfi_endproc
856 .LFE243:
858 .global ADC_msg
859 .section .data.ADC_msg,"aw"
860 .align 2
863 ADC_msg:
864 0000 52656365 .ascii "Received ADC value: ??????????\015\012\000"
864 69766564
864 20414443
864 2076616C
864 75653A20
865 .global ADC1_buff_circular
866 .section .bss.ADC1_buff_circular,"aw",%nobits
867 .align 2
870 ADC1_buff_circular:
871 0000 00000000 .space 200
871 00000000
871 00000000
871 00000000
871 00000000
872 .global adc_process
873 .section .bss.adc_process,"aw",%nobits
874 .align 2
ARM GAS /tmp/cc6ou28t.s page 42
877 adc_process:
878 0000 00000000 .space 16
878 00000000
878 00000000
878 00000000
879 .global hdma_adc1
880 .section .bss.hdma_adc1,"aw",%nobits
881 .align 2
884 hdma_adc1:
885 0000 00000000 .space 96
885 00000000
885 00000000
885 00000000
885 00000000
886 .global hadc1
887 .section .bss.hadc1,"aw",%nobits
888 .align 2
891 hadc1:
892 0000 00000000 .space 72
892 00000000
892 00000000
892 00000000
892 00000000
893 .text
894 .Letext0:
895 .file 3 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h"
896 .file 4 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h"
897 .file 5 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
898 .file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h"
899 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h"
900 .file 8 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h"
901 .file 9 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h"
902 .file 10 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h"
903 .file 11 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h"
904 .file 12 "Core/Inc/main.h"
905 .file 13 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h"
906 .file 14 "USB_DEVICE/App/usb_device.h"
907 .file 15 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h"
908 .file 16 "<built-in>"
ARM GAS /tmp/cc6ou28t.s page 43
DEFINED SYMBOLS
*ABS*:00000000 main.c
/tmp/cc6ou28t.s:21 .text.MX_GPIO_Init:00000000 $t
/tmp/cc6ou28t.s:26 .text.MX_GPIO_Init:00000000 MX_GPIO_Init
/tmp/cc6ou28t.s:187 .text.MX_GPIO_Init:000000c0 $d
/tmp/cc6ou28t.s:194 .text.MX_DMA_Init:00000000 $t
/tmp/cc6ou28t.s:199 .text.MX_DMA_Init:00000000 MX_DMA_Init
/tmp/cc6ou28t.s:248 .text.MX_DMA_Init:00000030 $d
/tmp/cc6ou28t.s:253 .text.Error_Handler:00000000 $t
/tmp/cc6ou28t.s:259 .text.Error_Handler:00000000 Error_Handler
/tmp/cc6ou28t.s:291 .text.MX_ADC1_Init:00000000 $t
/tmp/cc6ou28t.s:296 .text.MX_ADC1_Init:00000000 MX_ADC1_Init
/tmp/cc6ou28t.s:404 .text.MX_ADC1_Init:00000068 $d
/tmp/cc6ou28t.s:891 .bss.hadc1:00000000 hadc1
/tmp/cc6ou28t.s:410 .text.SystemClock_Config:00000000 $t
/tmp/cc6ou28t.s:416 .text.SystemClock_Config:00000000 SystemClock_Config
/tmp/cc6ou28t.s:564 .text.SystemClock_Config:000000a4 $d
/tmp/cc6ou28t.s:571 .text.main:00000000 $t
/tmp/cc6ou28t.s:577 .text.main:00000000 main
/tmp/cc6ou28t.s:839 .text.main:000001b8 $d
/tmp/cc6ou28t.s:870 .bss.ADC1_buff_circular:00000000 ADC1_buff_circular
/tmp/cc6ou28t.s:877 .bss.adc_process:00000000 adc_process
/tmp/cc6ou28t.s:863 .data.ADC_msg:00000000 ADC_msg
/tmp/cc6ou28t.s:860 .data.ADC_msg:00000000 $d
/tmp/cc6ou28t.s:867 .bss.ADC1_buff_circular:00000000 $d
/tmp/cc6ou28t.s:874 .bss.adc_process:00000000 $d
/tmp/cc6ou28t.s:884 .bss.hdma_adc1:00000000 hdma_adc1
/tmp/cc6ou28t.s:881 .bss.hdma_adc1:00000000 $d
/tmp/cc6ou28t.s:888 .bss.hadc1:00000000 $d
UNDEFINED SYMBOLS
HAL_GPIO_WritePin
HAL_GPIO_Init
HAL_NVIC_SetPriority
HAL_NVIC_EnableIRQ
HAL_ADC_Init
HAL_ADC_ConfigChannel
memset
HAL_RCC_OscConfig
HAL_RCC_ClockConfig
__aeabi_ldivmod
HAL_Init
MX_USB_DEVICE_Init
HAL_ADC_Start_DMA
HAL_GPIO_TogglePin
CDC_Transmit_FS
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