1708 lines
78 KiB
Plaintext
1708 lines
78 KiB
Plaintext
ARM GAS /tmp/ccLQihDm.s page 1
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1 .cpu cortex-m4
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2 .arch armv7e-m
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3 .fpu fpv4-sp-d16
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4 .eabi_attribute 27, 1
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5 .eabi_attribute 28, 1
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6 .eabi_attribute 20, 1
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||
7 .eabi_attribute 21, 1
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8 .eabi_attribute 23, 3
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9 .eabi_attribute 24, 1
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10 .eabi_attribute 25, 1
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11 .eabi_attribute 26, 1
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12 .eabi_attribute 30, 1
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13 .eabi_attribute 34, 1
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14 .eabi_attribute 18, 4
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15 .file "stm32f4xx_it.c"
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16 .text
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17 .Ltext0:
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18 .cfi_sections .debug_frame
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19 .file 1 "Core/Src/stm32f4xx_it.c"
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20 .section .text.NMI_Handler,"ax",%progbits
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21 .align 1
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22 .global NMI_Handler
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23 .syntax unified
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24 .thumb
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25 .thumb_func
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27 NMI_Handler:
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28 .LFB239:
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1:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN Header */
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2:Core/Src/stm32f4xx_it.c **** /**
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3:Core/Src/stm32f4xx_it.c **** ******************************************************************************
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4:Core/Src/stm32f4xx_it.c **** * @file stm32f4xx_it.c
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5:Core/Src/stm32f4xx_it.c **** * @brief Interrupt Service Routines.
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6:Core/Src/stm32f4xx_it.c **** ******************************************************************************
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7:Core/Src/stm32f4xx_it.c **** * @attention
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8:Core/Src/stm32f4xx_it.c **** *
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9:Core/Src/stm32f4xx_it.c **** * Copyright (c) 2025 STMicroelectronics.
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10:Core/Src/stm32f4xx_it.c **** * All rights reserved.
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11:Core/Src/stm32f4xx_it.c **** *
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12:Core/Src/stm32f4xx_it.c **** * This software is licensed under terms that can be found in the LICENSE file
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13:Core/Src/stm32f4xx_it.c **** * in the root directory of this software component.
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14:Core/Src/stm32f4xx_it.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
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15:Core/Src/stm32f4xx_it.c **** *
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16:Core/Src/stm32f4xx_it.c **** ******************************************************************************
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17:Core/Src/stm32f4xx_it.c **** */
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18:Core/Src/stm32f4xx_it.c **** /* USER CODE END Header */
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19:Core/Src/stm32f4xx_it.c ****
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20:Core/Src/stm32f4xx_it.c **** /* Includes ------------------------------------------------------------------*/
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21:Core/Src/stm32f4xx_it.c **** #include "main.h"
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22:Core/Src/stm32f4xx_it.c **** #include "stm32f4xx_it.h"
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23:Core/Src/stm32f4xx_it.c **** /* Private includes ----------------------------------------------------------*/
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24:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN Includes */
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25:Core/Src/stm32f4xx_it.c **** /* USER CODE END Includes */
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26:Core/Src/stm32f4xx_it.c ****
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27:Core/Src/stm32f4xx_it.c **** /* Private typedef -----------------------------------------------------------*/
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28:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN TD */
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29:Core/Src/stm32f4xx_it.c ****
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30:Core/Src/stm32f4xx_it.c **** /* USER CODE END TD */
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ARM GAS /tmp/ccLQihDm.s page 2
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31:Core/Src/stm32f4xx_it.c ****
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32:Core/Src/stm32f4xx_it.c **** /* Private define ------------------------------------------------------------*/
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33:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PD */
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34:Core/Src/stm32f4xx_it.c ****
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35:Core/Src/stm32f4xx_it.c **** /* USER CODE END PD */
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36:Core/Src/stm32f4xx_it.c ****
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37:Core/Src/stm32f4xx_it.c **** /* Private macro -------------------------------------------------------------*/
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38:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PM */
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39:Core/Src/stm32f4xx_it.c ****
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40:Core/Src/stm32f4xx_it.c **** /* USER CODE END PM */
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41:Core/Src/stm32f4xx_it.c ****
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42:Core/Src/stm32f4xx_it.c **** /* Private variables ---------------------------------------------------------*/
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43:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PV */
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44:Core/Src/stm32f4xx_it.c ****
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45:Core/Src/stm32f4xx_it.c **** /* USER CODE END PV */
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46:Core/Src/stm32f4xx_it.c ****
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47:Core/Src/stm32f4xx_it.c **** /* Private function prototypes -----------------------------------------------*/
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48:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PFP */
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49:Core/Src/stm32f4xx_it.c ****
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50:Core/Src/stm32f4xx_it.c **** /* USER CODE END PFP */
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51:Core/Src/stm32f4xx_it.c ****
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52:Core/Src/stm32f4xx_it.c **** /* Private user code ---------------------------------------------------------*/
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53:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN 0 */
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54:Core/Src/stm32f4xx_it.c ****
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55:Core/Src/stm32f4xx_it.c **** /* USER CODE END 0 */
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56:Core/Src/stm32f4xx_it.c ****
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57:Core/Src/stm32f4xx_it.c **** /* External variables --------------------------------------------------------*/
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58:Core/Src/stm32f4xx_it.c **** extern PCD_HandleTypeDef hpcd_USB_OTG_FS;
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59:Core/Src/stm32f4xx_it.c **** extern DMA_HandleTypeDef hdma_adc1;
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60:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN EV */
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61:Core/Src/stm32f4xx_it.c **** /* Externs are provided via main.h; no extra declarations needed here */
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62:Core/Src/stm32f4xx_it.c **** /* USER CODE END EV */
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63:Core/Src/stm32f4xx_it.c ****
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64:Core/Src/stm32f4xx_it.c **** /******************************************************************************/
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65:Core/Src/stm32f4xx_it.c **** /* Cortex-M4 Processor Interruption and Exception Handlers */
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66:Core/Src/stm32f4xx_it.c **** /******************************************************************************/
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67:Core/Src/stm32f4xx_it.c **** /**
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68:Core/Src/stm32f4xx_it.c **** * @brief This function handles Non maskable interrupt.
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69:Core/Src/stm32f4xx_it.c **** */
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70:Core/Src/stm32f4xx_it.c **** void NMI_Handler(void)
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71:Core/Src/stm32f4xx_it.c **** {
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29 .loc 1 71 1 view -0
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30 .cfi_startproc
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31 @ Volatile: function does not return.
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32 @ args = 0, pretend = 0, frame = 0
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33 @ frame_needed = 0, uses_anonymous_args = 0
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34 @ link register save eliminated.
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35 .L2:
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72:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
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73:Core/Src/stm32f4xx_it.c ****
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74:Core/Src/stm32f4xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 0 */
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75:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
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76:Core/Src/stm32f4xx_it.c **** while (1)
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36 .loc 1 76 4 view .LVU1
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77:Core/Src/stm32f4xx_it.c **** {
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78:Core/Src/stm32f4xx_it.c **** }
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37 .loc 1 78 3 view .LVU2
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ARM GAS /tmp/ccLQihDm.s page 3
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76:Core/Src/stm32f4xx_it.c **** {
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38 .loc 1 76 10 view .LVU3
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39 0000 FEE7 b .L2
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40 .cfi_endproc
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41 .LFE239:
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43 .section .text.HardFault_Handler,"ax",%progbits
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44 .align 1
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45 .global HardFault_Handler
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46 .syntax unified
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47 .thumb
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48 .thumb_func
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50 HardFault_Handler:
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51 .LFB240:
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79:Core/Src/stm32f4xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 1 */
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80:Core/Src/stm32f4xx_it.c **** }
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81:Core/Src/stm32f4xx_it.c ****
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82:Core/Src/stm32f4xx_it.c **** /**
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83:Core/Src/stm32f4xx_it.c **** * @brief This function handles Hard fault interrupt.
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84:Core/Src/stm32f4xx_it.c **** */
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85:Core/Src/stm32f4xx_it.c **** void HardFault_Handler(void)
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86:Core/Src/stm32f4xx_it.c **** {
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52 .loc 1 86 1 view -0
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53 .cfi_startproc
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54 @ Volatile: function does not return.
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55 @ args = 0, pretend = 0, frame = 0
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56 @ frame_needed = 0, uses_anonymous_args = 0
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57 @ link register save eliminated.
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58 .L4:
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87:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN HardFault_IRQn 0 */
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88:Core/Src/stm32f4xx_it.c ****
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89:Core/Src/stm32f4xx_it.c **** /* USER CODE END HardFault_IRQn 0 */
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90:Core/Src/stm32f4xx_it.c **** while (1)
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59 .loc 1 90 3 view .LVU5
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91:Core/Src/stm32f4xx_it.c **** {
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92:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_HardFault_IRQn 0 */
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93:Core/Src/stm32f4xx_it.c **** /* USER CODE END W1_HardFault_IRQn 0 */
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94:Core/Src/stm32f4xx_it.c **** }
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60 .loc 1 94 3 view .LVU6
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90:Core/Src/stm32f4xx_it.c **** {
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61 .loc 1 90 9 view .LVU7
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62 0000 FEE7 b .L4
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63 .cfi_endproc
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64 .LFE240:
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66 .section .text.MemManage_Handler,"ax",%progbits
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67 .align 1
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68 .global MemManage_Handler
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69 .syntax unified
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70 .thumb
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71 .thumb_func
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73 MemManage_Handler:
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74 .LFB241:
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95:Core/Src/stm32f4xx_it.c **** }
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96:Core/Src/stm32f4xx_it.c ****
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97:Core/Src/stm32f4xx_it.c **** /**
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98:Core/Src/stm32f4xx_it.c **** * @brief This function handles Memory management fault.
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99:Core/Src/stm32f4xx_it.c **** */
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100:Core/Src/stm32f4xx_it.c **** void MemManage_Handler(void)
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ARM GAS /tmp/ccLQihDm.s page 4
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101:Core/Src/stm32f4xx_it.c **** {
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75 .loc 1 101 1 view -0
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76 .cfi_startproc
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77 @ Volatile: function does not return.
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78 @ args = 0, pretend = 0, frame = 0
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79 @ frame_needed = 0, uses_anonymous_args = 0
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80 @ link register save eliminated.
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81 .L6:
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102:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN MemoryManagement_IRQn 0 */
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103:Core/Src/stm32f4xx_it.c ****
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104:Core/Src/stm32f4xx_it.c **** /* USER CODE END MemoryManagement_IRQn 0 */
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105:Core/Src/stm32f4xx_it.c **** while (1)
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82 .loc 1 105 3 view .LVU9
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106:Core/Src/stm32f4xx_it.c **** {
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107:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
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108:Core/Src/stm32f4xx_it.c **** /* USER CODE END W1_MemoryManagement_IRQn 0 */
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109:Core/Src/stm32f4xx_it.c **** }
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83 .loc 1 109 3 view .LVU10
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105:Core/Src/stm32f4xx_it.c **** {
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84 .loc 1 105 9 view .LVU11
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85 0000 FEE7 b .L6
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86 .cfi_endproc
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87 .LFE241:
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89 .section .text.BusFault_Handler,"ax",%progbits
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90 .align 1
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91 .global BusFault_Handler
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92 .syntax unified
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93 .thumb
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94 .thumb_func
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96 BusFault_Handler:
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97 .LFB242:
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110:Core/Src/stm32f4xx_it.c **** }
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111:Core/Src/stm32f4xx_it.c ****
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112:Core/Src/stm32f4xx_it.c **** /**
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113:Core/Src/stm32f4xx_it.c **** * @brief This function handles Pre-fetch fault, memory access fault.
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114:Core/Src/stm32f4xx_it.c **** */
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115:Core/Src/stm32f4xx_it.c **** void BusFault_Handler(void)
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116:Core/Src/stm32f4xx_it.c **** {
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98 .loc 1 116 1 view -0
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99 .cfi_startproc
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100 @ Volatile: function does not return.
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101 @ args = 0, pretend = 0, frame = 0
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102 @ frame_needed = 0, uses_anonymous_args = 0
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103 @ link register save eliminated.
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104 .L8:
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117:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN BusFault_IRQn 0 */
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118:Core/Src/stm32f4xx_it.c ****
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119:Core/Src/stm32f4xx_it.c **** /* USER CODE END BusFault_IRQn 0 */
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120:Core/Src/stm32f4xx_it.c **** while (1)
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105 .loc 1 120 3 view .LVU13
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121:Core/Src/stm32f4xx_it.c **** {
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122:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_BusFault_IRQn 0 */
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123:Core/Src/stm32f4xx_it.c **** /* USER CODE END W1_BusFault_IRQn 0 */
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124:Core/Src/stm32f4xx_it.c **** }
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106 .loc 1 124 3 view .LVU14
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120:Core/Src/stm32f4xx_it.c **** {
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107 .loc 1 120 9 view .LVU15
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ARM GAS /tmp/ccLQihDm.s page 5
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108 0000 FEE7 b .L8
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109 .cfi_endproc
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110 .LFE242:
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112 .section .text.UsageFault_Handler,"ax",%progbits
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113 .align 1
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114 .global UsageFault_Handler
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115 .syntax unified
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116 .thumb
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117 .thumb_func
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119 UsageFault_Handler:
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120 .LFB243:
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125:Core/Src/stm32f4xx_it.c **** }
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126:Core/Src/stm32f4xx_it.c ****
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127:Core/Src/stm32f4xx_it.c **** /**
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128:Core/Src/stm32f4xx_it.c **** * @brief This function handles Undefined instruction or illegal state.
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129:Core/Src/stm32f4xx_it.c **** */
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130:Core/Src/stm32f4xx_it.c **** void UsageFault_Handler(void)
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131:Core/Src/stm32f4xx_it.c **** {
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121 .loc 1 131 1 view -0
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122 .cfi_startproc
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123 @ Volatile: function does not return.
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124 @ args = 0, pretend = 0, frame = 0
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125 @ frame_needed = 0, uses_anonymous_args = 0
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126 @ link register save eliminated.
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127 .L10:
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132:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN UsageFault_IRQn 0 */
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133:Core/Src/stm32f4xx_it.c ****
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134:Core/Src/stm32f4xx_it.c **** /* USER CODE END UsageFault_IRQn 0 */
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135:Core/Src/stm32f4xx_it.c **** while (1)
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128 .loc 1 135 3 view .LVU17
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136:Core/Src/stm32f4xx_it.c **** {
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137:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
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138:Core/Src/stm32f4xx_it.c **** /* USER CODE END W1_UsageFault_IRQn 0 */
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139:Core/Src/stm32f4xx_it.c **** }
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129 .loc 1 139 3 view .LVU18
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135:Core/Src/stm32f4xx_it.c **** {
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130 .loc 1 135 9 view .LVU19
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131 0000 FEE7 b .L10
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132 .cfi_endproc
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133 .LFE243:
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135 .section .text.SVC_Handler,"ax",%progbits
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136 .align 1
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137 .global SVC_Handler
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138 .syntax unified
|
||
139 .thumb
|
||
140 .thumb_func
|
||
142 SVC_Handler:
|
||
143 .LFB244:
|
||
140:Core/Src/stm32f4xx_it.c **** }
|
||
141:Core/Src/stm32f4xx_it.c ****
|
||
142:Core/Src/stm32f4xx_it.c **** /**
|
||
143:Core/Src/stm32f4xx_it.c **** * @brief This function handles System service call via SWI instruction.
|
||
144:Core/Src/stm32f4xx_it.c **** */
|
||
145:Core/Src/stm32f4xx_it.c **** void SVC_Handler(void)
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||
146:Core/Src/stm32f4xx_it.c **** {
|
||
144 .loc 1 146 1 view -0
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||
145 .cfi_startproc
|
||
ARM GAS /tmp/ccLQihDm.s page 6
|
||
|
||
|
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146 @ args = 0, pretend = 0, frame = 0
|
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147 @ frame_needed = 0, uses_anonymous_args = 0
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||
148 @ link register save eliminated.
|
||
147:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 0 */
|
||
148:Core/Src/stm32f4xx_it.c ****
|
||
149:Core/Src/stm32f4xx_it.c **** /* USER CODE END SVCall_IRQn 0 */
|
||
150:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 1 */
|
||
151:Core/Src/stm32f4xx_it.c ****
|
||
152:Core/Src/stm32f4xx_it.c **** /* USER CODE END SVCall_IRQn 1 */
|
||
153:Core/Src/stm32f4xx_it.c **** }
|
||
149 .loc 1 153 1 view .LVU21
|
||
150 0000 7047 bx lr
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||
151 .cfi_endproc
|
||
152 .LFE244:
|
||
154 .section .text.DebugMon_Handler,"ax",%progbits
|
||
155 .align 1
|
||
156 .global DebugMon_Handler
|
||
157 .syntax unified
|
||
158 .thumb
|
||
159 .thumb_func
|
||
161 DebugMon_Handler:
|
||
162 .LFB245:
|
||
154:Core/Src/stm32f4xx_it.c ****
|
||
155:Core/Src/stm32f4xx_it.c **** /**
|
||
156:Core/Src/stm32f4xx_it.c **** * @brief This function handles Debug monitor.
|
||
157:Core/Src/stm32f4xx_it.c **** */
|
||
158:Core/Src/stm32f4xx_it.c **** void DebugMon_Handler(void)
|
||
159:Core/Src/stm32f4xx_it.c **** {
|
||
163 .loc 1 159 1 view -0
|
||
164 .cfi_startproc
|
||
165 @ args = 0, pretend = 0, frame = 0
|
||
166 @ frame_needed = 0, uses_anonymous_args = 0
|
||
167 @ link register save eliminated.
|
||
160:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 0 */
|
||
161:Core/Src/stm32f4xx_it.c ****
|
||
162:Core/Src/stm32f4xx_it.c **** /* USER CODE END DebugMonitor_IRQn 0 */
|
||
163:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
||
164:Core/Src/stm32f4xx_it.c ****
|
||
165:Core/Src/stm32f4xx_it.c **** /* USER CODE END DebugMonitor_IRQn 1 */
|
||
166:Core/Src/stm32f4xx_it.c **** }
|
||
168 .loc 1 166 1 view .LVU23
|
||
169 0000 7047 bx lr
|
||
170 .cfi_endproc
|
||
171 .LFE245:
|
||
173 .section .text.PendSV_Handler,"ax",%progbits
|
||
174 .align 1
|
||
175 .global PendSV_Handler
|
||
176 .syntax unified
|
||
177 .thumb
|
||
178 .thumb_func
|
||
180 PendSV_Handler:
|
||
181 .LFB246:
|
||
167:Core/Src/stm32f4xx_it.c ****
|
||
168:Core/Src/stm32f4xx_it.c **** /**
|
||
169:Core/Src/stm32f4xx_it.c **** * @brief This function handles Pendable request for system service.
|
||
170:Core/Src/stm32f4xx_it.c **** */
|
||
171:Core/Src/stm32f4xx_it.c **** void PendSV_Handler(void)
|
||
ARM GAS /tmp/ccLQihDm.s page 7
|
||
|
||
|
||
172:Core/Src/stm32f4xx_it.c **** {
|
||
182 .loc 1 172 1 view -0
|
||
183 .cfi_startproc
|
||
184 @ args = 0, pretend = 0, frame = 0
|
||
185 @ frame_needed = 0, uses_anonymous_args = 0
|
||
186 @ link register save eliminated.
|
||
173:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 0 */
|
||
174:Core/Src/stm32f4xx_it.c ****
|
||
175:Core/Src/stm32f4xx_it.c **** /* USER CODE END PendSV_IRQn 0 */
|
||
176:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 1 */
|
||
177:Core/Src/stm32f4xx_it.c ****
|
||
178:Core/Src/stm32f4xx_it.c **** /* USER CODE END PendSV_IRQn 1 */
|
||
179:Core/Src/stm32f4xx_it.c **** }
|
||
187 .loc 1 179 1 view .LVU25
|
||
188 0000 7047 bx lr
|
||
189 .cfi_endproc
|
||
190 .LFE246:
|
||
192 .section .text.SysTick_Handler,"ax",%progbits
|
||
193 .align 1
|
||
194 .global SysTick_Handler
|
||
195 .syntax unified
|
||
196 .thumb
|
||
197 .thumb_func
|
||
199 SysTick_Handler:
|
||
200 .LFB247:
|
||
180:Core/Src/stm32f4xx_it.c ****
|
||
181:Core/Src/stm32f4xx_it.c **** /**
|
||
182:Core/Src/stm32f4xx_it.c **** * @brief This function handles System tick timer.
|
||
183:Core/Src/stm32f4xx_it.c **** */
|
||
184:Core/Src/stm32f4xx_it.c **** void SysTick_Handler(void)
|
||
185:Core/Src/stm32f4xx_it.c **** {
|
||
201 .loc 1 185 1 view -0
|
||
202 .cfi_startproc
|
||
203 @ args = 0, pretend = 0, frame = 0
|
||
204 @ frame_needed = 0, uses_anonymous_args = 0
|
||
205 0000 08B5 push {r3, lr}
|
||
206 .LCFI0:
|
||
207 .cfi_def_cfa_offset 8
|
||
208 .cfi_offset 3, -8
|
||
209 .cfi_offset 14, -4
|
||
186:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 0 */
|
||
187:Core/Src/stm32f4xx_it.c ****
|
||
188:Core/Src/stm32f4xx_it.c **** /* USER CODE END SysTick_IRQn 0 */
|
||
189:Core/Src/stm32f4xx_it.c **** HAL_IncTick();
|
||
210 .loc 1 189 3 view .LVU27
|
||
211 0002 FFF7FEFF bl HAL_IncTick
|
||
212 .LVL0:
|
||
190:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 1 */
|
||
191:Core/Src/stm32f4xx_it.c ****
|
||
192:Core/Src/stm32f4xx_it.c **** /* USER CODE END SysTick_IRQn 1 */
|
||
193:Core/Src/stm32f4xx_it.c **** }
|
||
213 .loc 1 193 1 is_stmt 0 view .LVU28
|
||
214 0006 08BD pop {r3, pc}
|
||
215 .cfi_endproc
|
||
216 .LFE247:
|
||
218 .section .text.EXTI0_IRQHandler,"ax",%progbits
|
||
219 .align 1
|
||
ARM GAS /tmp/ccLQihDm.s page 8
|
||
|
||
|
||
220 .global EXTI0_IRQHandler
|
||
221 .syntax unified
|
||
222 .thumb
|
||
223 .thumb_func
|
||
225 EXTI0_IRQHandler:
|
||
226 .LFB248:
|
||
194:Core/Src/stm32f4xx_it.c ****
|
||
195:Core/Src/stm32f4xx_it.c **** /******************************************************************************/
|
||
196:Core/Src/stm32f4xx_it.c **** /* STM32F4xx Peripheral Interrupt Handlers */
|
||
197:Core/Src/stm32f4xx_it.c **** /* Add here the Interrupt Handlers for the used peripherals. */
|
||
198:Core/Src/stm32f4xx_it.c **** /* For the available peripheral interrupt handler names, */
|
||
199:Core/Src/stm32f4xx_it.c **** /* please refer to the startup file (startup_stm32f4xx.s). */
|
||
200:Core/Src/stm32f4xx_it.c **** /******************************************************************************/
|
||
201:Core/Src/stm32f4xx_it.c ****
|
||
202:Core/Src/stm32f4xx_it.c **** /**
|
||
203:Core/Src/stm32f4xx_it.c **** * @brief This function handles EXTI line0 interrupt.
|
||
204:Core/Src/stm32f4xx_it.c **** */
|
||
205:Core/Src/stm32f4xx_it.c **** void EXTI0_IRQHandler(void)
|
||
206:Core/Src/stm32f4xx_it.c **** {
|
||
227 .loc 1 206 1 is_stmt 1 view -0
|
||
228 .cfi_startproc
|
||
229 @ args = 0, pretend = 0, frame = 0
|
||
230 @ frame_needed = 0, uses_anonymous_args = 0
|
||
231 0000 08B5 push {r3, lr}
|
||
232 .LCFI1:
|
||
233 .cfi_def_cfa_offset 8
|
||
234 .cfi_offset 3, -8
|
||
235 .cfi_offset 14, -4
|
||
207:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN EXTI0_IRQn 0 */
|
||
208:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_start_DMA_N = ADC_BUFF_SIZE - hdma_adc1.Instance->NDTR;
|
||
236 .loc 1 208 3 view .LVU30
|
||
237 .loc 1 208 64 is_stmt 0 view .LVU31
|
||
238 0002 0C4B ldr r3, .L20
|
||
239 0004 1B68 ldr r3, [r3]
|
||
240 .loc 1 208 73 view .LVU32
|
||
241 0006 5B68 ldr r3, [r3, #4]
|
||
242 .loc 1 208 53 view .LVU33
|
||
243 0008 C3F13203 rsb r3, r3, #50
|
||
244 .loc 1 208 37 view .LVU34
|
||
245 000c 0A4A ldr r2, .L20+4
|
||
246 000e 9360 str r3, [r2, #8]
|
||
209:Core/Src/stm32f4xx_it.c **** if (Sweep_state.curr_step_start_DMA_N < ADC_BUFF_SIZE/2) {
|
||
247 .loc 1 209 3 is_stmt 1 view .LVU35
|
||
248 .loc 1 209 18 is_stmt 0 view .LVU36
|
||
249 0010 9368 ldr r3, [r2, #8]
|
||
250 .loc 1 209 6 view .LVU37
|
||
251 0012 182B cmp r3, #24
|
||
252 0014 0AD8 bhi .L17
|
||
210:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag =1; // first half DMA buffer
|
||
253 .loc 1 210 5 is_stmt 1 view .LVU38
|
||
254 .loc 1 210 40 is_stmt 0 view .LVU39
|
||
255 0016 1346 mov r3, r2
|
||
256 0018 0122 movs r2, #1
|
||
257 001a 1A71 strb r2, [r3, #4]
|
||
258 .L18:
|
||
211:Core/Src/stm32f4xx_it.c **** } else{
|
||
212:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag =2; // second half DMA buffer
|
||
ARM GAS /tmp/ccLQihDm.s page 9
|
||
|
||
|
||
213:Core/Src/stm32f4xx_it.c **** }
|
||
214:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_N++;
|
||
259 .loc 1 214 3 is_stmt 1 view .LVU40
|
||
260 .loc 1 214 14 is_stmt 0 view .LVU41
|
||
261 001c 064A ldr r2, .L20+4
|
||
262 001e 1368 ldr r3, [r2]
|
||
263 .loc 1 214 26 view .LVU42
|
||
264 0020 0133 adds r3, r3, #1
|
||
265 0022 1360 str r3, [r2]
|
||
215:Core/Src/stm32f4xx_it.c **** /* USER CODE END EXTI0_IRQn 0 */
|
||
216:Core/Src/stm32f4xx_it.c **** HAL_GPIO_EXTI_IRQHandler(CURR_STEP_START_TRG_Pin);
|
||
266 .loc 1 216 3 is_stmt 1 view .LVU43
|
||
267 0024 0120 movs r0, #1
|
||
268 0026 FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler
|
||
269 .LVL1:
|
||
217:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN EXTI0_IRQn 1 */
|
||
218:Core/Src/stm32f4xx_it.c ****
|
||
219:Core/Src/stm32f4xx_it.c **** /* USER CODE END EXTI0_IRQn 1 */
|
||
220:Core/Src/stm32f4xx_it.c **** }
|
||
270 .loc 1 220 1 is_stmt 0 view .LVU44
|
||
271 002a 08BD pop {r3, pc}
|
||
272 .L17:
|
||
212:Core/Src/stm32f4xx_it.c **** }
|
||
273 .loc 1 212 5 is_stmt 1 view .LVU45
|
||
212:Core/Src/stm32f4xx_it.c **** }
|
||
274 .loc 1 212 40 is_stmt 0 view .LVU46
|
||
275 002c 024B ldr r3, .L20+4
|
||
276 002e 0222 movs r2, #2
|
||
277 0030 1A71 strb r2, [r3, #4]
|
||
278 0032 F3E7 b .L18
|
||
279 .L21:
|
||
280 .align 2
|
||
281 .L20:
|
||
282 0034 00000000 .word hdma_adc1
|
||
283 0038 00000000 .word Sweep_state
|
||
284 .cfi_endproc
|
||
285 .LFE248:
|
||
287 .section .text.EXTI3_IRQHandler,"ax",%progbits
|
||
288 .align 1
|
||
289 .global EXTI3_IRQHandler
|
||
290 .syntax unified
|
||
291 .thumb
|
||
292 .thumb_func
|
||
294 EXTI3_IRQHandler:
|
||
295 .LFB249:
|
||
221:Core/Src/stm32f4xx_it.c ****
|
||
222:Core/Src/stm32f4xx_it.c **** /**
|
||
223:Core/Src/stm32f4xx_it.c **** * @brief This function handles EXTI line3 interrupt.
|
||
224:Core/Src/stm32f4xx_it.c **** */
|
||
225:Core/Src/stm32f4xx_it.c **** void EXTI3_IRQHandler(void)
|
||
226:Core/Src/stm32f4xx_it.c **** {
|
||
296 .loc 1 226 1 is_stmt 1 view -0
|
||
297 .cfi_startproc
|
||
298 @ args = 0, pretend = 0, frame = 0
|
||
299 @ frame_needed = 0, uses_anonymous_args = 0
|
||
300 0000 08B5 push {r3, lr}
|
||
301 .LCFI2:
|
||
ARM GAS /tmp/ccLQihDm.s page 10
|
||
|
||
|
||
302 .cfi_def_cfa_offset 8
|
||
303 .cfi_offset 3, -8
|
||
304 .cfi_offset 14, -4
|
||
227:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN EXTI3_IRQn 0 */
|
||
228:Core/Src/stm32f4xx_it.c **** Sweep_state.sweep_cycle_started_flag = 1; //sweep cycle started
|
||
305 .loc 1 228 3 view .LVU48
|
||
306 .loc 1 228 40 is_stmt 0 view .LVU49
|
||
307 0002 044B ldr r3, .L24
|
||
308 0004 0122 movs r2, #1
|
||
309 0006 1A73 strb r2, [r3, #12]
|
||
229:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_N = 0;
|
||
310 .loc 1 229 3 is_stmt 1 view .LVU50
|
||
311 .loc 1 229 27 is_stmt 0 view .LVU51
|
||
312 0008 0022 movs r2, #0
|
||
313 000a 1A60 str r2, [r3]
|
||
230:Core/Src/stm32f4xx_it.c **** /* USER CODE END EXTI3_IRQn 0 */
|
||
231:Core/Src/stm32f4xx_it.c **** HAL_GPIO_EXTI_IRQHandler(SWEEP_CYCLE_START_TRG_Pin);
|
||
314 .loc 1 231 3 is_stmt 1 view .LVU52
|
||
315 000c 0820 movs r0, #8
|
||
316 000e FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler
|
||
317 .LVL2:
|
||
232:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN EXTI3_IRQn 1 */
|
||
233:Core/Src/stm32f4xx_it.c ****
|
||
234:Core/Src/stm32f4xx_it.c **** /* USER CODE END EXTI3_IRQn 1 */
|
||
235:Core/Src/stm32f4xx_it.c **** }
|
||
318 .loc 1 235 1 is_stmt 0 view .LVU53
|
||
319 0012 08BD pop {r3, pc}
|
||
320 .L25:
|
||
321 .align 2
|
||
322 .L24:
|
||
323 0014 00000000 .word Sweep_state
|
||
324 .cfi_endproc
|
||
325 .LFE249:
|
||
327 .section .text.DMA2_Stream0_IRQHandler,"ax",%progbits
|
||
328 .align 1
|
||
329 .global DMA2_Stream0_IRQHandler
|
||
330 .syntax unified
|
||
331 .thumb
|
||
332 .thumb_func
|
||
334 DMA2_Stream0_IRQHandler:
|
||
335 .LFB250:
|
||
236:Core/Src/stm32f4xx_it.c ****
|
||
237:Core/Src/stm32f4xx_it.c **** /**
|
||
238:Core/Src/stm32f4xx_it.c **** * @brief This function handles DMA2 stream0 global interrupt.
|
||
239:Core/Src/stm32f4xx_it.c **** */
|
||
240:Core/Src/stm32f4xx_it.c **** void DMA2_Stream0_IRQHandler(void)
|
||
241:Core/Src/stm32f4xx_it.c **** {
|
||
336 .loc 1 241 1 is_stmt 1 view -0
|
||
337 .cfi_startproc
|
||
338 @ args = 0, pretend = 0, frame = 0
|
||
339 @ frame_needed = 0, uses_anonymous_args = 0
|
||
340 0000 08B5 push {r3, lr}
|
||
341 .LCFI3:
|
||
342 .cfi_def_cfa_offset 8
|
||
343 .cfi_offset 3, -8
|
||
344 .cfi_offset 14, -4
|
||
242:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN DMA2_Stream0_IRQn 0 */
|
||
ARM GAS /tmp/ccLQihDm.s page 11
|
||
|
||
|
||
243:Core/Src/stm32f4xx_it.c ****
|
||
244:Core/Src/stm32f4xx_it.c **** /* USER CODE END DMA2_Stream0_IRQn 0 */
|
||
245:Core/Src/stm32f4xx_it.c **** HAL_DMA_IRQHandler(&hdma_adc1);
|
||
345 .loc 1 245 3 view .LVU55
|
||
346 0002 0248 ldr r0, .L28
|
||
347 0004 FFF7FEFF bl HAL_DMA_IRQHandler
|
||
348 .LVL3:
|
||
246:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN DMA2_Stream0_IRQn 1 */
|
||
247:Core/Src/stm32f4xx_it.c ****
|
||
248:Core/Src/stm32f4xx_it.c **** /* USER CODE END DMA2_Stream0_IRQn 1 */
|
||
249:Core/Src/stm32f4xx_it.c **** }
|
||
349 .loc 1 249 1 is_stmt 0 view .LVU56
|
||
350 0008 08BD pop {r3, pc}
|
||
351 .L29:
|
||
352 000a 00BF .align 2
|
||
353 .L28:
|
||
354 000c 00000000 .word hdma_adc1
|
||
355 .cfi_endproc
|
||
356 .LFE250:
|
||
358 .section .text.OTG_FS_IRQHandler,"ax",%progbits
|
||
359 .align 1
|
||
360 .global OTG_FS_IRQHandler
|
||
361 .syntax unified
|
||
362 .thumb
|
||
363 .thumb_func
|
||
365 OTG_FS_IRQHandler:
|
||
366 .LFB251:
|
||
250:Core/Src/stm32f4xx_it.c ****
|
||
251:Core/Src/stm32f4xx_it.c **** /**
|
||
252:Core/Src/stm32f4xx_it.c **** * @brief This function handles USB On The Go FS global interrupt.
|
||
253:Core/Src/stm32f4xx_it.c **** */
|
||
254:Core/Src/stm32f4xx_it.c **** void OTG_FS_IRQHandler(void)
|
||
255:Core/Src/stm32f4xx_it.c **** {
|
||
367 .loc 1 255 1 is_stmt 1 view -0
|
||
368 .cfi_startproc
|
||
369 @ args = 0, pretend = 0, frame = 0
|
||
370 @ frame_needed = 0, uses_anonymous_args = 0
|
||
371 0000 08B5 push {r3, lr}
|
||
372 .LCFI4:
|
||
373 .cfi_def_cfa_offset 8
|
||
374 .cfi_offset 3, -8
|
||
375 .cfi_offset 14, -4
|
||
256:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN OTG_FS_IRQn 0 */
|
||
257:Core/Src/stm32f4xx_it.c ****
|
||
258:Core/Src/stm32f4xx_it.c **** /* USER CODE END OTG_FS_IRQn 0 */
|
||
259:Core/Src/stm32f4xx_it.c **** HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS);
|
||
376 .loc 1 259 3 view .LVU58
|
||
377 0002 0248 ldr r0, .L32
|
||
378 0004 FFF7FEFF bl HAL_PCD_IRQHandler
|
||
379 .LVL4:
|
||
260:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN OTG_FS_IRQn 1 */
|
||
261:Core/Src/stm32f4xx_it.c ****
|
||
262:Core/Src/stm32f4xx_it.c **** /* USER CODE END OTG_FS_IRQn 1 */
|
||
263:Core/Src/stm32f4xx_it.c **** }
|
||
380 .loc 1 263 1 is_stmt 0 view .LVU59
|
||
381 0008 08BD pop {r3, pc}
|
||
382 .L33:
|
||
ARM GAS /tmp/ccLQihDm.s page 12
|
||
|
||
|
||
383 000a 00BF .align 2
|
||
384 .L32:
|
||
385 000c 00000000 .word hpcd_USB_OTG_FS
|
||
386 .cfi_endproc
|
||
387 .LFE251:
|
||
389 .section .text.HAL_ADC_ConvCpltCallback,"ax",%progbits
|
||
390 .align 1
|
||
391 .global HAL_ADC_ConvCpltCallback
|
||
392 .syntax unified
|
||
393 .thumb
|
||
394 .thumb_func
|
||
396 HAL_ADC_ConvCpltCallback:
|
||
397 .LVL5:
|
||
398 .LFB252:
|
||
264:Core/Src/stm32f4xx_it.c ****
|
||
265:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN 1 */
|
||
266:Core/Src/stm32f4xx_it.c ****
|
||
267:Core/Src/stm32f4xx_it.c **** #ifdef SYNC_DET_ON
|
||
268:Core/Src/stm32f4xx_it.c ****
|
||
269:Core/Src/stm32f4xx_it.c ****
|
||
270:Core/Src/stm32f4xx_it.c ****
|
||
271:Core/Src/stm32f4xx_it.c ****
|
||
272:Core/Src/stm32f4xx_it.c **** void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
|
||
273:Core/Src/stm32f4xx_it.c **** {
|
||
399 .loc 1 273 1 is_stmt 1 view -0
|
||
400 .cfi_startproc
|
||
401 @ args = 0, pretend = 0, frame = 0
|
||
402 @ frame_needed = 0, uses_anonymous_args = 0
|
||
403 .loc 1 273 1 is_stmt 0 view .LVU61
|
||
404 0000 08B5 push {r3, lr}
|
||
405 .LCFI5:
|
||
406 .cfi_def_cfa_offset 8
|
||
407 .cfi_offset 3, -8
|
||
408 .cfi_offset 14, -4
|
||
274:Core/Src/stm32f4xx_it.c **** HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_SET);
|
||
409 .loc 1 274 3 is_stmt 1 view .LVU62
|
||
410 0002 0122 movs r2, #1
|
||
411 0004 8021 movs r1, #128
|
||
412 0006 4C48 ldr r0, .L55
|
||
413 .LVL6:
|
||
414 .loc 1 274 3 is_stmt 0 view .LVU63
|
||
415 0008 FFF7FEFF bl HAL_GPIO_WritePin
|
||
416 .LVL7:
|
||
275:Core/Src/stm32f4xx_it.c ****
|
||
276:Core/Src/stm32f4xx_it.c **** if (Sweep_state.curr_step_started_flag == 2) {
|
||
417 .loc 1 276 3 is_stmt 1 view .LVU64
|
||
418 .loc 1 276 18 is_stmt 0 view .LVU65
|
||
419 000c 4B4B ldr r3, .L55+4
|
||
420 000e 1B79 ldrb r3, [r3, #4] @ zero_extendqisi2
|
||
421 0010 DBB2 uxtb r3, r3
|
||
422 .loc 1 276 6 view .LVU66
|
||
423 0012 022B cmp r3, #2
|
||
424 0014 01D0 beq .L51
|
||
425 .LBB2:
|
||
277:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag = 0; // reset flag after processing second half
|
||
278:Core/Src/stm32f4xx_it.c **** for (uint32_t i = ADC_BUFF_SIZE/2; i < Sweep_state.curr_step_start_DMA_N; i++) {
|
||
279:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
ARM GAS /tmp/ccLQihDm.s page 13
|
||
|
||
|
||
280:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
|
||
281:Core/Src/stm32f4xx_it.c **** }else{
|
||
282:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF += ADC1_buff_circular[i];
|
||
283:Core/Src/stm32f4xx_it.c **** }
|
||
284:Core/Src/stm32f4xx_it.c **** }
|
||
285:Core/Src/stm32f4xx_it.c ****
|
||
286:Core/Src/stm32f4xx_it.c **** ADC_proc.N += (Sweep_state.curr_step_start_DMA_N - ADC_BUFF_SIZE/2)/2;
|
||
287:Core/Src/stm32f4xx_it.c ****
|
||
288:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_ON = ADC_proc.sum_ON;
|
||
289:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
|
||
290:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
|
||
291:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
|
||
292:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
|
||
293:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
|
||
294:Core/Src/stm32f4xx_it.c ****
|
||
295:Core/Src/stm32f4xx_it.c ****
|
||
296:Core/Src/stm32f4xx_it.c **** ADC_proc.sum = 0;
|
||
297:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON = 0;
|
||
298:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF = 0;
|
||
299:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0;
|
||
300:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_ON = 0;
|
||
301:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_OFF = 0;
|
||
302:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data
|
||
303:Core/Src/stm32f4xx_it.c ****
|
||
304:Core/Src/stm32f4xx_it.c **** for (uint32_t i = Sweep_state.curr_step_start_DMA_N; i < ADC_BUFF_SIZE; i++) {
|
||
305:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
306:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
|
||
307:Core/Src/stm32f4xx_it.c **** }else{
|
||
308:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF += ADC1_buff_circular[i];
|
||
309:Core/Src/stm32f4xx_it.c **** }
|
||
310:Core/Src/stm32f4xx_it.c **** }
|
||
311:Core/Src/stm32f4xx_it.c **** ADC_proc.N = (ADC_BUFF_SIZE - Sweep_state.curr_step_start_DMA_N)/2;
|
||
312:Core/Src/stm32f4xx_it.c ****
|
||
313:Core/Src/stm32f4xx_it.c ****
|
||
314:Core/Src/stm32f4xx_it.c **** }else{
|
||
315:Core/Src/stm32f4xx_it.c **** for (uint32_t i = ADC_BUFF_SIZE/2; i < ADC_BUFF_SIZE; i++) {
|
||
426 .loc 1 315 19 view .LVU67
|
||
427 0016 1923 movs r3, #25
|
||
428 0018 60E0 b .L35
|
||
429 .L51:
|
||
430 .LBE2:
|
||
277:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag = 0; // reset flag after processing second half
|
||
431 .loc 1 277 5 is_stmt 1 view .LVU68
|
||
277:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag = 0; // reset flag after processing second half
|
||
432 .loc 1 277 40 is_stmt 0 view .LVU69
|
||
433 001a 484B ldr r3, .L55+4
|
||
434 001c 0022 movs r2, #0
|
||
435 001e 1A71 strb r2, [r3, #4]
|
||
278:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
436 .loc 1 278 5 is_stmt 1 view .LVU70
|
||
437 .LBB3:
|
||
278:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
438 .loc 1 278 10 view .LVU71
|
||
439 .LVL8:
|
||
278:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
440 .loc 1 278 19 is_stmt 0 view .LVU72
|
||
441 0020 1923 movs r3, #25
|
||
ARM GAS /tmp/ccLQihDm.s page 14
|
||
|
||
|
||
278:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
442 .loc 1 278 5 view .LVU73
|
||
443 0022 07E0 b .L36
|
||
444 .LVL9:
|
||
445 .L37:
|
||
282:Core/Src/stm32f4xx_it.c **** }
|
||
446 .loc 1 282 9 is_stmt 1 view .LVU74
|
||
282:Core/Src/stm32f4xx_it.c **** }
|
||
447 .loc 1 282 17 is_stmt 0 view .LVU75
|
||
448 0024 4649 ldr r1, .L55+8
|
||
449 0026 CA68 ldr r2, [r1, #12]
|
||
282:Core/Src/stm32f4xx_it.c **** }
|
||
450 .loc 1 282 47 view .LVU76
|
||
451 0028 4648 ldr r0, .L55+12
|
||
452 002a 30F81300 ldrh r0, [r0, r3, lsl #1]
|
||
282:Core/Src/stm32f4xx_it.c **** }
|
||
453 .loc 1 282 26 view .LVU77
|
||
454 002e 0244 add r2, r2, r0
|
||
455 0030 CA60 str r2, [r1, #12]
|
||
456 .L38:
|
||
278:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
457 .loc 1 278 80 is_stmt 1 discriminator 2 view .LVU78
|
||
458 0032 0133 adds r3, r3, #1
|
||
459 .LVL10:
|
||
460 .L36:
|
||
278:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
461 .loc 1 278 42 discriminator 1 view .LVU79
|
||
278:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
462 .loc 1 278 55 is_stmt 0 discriminator 1 view .LVU80
|
||
463 0034 414A ldr r2, .L55+4
|
||
464 0036 9268 ldr r2, [r2, #8]
|
||
278:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
465 .loc 1 278 42 discriminator 1 view .LVU81
|
||
466 0038 9A42 cmp r2, r3
|
||
467 003a 0AD9 bls .L52
|
||
279:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
|
||
468 .loc 1 279 7 is_stmt 1 view .LVU82
|
||
279:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
|
||
469 .loc 1 279 10 is_stmt 0 view .LVU83
|
||
470 003c 13F0010F tst r3, #1
|
||
471 0040 F0D0 beq .L37
|
||
280:Core/Src/stm32f4xx_it.c **** }else{
|
||
472 .loc 1 280 9 is_stmt 1 view .LVU84
|
||
280:Core/Src/stm32f4xx_it.c **** }else{
|
||
473 .loc 1 280 17 is_stmt 0 view .LVU85
|
||
474 0042 3F49 ldr r1, .L55+8
|
||
475 0044 8A68 ldr r2, [r1, #8]
|
||
280:Core/Src/stm32f4xx_it.c **** }else{
|
||
476 .loc 1 280 46 view .LVU86
|
||
477 0046 3F48 ldr r0, .L55+12
|
||
478 0048 30F81300 ldrh r0, [r0, r3, lsl #1]
|
||
280:Core/Src/stm32f4xx_it.c **** }else{
|
||
479 .loc 1 280 25 view .LVU87
|
||
480 004c 0244 add r2, r2, r0
|
||
481 004e 8A60 str r2, [r1, #8]
|
||
482 0050 EFE7 b .L38
|
||
483 .L52:
|
||
ARM GAS /tmp/ccLQihDm.s page 15
|
||
|
||
|
||
484 .LBE3:
|
||
286:Core/Src/stm32f4xx_it.c ****
|
||
485 .loc 1 286 5 is_stmt 1 view .LVU88
|
||
286:Core/Src/stm32f4xx_it.c ****
|
||
486 .loc 1 286 31 is_stmt 0 view .LVU89
|
||
487 0052 3A48 ldr r0, .L55+4
|
||
488 0054 8168 ldr r1, [r0, #8]
|
||
286:Core/Src/stm32f4xx_it.c ****
|
||
489 .loc 1 286 54 view .LVU90
|
||
490 0056 1939 subs r1, r1, #25
|
||
286:Core/Src/stm32f4xx_it.c ****
|
||
491 .loc 1 286 13 view .LVU91
|
||
492 0058 394B ldr r3, .L55+8
|
||
493 .LVL11:
|
||
286:Core/Src/stm32f4xx_it.c ****
|
||
494 .loc 1 286 13 view .LVU92
|
||
495 005a 9A69 ldr r2, [r3, #24]
|
||
286:Core/Src/stm32f4xx_it.c ****
|
||
496 .loc 1 286 16 view .LVU93
|
||
497 005c 02EB5102 add r2, r2, r1, lsr #1
|
||
498 0060 9A61 str r2, [r3, #24]
|
||
288:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
|
||
499 .loc 1 288 5 is_stmt 1 view .LVU94
|
||
288:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
|
||
500 .loc 1 288 38 is_stmt 0 view .LVU95
|
||
501 0062 9968 ldr r1, [r3, #8]
|
||
288:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
|
||
502 .loc 1 288 28 view .LVU96
|
||
503 0064 384A ldr r2, .L55+16
|
||
504 0066 9160 str r1, [r2, #8]
|
||
289:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
|
||
505 .loc 1 289 5 is_stmt 1 view .LVU97
|
||
289:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
|
||
506 .loc 1 289 39 is_stmt 0 view .LVU98
|
||
507 0068 D968 ldr r1, [r3, #12]
|
||
289:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
|
||
508 .loc 1 289 29 view .LVU99
|
||
509 006a D160 str r1, [r2, #12]
|
||
290:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
|
||
510 .loc 1 290 5 is_stmt 1 view .LVU100
|
||
290:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
|
||
511 .loc 1 290 38 is_stmt 0 view .LVU101
|
||
512 006c 1969 ldr r1, [r3, #16]
|
||
290:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
|
||
513 .loc 1 290 28 view .LVU102
|
||
514 006e 1161 str r1, [r2, #16]
|
||
291:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
|
||
515 .loc 1 291 5 is_stmt 1 view .LVU103
|
||
291:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
|
||
516 .loc 1 291 39 is_stmt 0 view .LVU104
|
||
517 0070 5969 ldr r1, [r3, #20]
|
||
291:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
|
||
518 .loc 1 291 29 view .LVU105
|
||
519 0072 5161 str r1, [r2, #20]
|
||
292:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
|
||
520 .loc 1 292 5 is_stmt 1 view .LVU106
|
||
292:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
|
||
ARM GAS /tmp/ccLQihDm.s page 16
|
||
|
||
|
||
521 .loc 1 292 33 is_stmt 0 view .LVU107
|
||
522 0074 9969 ldr r1, [r3, #24]
|
||
292:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
|
||
523 .loc 1 292 23 view .LVU108
|
||
524 0076 9161 str r1, [r2, #24]
|
||
293:Core/Src/stm32f4xx_it.c ****
|
||
525 .loc 1 293 5 is_stmt 1 view .LVU109
|
||
293:Core/Src/stm32f4xx_it.c ****
|
||
526 .loc 1 293 28 is_stmt 0 view .LVU110
|
||
527 0078 0221 movs r1, #2
|
||
528 007a 1170 strb r1, [r2]
|
||
296:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON = 0;
|
||
529 .loc 1 296 5 is_stmt 1 view .LVU111
|
||
296:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON = 0;
|
||
530 .loc 1 296 18 is_stmt 0 view .LVU112
|
||
531 007c 0022 movs r2, #0
|
||
532 007e 5A60 str r2, [r3, #4]
|
||
297:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF = 0;
|
||
533 .loc 1 297 5 is_stmt 1 view .LVU113
|
||
297:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF = 0;
|
||
534 .loc 1 297 21 is_stmt 0 view .LVU114
|
||
535 0080 9A60 str r2, [r3, #8]
|
||
298:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0;
|
||
536 .loc 1 298 5 is_stmt 1 view .LVU115
|
||
298:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0;
|
||
537 .loc 1 298 22 is_stmt 0 view .LVU116
|
||
538 0082 DA60 str r2, [r3, #12]
|
||
299:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_ON = 0;
|
||
539 .loc 1 299 5 is_stmt 1 view .LVU117
|
||
299:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_ON = 0;
|
||
540 .loc 1 299 16 is_stmt 0 view .LVU118
|
||
541 0084 9A61 str r2, [r3, #24]
|
||
300:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_OFF = 0;
|
||
542 .loc 1 300 5 is_stmt 1 view .LVU119
|
||
300:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_OFF = 0;
|
||
543 .loc 1 300 21 is_stmt 0 view .LVU120
|
||
544 0086 1A61 str r2, [r3, #16]
|
||
301:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data
|
||
545 .loc 1 301 5 is_stmt 1 view .LVU121
|
||
301:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data
|
||
546 .loc 1 301 22 is_stmt 0 view .LVU122
|
||
547 0088 5A61 str r2, [r3, #20]
|
||
302:Core/Src/stm32f4xx_it.c ****
|
||
548 .loc 1 302 5 is_stmt 1 view .LVU123
|
||
302:Core/Src/stm32f4xx_it.c ****
|
||
549 .loc 1 302 21 is_stmt 0 view .LVU124
|
||
550 008a 0122 movs r2, #1
|
||
551 008c 1A70 strb r2, [r3]
|
||
304:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
552 .loc 1 304 5 is_stmt 1 view .LVU125
|
||
553 .LBB4:
|
||
304:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
554 .loc 1 304 10 view .LVU126
|
||
304:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
555 .loc 1 304 19 is_stmt 0 view .LVU127
|
||
556 008e 8368 ldr r3, [r0, #8]
|
||
557 .LVL12:
|
||
ARM GAS /tmp/ccLQihDm.s page 17
|
||
|
||
|
||
304:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
558 .loc 1 304 5 view .LVU128
|
||
559 0090 07E0 b .L40
|
||
560 .L41:
|
||
308:Core/Src/stm32f4xx_it.c **** }
|
||
561 .loc 1 308 9 is_stmt 1 view .LVU129
|
||
308:Core/Src/stm32f4xx_it.c **** }
|
||
562 .loc 1 308 17 is_stmt 0 view .LVU130
|
||
563 0092 2B49 ldr r1, .L55+8
|
||
564 0094 CA68 ldr r2, [r1, #12]
|
||
308:Core/Src/stm32f4xx_it.c **** }
|
||
565 .loc 1 308 47 view .LVU131
|
||
566 0096 2B48 ldr r0, .L55+12
|
||
567 0098 30F81300 ldrh r0, [r0, r3, lsl #1]
|
||
308:Core/Src/stm32f4xx_it.c **** }
|
||
568 .loc 1 308 26 view .LVU132
|
||
569 009c 0244 add r2, r2, r0
|
||
570 009e CA60 str r2, [r1, #12]
|
||
571 .L42:
|
||
304:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
572 .loc 1 304 78 is_stmt 1 discriminator 2 view .LVU133
|
||
573 00a0 0133 adds r3, r3, #1
|
||
574 .LVL13:
|
||
575 .L40:
|
||
304:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
576 .loc 1 304 60 discriminator 1 view .LVU134
|
||
577 00a2 312B cmp r3, #49
|
||
578 00a4 0AD8 bhi .L53
|
||
305:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
|
||
579 .loc 1 305 7 view .LVU135
|
||
305:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
|
||
580 .loc 1 305 10 is_stmt 0 view .LVU136
|
||
581 00a6 13F0010F tst r3, #1
|
||
582 00aa F2D0 beq .L41
|
||
306:Core/Src/stm32f4xx_it.c **** }else{
|
||
583 .loc 1 306 9 is_stmt 1 view .LVU137
|
||
306:Core/Src/stm32f4xx_it.c **** }else{
|
||
584 .loc 1 306 17 is_stmt 0 view .LVU138
|
||
585 00ac 2449 ldr r1, .L55+8
|
||
586 00ae 8A68 ldr r2, [r1, #8]
|
||
306:Core/Src/stm32f4xx_it.c **** }else{
|
||
587 .loc 1 306 46 view .LVU139
|
||
588 00b0 2448 ldr r0, .L55+12
|
||
589 00b2 30F81300 ldrh r0, [r0, r3, lsl #1]
|
||
306:Core/Src/stm32f4xx_it.c **** }else{
|
||
590 .loc 1 306 25 view .LVU140
|
||
591 00b6 0244 add r2, r2, r0
|
||
592 00b8 8A60 str r2, [r1, #8]
|
||
593 00ba F1E7 b .L42
|
||
594 .L53:
|
||
595 .LBE4:
|
||
311:Core/Src/stm32f4xx_it.c ****
|
||
596 .loc 1 311 5 is_stmt 1 view .LVU141
|
||
311:Core/Src/stm32f4xx_it.c ****
|
||
597 .loc 1 311 46 is_stmt 0 view .LVU142
|
||
598 00bc 1F4B ldr r3, .L55+4
|
||
599 .LVL14:
|
||
ARM GAS /tmp/ccLQihDm.s page 18
|
||
|
||
|
||
311:Core/Src/stm32f4xx_it.c ****
|
||
600 .loc 1 311 46 view .LVU143
|
||
601 00be 9B68 ldr r3, [r3, #8]
|
||
311:Core/Src/stm32f4xx_it.c ****
|
||
602 .loc 1 311 33 view .LVU144
|
||
603 00c0 C3F13203 rsb r3, r3, #50
|
||
311:Core/Src/stm32f4xx_it.c ****
|
||
604 .loc 1 311 69 view .LVU145
|
||
605 00c4 5B08 lsrs r3, r3, #1
|
||
311:Core/Src/stm32f4xx_it.c ****
|
||
606 .loc 1 311 16 view .LVU146
|
||
607 00c6 1E4A ldr r2, .L55+8
|
||
608 00c8 9361 str r3, [r2, #24]
|
||
609 00ca 18E0 b .L44
|
||
610 .LVL15:
|
||
611 .L45:
|
||
612 .LBB5:
|
||
316:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
317:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
|
||
318:Core/Src/stm32f4xx_it.c **** }else{
|
||
319:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF += ADC1_buff_circular[i];
|
||
613 .loc 1 319 9 is_stmt 1 view .LVU147
|
||
614 .loc 1 319 17 is_stmt 0 view .LVU148
|
||
615 00cc 1C49 ldr r1, .L55+8
|
||
616 00ce CA68 ldr r2, [r1, #12]
|
||
617 .loc 1 319 47 view .LVU149
|
||
618 00d0 1C48 ldr r0, .L55+12
|
||
619 00d2 30F81300 ldrh r0, [r0, r3, lsl #1]
|
||
620 .loc 1 319 26 view .LVU150
|
||
621 00d6 0244 add r2, r2, r0
|
||
622 00d8 CA60 str r2, [r1, #12]
|
||
623 .L46:
|
||
315:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
624 .loc 1 315 60 is_stmt 1 discriminator 2 view .LVU151
|
||
625 00da 0133 adds r3, r3, #1
|
||
626 .LVL16:
|
||
627 .L35:
|
||
315:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
628 .loc 1 315 42 discriminator 1 view .LVU152
|
||
629 00dc 312B cmp r3, #49
|
||
630 00de 0AD8 bhi .L54
|
||
316:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
631 .loc 1 316 7 view .LVU153
|
||
316:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
632 .loc 1 316 10 is_stmt 0 view .LVU154
|
||
633 00e0 13F0010F tst r3, #1
|
||
634 00e4 F2D0 beq .L45
|
||
317:Core/Src/stm32f4xx_it.c **** }else{
|
||
635 .loc 1 317 9 is_stmt 1 view .LVU155
|
||
317:Core/Src/stm32f4xx_it.c **** }else{
|
||
636 .loc 1 317 17 is_stmt 0 view .LVU156
|
||
637 00e6 1649 ldr r1, .L55+8
|
||
638 00e8 8A68 ldr r2, [r1, #8]
|
||
317:Core/Src/stm32f4xx_it.c **** }else{
|
||
639 .loc 1 317 46 view .LVU157
|
||
640 00ea 1648 ldr r0, .L55+12
|
||
641 00ec 30F81300 ldrh r0, [r0, r3, lsl #1]
|
||
ARM GAS /tmp/ccLQihDm.s page 19
|
||
|
||
|
||
317:Core/Src/stm32f4xx_it.c **** }else{
|
||
642 .loc 1 317 25 view .LVU158
|
||
643 00f0 0244 add r2, r2, r0
|
||
644 00f2 8A60 str r2, [r1, #8]
|
||
645 00f4 F1E7 b .L46
|
||
646 .L54:
|
||
647 .LBE5:
|
||
320:Core/Src/stm32f4xx_it.c **** }
|
||
321:Core/Src/stm32f4xx_it.c **** }
|
||
322:Core/Src/stm32f4xx_it.c **** ADC_proc.N += (ADC_BUFF_SIZE - ADC_BUFF_SIZE/2)/2;
|
||
648 .loc 1 322 5 is_stmt 1 view .LVU159
|
||
649 .loc 1 322 13 is_stmt 0 view .LVU160
|
||
650 00f6 124A ldr r2, .L55+8
|
||
651 00f8 9369 ldr r3, [r2, #24]
|
||
652 .LVL17:
|
||
653 .loc 1 322 16 view .LVU161
|
||
654 00fa 0C33 adds r3, r3, #12
|
||
655 00fc 9361 str r3, [r2, #24]
|
||
656 .LVL18:
|
||
657 .L44:
|
||
323:Core/Src/stm32f4xx_it.c **** }
|
||
324:Core/Src/stm32f4xx_it.c ****
|
||
325:Core/Src/stm32f4xx_it.c **** //if (0){
|
||
326:Core/Src/stm32f4xx_it.c **** if (ADC_proc.N >= ADC_BUFF_SIZE*100){
|
||
658 .loc 1 326 3 is_stmt 1 view .LVU162
|
||
659 .loc 1 326 15 is_stmt 0 view .LVU163
|
||
660 00fe 104B ldr r3, .L55+8
|
||
661 0100 9A69 ldr r2, [r3, #24]
|
||
662 .loc 1 326 6 view .LVU164
|
||
663 0102 41F28733 movw r3, #4999
|
||
664 0106 9A42 cmp r2, r3
|
||
665 0108 15D9 bls .L34
|
||
327:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
|
||
666 .loc 1 327 5 is_stmt 1 view .LVU165
|
||
667 .loc 1 327 39 is_stmt 0 view .LVU166
|
||
668 010a 0D4B ldr r3, .L55+8
|
||
669 010c D968 ldr r1, [r3, #12]
|
||
670 .loc 1 327 29 view .LVU167
|
||
671 010e 0E4A ldr r2, .L55+16
|
||
672 0110 D160 str r1, [r2, #12]
|
||
328:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_ON = ADC_proc.sum_ON;
|
||
673 .loc 1 328 5 is_stmt 1 view .LVU168
|
||
674 .loc 1 328 38 is_stmt 0 view .LVU169
|
||
675 0112 9968 ldr r1, [r3, #8]
|
||
676 .loc 1 328 28 view .LVU170
|
||
677 0114 9160 str r1, [r2, #8]
|
||
329:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
|
||
678 .loc 1 329 5 is_stmt 1 view .LVU171
|
||
679 .loc 1 329 38 is_stmt 0 view .LVU172
|
||
680 0116 1969 ldr r1, [r3, #16]
|
||
681 .loc 1 329 28 view .LVU173
|
||
682 0118 1161 str r1, [r2, #16]
|
||
330:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
|
||
683 .loc 1 330 5 is_stmt 1 view .LVU174
|
||
684 .loc 1 330 39 is_stmt 0 view .LVU175
|
||
685 011a 5969 ldr r1, [r3, #20]
|
||
686 .loc 1 330 29 view .LVU176
|
||
ARM GAS /tmp/ccLQihDm.s page 20
|
||
|
||
|
||
687 011c 5161 str r1, [r2, #20]
|
||
331:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
|
||
688 .loc 1 331 5 is_stmt 1 view .LVU177
|
||
689 .loc 1 331 33 is_stmt 0 view .LVU178
|
||
690 011e 9969 ldr r1, [r3, #24]
|
||
691 .loc 1 331 23 view .LVU179
|
||
692 0120 9161 str r1, [r2, #24]
|
||
332:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
|
||
693 .loc 1 332 5 is_stmt 1 view .LVU180
|
||
694 .loc 1 332 28 is_stmt 0 view .LVU181
|
||
695 0122 0221 movs r1, #2
|
||
696 0124 1170 strb r1, [r2]
|
||
333:Core/Src/stm32f4xx_it.c ****
|
||
334:Core/Src/stm32f4xx_it.c ****
|
||
335:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF = 0;
|
||
697 .loc 1 335 5 is_stmt 1 view .LVU182
|
||
698 .loc 1 335 22 is_stmt 0 view .LVU183
|
||
699 0126 0022 movs r2, #0
|
||
700 0128 DA60 str r2, [r3, #12]
|
||
336:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON = 0;
|
||
701 .loc 1 336 5 is_stmt 1 view .LVU184
|
||
702 .loc 1 336 21 is_stmt 0 view .LVU185
|
||
703 012a 9A60 str r2, [r3, #8]
|
||
337:Core/Src/stm32f4xx_it.c ****
|
||
338:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0;
|
||
704 .loc 1 338 5 is_stmt 1 view .LVU186
|
||
705 .loc 1 338 16 is_stmt 0 view .LVU187
|
||
706 012c 9A61 str r2, [r3, #24]
|
||
339:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_ON = 0;
|
||
707 .loc 1 339 5 is_stmt 1 view .LVU188
|
||
708 .loc 1 339 21 is_stmt 0 view .LVU189
|
||
709 012e 1A61 str r2, [r3, #16]
|
||
340:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_OFF = 0;
|
||
710 .loc 1 340 5 is_stmt 1 view .LVU190
|
||
711 .loc 1 340 22 is_stmt 0 view .LVU191
|
||
712 0130 5A61 str r2, [r3, #20]
|
||
341:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data
|
||
713 .loc 1 341 5 is_stmt 1 view .LVU192
|
||
714 .loc 1 341 21 is_stmt 0 view .LVU193
|
||
715 0132 0122 movs r2, #1
|
||
716 0134 1A70 strb r2, [r3]
|
||
717 .L34:
|
||
342:Core/Src/stm32f4xx_it.c **** }
|
||
343:Core/Src/stm32f4xx_it.c **** // This function is called when the first half of the ADC buffer is filled
|
||
344:Core/Src/stm32f4xx_it.c **** // You can process the first half of ADC1_buff_circular here
|
||
345:Core/Src/stm32f4xx_it.c **** }
|
||
718 .loc 1 345 1 view .LVU194
|
||
719 0136 08BD pop {r3, pc}
|
||
720 .L56:
|
||
721 .align 2
|
||
722 .L55:
|
||
723 0138 00040240 .word 1073873920
|
||
724 013c 00000000 .word Sweep_state
|
||
725 0140 00000000 .word ADC_proc
|
||
726 0144 00000000 .word ADC1_buff_circular
|
||
727 0148 00000000 .word ADC_proc_shadow
|
||
728 .cfi_endproc
|
||
ARM GAS /tmp/ccLQihDm.s page 21
|
||
|
||
|
||
729 .LFE252:
|
||
731 .section .text.HAL_ADC_ConvHalfCpltCallback,"ax",%progbits
|
||
732 .align 1
|
||
733 .global HAL_ADC_ConvHalfCpltCallback
|
||
734 .syntax unified
|
||
735 .thumb
|
||
736 .thumb_func
|
||
738 HAL_ADC_ConvHalfCpltCallback:
|
||
739 .LVL19:
|
||
740 .LFB253:
|
||
346:Core/Src/stm32f4xx_it.c ****
|
||
347:Core/Src/stm32f4xx_it.c **** void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
|
||
348:Core/Src/stm32f4xx_it.c **** {
|
||
741 .loc 1 348 1 is_stmt 1 view -0
|
||
742 .cfi_startproc
|
||
743 @ args = 0, pretend = 0, frame = 0
|
||
744 @ frame_needed = 0, uses_anonymous_args = 0
|
||
745 .loc 1 348 1 is_stmt 0 view .LVU196
|
||
746 0000 08B5 push {r3, lr}
|
||
747 .LCFI6:
|
||
748 .cfi_def_cfa_offset 8
|
||
749 .cfi_offset 3, -8
|
||
750 .cfi_offset 14, -4
|
||
349:Core/Src/stm32f4xx_it.c **** //HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_RESET);
|
||
350:Core/Src/stm32f4xx_it.c ****
|
||
351:Core/Src/stm32f4xx_it.c **** HAL_GPIO_TogglePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin);
|
||
751 .loc 1 351 3 is_stmt 1 view .LVU197
|
||
752 0002 8021 movs r1, #128
|
||
753 0004 3C48 ldr r0, .L77
|
||
754 .LVL20:
|
||
755 .loc 1 351 3 is_stmt 0 view .LVU198
|
||
756 0006 FFF7FEFF bl HAL_GPIO_TogglePin
|
||
757 .LVL21:
|
||
352:Core/Src/stm32f4xx_it.c **** if (Sweep_state.curr_step_started_flag == 1) {
|
||
758 .loc 1 352 3 is_stmt 1 view .LVU199
|
||
759 .loc 1 352 18 is_stmt 0 view .LVU200
|
||
760 000a 3C4B ldr r3, .L77+4
|
||
761 000c 1B79 ldrb r3, [r3, #4] @ zero_extendqisi2
|
||
762 000e DBB2 uxtb r3, r3
|
||
763 .loc 1 352 6 view .LVU201
|
||
764 0010 012B cmp r3, #1
|
||
765 0012 01D0 beq .L73
|
||
766 .LBB6:
|
||
353:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag = 0;
|
||
354:Core/Src/stm32f4xx_it.c **** for (uint32_t i = 0; i < Sweep_state.curr_step_start_DMA_N; i++) {
|
||
355:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
356:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
|
||
357:Core/Src/stm32f4xx_it.c **** }else{
|
||
358:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF += ADC1_buff_circular[i];
|
||
359:Core/Src/stm32f4xx_it.c **** }
|
||
360:Core/Src/stm32f4xx_it.c **** }
|
||
361:Core/Src/stm32f4xx_it.c ****
|
||
362:Core/Src/stm32f4xx_it.c **** ADC_proc.N += (Sweep_state.curr_step_start_DMA_N)/2;
|
||
363:Core/Src/stm32f4xx_it.c ****
|
||
364:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_ON = ADC_proc.sum_ON;
|
||
365:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
|
||
366:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
|
||
ARM GAS /tmp/ccLQihDm.s page 22
|
||
|
||
|
||
367:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
|
||
368:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
|
||
369:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
|
||
370:Core/Src/stm32f4xx_it.c ****
|
||
371:Core/Src/stm32f4xx_it.c ****
|
||
372:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON = 0;
|
||
373:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF = 0;
|
||
374:Core/Src/stm32f4xx_it.c **** ADC_proc.sum = 0;
|
||
375:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0;
|
||
376:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_OFF = 0;
|
||
377:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_ON = 0;
|
||
378:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data
|
||
379:Core/Src/stm32f4xx_it.c ****
|
||
380:Core/Src/stm32f4xx_it.c **** for (uint32_t i = Sweep_state.curr_step_start_DMA_N; i < ADC_BUFF_SIZE/2; i++) {
|
||
381:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
382:Core/Src/stm32f4xx_it.c ****
|
||
383:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
|
||
384:Core/Src/stm32f4xx_it.c **** }else{
|
||
385:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF += ADC1_buff_circular[i];
|
||
386:Core/Src/stm32f4xx_it.c **** }
|
||
387:Core/Src/stm32f4xx_it.c **** }
|
||
388:Core/Src/stm32f4xx_it.c **** ADC_proc.N = (Sweep_state.curr_step_start_DMA_N)/2;
|
||
389:Core/Src/stm32f4xx_it.c ****
|
||
390:Core/Src/stm32f4xx_it.c **** }else{
|
||
391:Core/Src/stm32f4xx_it.c **** for (uint32_t i = 0; i < ADC_BUFF_SIZE/2; i++) {
|
||
767 .loc 1 391 19 view .LVU202
|
||
768 0014 0023 movs r3, #0
|
||
769 0016 5CE0 b .L58
|
||
770 .L73:
|
||
771 .LBE6:
|
||
353:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag = 0;
|
||
772 .loc 1 353 5 is_stmt 1 view .LVU203
|
||
353:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag = 0;
|
||
773 .loc 1 353 40 is_stmt 0 view .LVU204
|
||
774 0018 0023 movs r3, #0
|
||
775 001a 384A ldr r2, .L77+4
|
||
776 001c 1371 strb r3, [r2, #4]
|
||
354:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
777 .loc 1 354 5 is_stmt 1 view .LVU205
|
||
778 .LBB7:
|
||
354:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
779 .loc 1 354 10 view .LVU206
|
||
780 .LVL22:
|
||
354:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
781 .loc 1 354 5 is_stmt 0 view .LVU207
|
||
782 001e 07E0 b .L59
|
||
783 .LVL23:
|
||
784 .L60:
|
||
358:Core/Src/stm32f4xx_it.c **** }
|
||
785 .loc 1 358 9 is_stmt 1 view .LVU208
|
||
358:Core/Src/stm32f4xx_it.c **** }
|
||
786 .loc 1 358 17 is_stmt 0 view .LVU209
|
||
787 0020 3749 ldr r1, .L77+8
|
||
788 0022 CA68 ldr r2, [r1, #12]
|
||
358:Core/Src/stm32f4xx_it.c **** }
|
||
789 .loc 1 358 47 view .LVU210
|
||
790 0024 3748 ldr r0, .L77+12
|
||
ARM GAS /tmp/ccLQihDm.s page 23
|
||
|
||
|
||
791 0026 30F81300 ldrh r0, [r0, r3, lsl #1]
|
||
358:Core/Src/stm32f4xx_it.c **** }
|
||
792 .loc 1 358 26 view .LVU211
|
||
793 002a 0244 add r2, r2, r0
|
||
794 002c CA60 str r2, [r1, #12]
|
||
795 .L61:
|
||
354:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
796 .loc 1 354 66 is_stmt 1 discriminator 2 view .LVU212
|
||
797 002e 0133 adds r3, r3, #1
|
||
798 .LVL24:
|
||
799 .L59:
|
||
354:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
800 .loc 1 354 28 discriminator 1 view .LVU213
|
||
354:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
801 .loc 1 354 41 is_stmt 0 discriminator 1 view .LVU214
|
||
802 0030 324A ldr r2, .L77+4
|
||
803 0032 9268 ldr r2, [r2, #8]
|
||
354:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
804 .loc 1 354 28 discriminator 1 view .LVU215
|
||
805 0034 9A42 cmp r2, r3
|
||
806 0036 0AD9 bls .L74
|
||
355:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
|
||
807 .loc 1 355 7 is_stmt 1 view .LVU216
|
||
355:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
|
||
808 .loc 1 355 10 is_stmt 0 view .LVU217
|
||
809 0038 13F0010F tst r3, #1
|
||
810 003c F0D0 beq .L60
|
||
356:Core/Src/stm32f4xx_it.c **** }else{
|
||
811 .loc 1 356 9 is_stmt 1 view .LVU218
|
||
356:Core/Src/stm32f4xx_it.c **** }else{
|
||
812 .loc 1 356 17 is_stmt 0 view .LVU219
|
||
813 003e 3049 ldr r1, .L77+8
|
||
814 0040 8A68 ldr r2, [r1, #8]
|
||
356:Core/Src/stm32f4xx_it.c **** }else{
|
||
815 .loc 1 356 46 view .LVU220
|
||
816 0042 3048 ldr r0, .L77+12
|
||
817 0044 30F81300 ldrh r0, [r0, r3, lsl #1]
|
||
356:Core/Src/stm32f4xx_it.c **** }else{
|
||
818 .loc 1 356 25 view .LVU221
|
||
819 0048 0244 add r2, r2, r0
|
||
820 004a 8A60 str r2, [r1, #8]
|
||
821 004c EFE7 b .L61
|
||
822 .L74:
|
||
823 .LBE7:
|
||
362:Core/Src/stm32f4xx_it.c ****
|
||
824 .loc 1 362 5 is_stmt 1 view .LVU222
|
||
362:Core/Src/stm32f4xx_it.c ****
|
||
825 .loc 1 362 31 is_stmt 0 view .LVU223
|
||
826 004e 2B49 ldr r1, .L77+4
|
||
827 0050 8868 ldr r0, [r1, #8]
|
||
362:Core/Src/stm32f4xx_it.c ****
|
||
828 .loc 1 362 13 view .LVU224
|
||
829 0052 2B4B ldr r3, .L77+8
|
||
830 .LVL25:
|
||
362:Core/Src/stm32f4xx_it.c ****
|
||
831 .loc 1 362 13 view .LVU225
|
||
832 0054 9A69 ldr r2, [r3, #24]
|
||
ARM GAS /tmp/ccLQihDm.s page 24
|
||
|
||
|
||
362:Core/Src/stm32f4xx_it.c ****
|
||
833 .loc 1 362 16 view .LVU226
|
||
834 0056 02EB5002 add r2, r2, r0, lsr #1
|
||
835 005a 9A61 str r2, [r3, #24]
|
||
364:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
|
||
836 .loc 1 364 5 is_stmt 1 view .LVU227
|
||
364:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
|
||
837 .loc 1 364 38 is_stmt 0 view .LVU228
|
||
838 005c 9868 ldr r0, [r3, #8]
|
||
364:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
|
||
839 .loc 1 364 28 view .LVU229
|
||
840 005e 2A4A ldr r2, .L77+16
|
||
841 0060 9060 str r0, [r2, #8]
|
||
365:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
|
||
842 .loc 1 365 5 is_stmt 1 view .LVU230
|
||
365:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
|
||
843 .loc 1 365 38 is_stmt 0 view .LVU231
|
||
844 0062 1869 ldr r0, [r3, #16]
|
||
365:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
|
||
845 .loc 1 365 28 view .LVU232
|
||
846 0064 1061 str r0, [r2, #16]
|
||
366:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
|
||
847 .loc 1 366 5 is_stmt 1 view .LVU233
|
||
366:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
|
||
848 .loc 1 366 39 is_stmt 0 view .LVU234
|
||
849 0066 D868 ldr r0, [r3, #12]
|
||
366:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
|
||
850 .loc 1 366 29 view .LVU235
|
||
851 0068 D060 str r0, [r2, #12]
|
||
367:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
|
||
852 .loc 1 367 5 is_stmt 1 view .LVU236
|
||
367:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
|
||
853 .loc 1 367 39 is_stmt 0 view .LVU237
|
||
854 006a 5869 ldr r0, [r3, #20]
|
||
367:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
|
||
855 .loc 1 367 29 view .LVU238
|
||
856 006c 5061 str r0, [r2, #20]
|
||
368:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
|
||
857 .loc 1 368 5 is_stmt 1 view .LVU239
|
||
368:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
|
||
858 .loc 1 368 33 is_stmt 0 view .LVU240
|
||
859 006e 9869 ldr r0, [r3, #24]
|
||
368:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
|
||
860 .loc 1 368 23 view .LVU241
|
||
861 0070 9061 str r0, [r2, #24]
|
||
369:Core/Src/stm32f4xx_it.c ****
|
||
862 .loc 1 369 5 is_stmt 1 view .LVU242
|
||
369:Core/Src/stm32f4xx_it.c ****
|
||
863 .loc 1 369 28 is_stmt 0 view .LVU243
|
||
864 0072 0220 movs r0, #2
|
||
865 0074 1070 strb r0, [r2]
|
||
372:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF = 0;
|
||
866 .loc 1 372 5 is_stmt 1 view .LVU244
|
||
372:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF = 0;
|
||
867 .loc 1 372 21 is_stmt 0 view .LVU245
|
||
868 0076 0022 movs r2, #0
|
||
869 0078 9A60 str r2, [r3, #8]
|
||
ARM GAS /tmp/ccLQihDm.s page 25
|
||
|
||
|
||
373:Core/Src/stm32f4xx_it.c **** ADC_proc.sum = 0;
|
||
870 .loc 1 373 5 is_stmt 1 view .LVU246
|
||
373:Core/Src/stm32f4xx_it.c **** ADC_proc.sum = 0;
|
||
871 .loc 1 373 22 is_stmt 0 view .LVU247
|
||
872 007a DA60 str r2, [r3, #12]
|
||
374:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0;
|
||
873 .loc 1 374 5 is_stmt 1 view .LVU248
|
||
374:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0;
|
||
874 .loc 1 374 18 is_stmt 0 view .LVU249
|
||
875 007c 5A60 str r2, [r3, #4]
|
||
375:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_OFF = 0;
|
||
876 .loc 1 375 5 is_stmt 1 view .LVU250
|
||
375:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_OFF = 0;
|
||
877 .loc 1 375 16 is_stmt 0 view .LVU251
|
||
878 007e 9A61 str r2, [r3, #24]
|
||
376:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_ON = 0;
|
||
879 .loc 1 376 5 is_stmt 1 view .LVU252
|
||
376:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_ON = 0;
|
||
880 .loc 1 376 22 is_stmt 0 view .LVU253
|
||
881 0080 5A61 str r2, [r3, #20]
|
||
377:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data
|
||
882 .loc 1 377 5 is_stmt 1 view .LVU254
|
||
377:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data
|
||
883 .loc 1 377 21 is_stmt 0 view .LVU255
|
||
884 0082 1A61 str r2, [r3, #16]
|
||
378:Core/Src/stm32f4xx_it.c ****
|
||
885 .loc 1 378 5 is_stmt 1 view .LVU256
|
||
378:Core/Src/stm32f4xx_it.c ****
|
||
886 .loc 1 378 21 is_stmt 0 view .LVU257
|
||
887 0084 0122 movs r2, #1
|
||
888 0086 1A70 strb r2, [r3]
|
||
380:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
889 .loc 1 380 5 is_stmt 1 view .LVU258
|
||
890 .LBB8:
|
||
380:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
891 .loc 1 380 10 view .LVU259
|
||
380:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
892 .loc 1 380 19 is_stmt 0 view .LVU260
|
||
893 0088 8B68 ldr r3, [r1, #8]
|
||
894 .LVL26:
|
||
380:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
895 .loc 1 380 5 view .LVU261
|
||
896 008a 07E0 b .L63
|
||
897 .L64:
|
||
385:Core/Src/stm32f4xx_it.c **** }
|
||
898 .loc 1 385 9 is_stmt 1 view .LVU262
|
||
385:Core/Src/stm32f4xx_it.c **** }
|
||
899 .loc 1 385 17 is_stmt 0 view .LVU263
|
||
900 008c 1C49 ldr r1, .L77+8
|
||
901 008e CA68 ldr r2, [r1, #12]
|
||
385:Core/Src/stm32f4xx_it.c **** }
|
||
902 .loc 1 385 47 view .LVU264
|
||
903 0090 1C48 ldr r0, .L77+12
|
||
904 0092 30F81300 ldrh r0, [r0, r3, lsl #1]
|
||
385:Core/Src/stm32f4xx_it.c **** }
|
||
905 .loc 1 385 26 view .LVU265
|
||
906 0096 0244 add r2, r2, r0
|
||
ARM GAS /tmp/ccLQihDm.s page 26
|
||
|
||
|
||
907 0098 CA60 str r2, [r1, #12]
|
||
908 .L65:
|
||
380:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
909 .loc 1 380 80 is_stmt 1 discriminator 2 view .LVU266
|
||
910 009a 0133 adds r3, r3, #1
|
||
911 .LVL27:
|
||
912 .L63:
|
||
380:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
913 .loc 1 380 60 discriminator 1 view .LVU267
|
||
914 009c 182B cmp r3, #24
|
||
915 009e 0AD8 bhi .L75
|
||
381:Core/Src/stm32f4xx_it.c ****
|
||
916 .loc 1 381 7 view .LVU268
|
||
381:Core/Src/stm32f4xx_it.c ****
|
||
917 .loc 1 381 10 is_stmt 0 view .LVU269
|
||
918 00a0 13F0010F tst r3, #1
|
||
919 00a4 F2D0 beq .L64
|
||
383:Core/Src/stm32f4xx_it.c **** }else{
|
||
920 .loc 1 383 9 is_stmt 1 view .LVU270
|
||
383:Core/Src/stm32f4xx_it.c **** }else{
|
||
921 .loc 1 383 17 is_stmt 0 view .LVU271
|
||
922 00a6 1649 ldr r1, .L77+8
|
||
923 00a8 8A68 ldr r2, [r1, #8]
|
||
383:Core/Src/stm32f4xx_it.c **** }else{
|
||
924 .loc 1 383 46 view .LVU272
|
||
925 00aa 1648 ldr r0, .L77+12
|
||
926 00ac 30F81300 ldrh r0, [r0, r3, lsl #1]
|
||
383:Core/Src/stm32f4xx_it.c **** }else{
|
||
927 .loc 1 383 25 view .LVU273
|
||
928 00b0 0244 add r2, r2, r0
|
||
929 00b2 8A60 str r2, [r1, #8]
|
||
930 00b4 F1E7 b .L65
|
||
931 .L75:
|
||
932 .LBE8:
|
||
388:Core/Src/stm32f4xx_it.c ****
|
||
933 .loc 1 388 5 is_stmt 1 view .LVU274
|
||
388:Core/Src/stm32f4xx_it.c ****
|
||
934 .loc 1 388 30 is_stmt 0 view .LVU275
|
||
935 00b6 114B ldr r3, .L77+4
|
||
936 .LVL28:
|
||
388:Core/Src/stm32f4xx_it.c ****
|
||
937 .loc 1 388 30 view .LVU276
|
||
938 00b8 9B68 ldr r3, [r3, #8]
|
||
388:Core/Src/stm32f4xx_it.c ****
|
||
939 .loc 1 388 53 view .LVU277
|
||
940 00ba 5B08 lsrs r3, r3, #1
|
||
388:Core/Src/stm32f4xx_it.c ****
|
||
941 .loc 1 388 16 view .LVU278
|
||
942 00bc 104A ldr r2, .L77+8
|
||
943 00be 9361 str r3, [r2, #24]
|
||
944 00c0 18E0 b .L57
|
||
945 .LVL29:
|
||
946 .L68:
|
||
947 .LBB9:
|
||
392:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
393:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON += ADC1_buff_circular[i];
|
||
394:Core/Src/stm32f4xx_it.c **** }else{
|
||
ARM GAS /tmp/ccLQihDm.s page 27
|
||
|
||
|
||
395:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF += ADC1_buff_circular[i];
|
||
948 .loc 1 395 9 is_stmt 1 view .LVU279
|
||
949 .loc 1 395 17 is_stmt 0 view .LVU280
|
||
950 00c2 0F49 ldr r1, .L77+8
|
||
951 00c4 CA68 ldr r2, [r1, #12]
|
||
952 .loc 1 395 47 view .LVU281
|
||
953 00c6 0F48 ldr r0, .L77+12
|
||
954 00c8 30F81300 ldrh r0, [r0, r3, lsl #1]
|
||
955 .loc 1 395 26 view .LVU282
|
||
956 00cc 0244 add r2, r2, r0
|
||
957 00ce CA60 str r2, [r1, #12]
|
||
958 .L69:
|
||
391:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
959 .loc 1 391 48 is_stmt 1 discriminator 2 view .LVU283
|
||
960 00d0 0133 adds r3, r3, #1
|
||
961 .LVL30:
|
||
962 .L58:
|
||
391:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
963 .loc 1 391 28 discriminator 1 view .LVU284
|
||
964 00d2 182B cmp r3, #24
|
||
965 00d4 0AD8 bhi .L76
|
||
392:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
966 .loc 1 392 7 view .LVU285
|
||
392:Core/Src/stm32f4xx_it.c **** if ((i & 1) != 0){
|
||
967 .loc 1 392 10 is_stmt 0 view .LVU286
|
||
968 00d6 13F0010F tst r3, #1
|
||
969 00da F2D0 beq .L68
|
||
393:Core/Src/stm32f4xx_it.c **** }else{
|
||
970 .loc 1 393 9 is_stmt 1 view .LVU287
|
||
393:Core/Src/stm32f4xx_it.c **** }else{
|
||
971 .loc 1 393 17 is_stmt 0 view .LVU288
|
||
972 00dc 0849 ldr r1, .L77+8
|
||
973 00de 8A68 ldr r2, [r1, #8]
|
||
393:Core/Src/stm32f4xx_it.c **** }else{
|
||
974 .loc 1 393 46 view .LVU289
|
||
975 00e0 0848 ldr r0, .L77+12
|
||
976 00e2 30F81300 ldrh r0, [r0, r3, lsl #1]
|
||
393:Core/Src/stm32f4xx_it.c **** }else{
|
||
977 .loc 1 393 25 view .LVU290
|
||
978 00e6 0244 add r2, r2, r0
|
||
979 00e8 8A60 str r2, [r1, #8]
|
||
980 00ea F1E7 b .L69
|
||
981 .L76:
|
||
982 .LBE9:
|
||
396:Core/Src/stm32f4xx_it.c **** }
|
||
397:Core/Src/stm32f4xx_it.c **** }
|
||
398:Core/Src/stm32f4xx_it.c **** ADC_proc.N += (ADC_BUFF_SIZE/2)/2;
|
||
983 .loc 1 398 5 is_stmt 1 view .LVU291
|
||
984 .loc 1 398 13 is_stmt 0 view .LVU292
|
||
985 00ec 044A ldr r2, .L77+8
|
||
986 00ee 9369 ldr r3, [r2, #24]
|
||
987 .LVL31:
|
||
988 .loc 1 398 16 view .LVU293
|
||
989 00f0 0C33 adds r3, r3, #12
|
||
990 00f2 9361 str r3, [r2, #24]
|
||
991 .LVL32:
|
||
992 .L57:
|
||
ARM GAS /tmp/ccLQihDm.s page 28
|
||
|
||
|
||
399:Core/Src/stm32f4xx_it.c **** }
|
||
400:Core/Src/stm32f4xx_it.c **** // This function is called when the first half of the ADC buffer is filled
|
||
401:Core/Src/stm32f4xx_it.c **** // You can process the first half of ADC1_buff_circular here
|
||
402:Core/Src/stm32f4xx_it.c **** }
|
||
993 .loc 1 402 1 view .LVU294
|
||
994 00f4 08BD pop {r3, pc}
|
||
995 .L78:
|
||
996 00f6 00BF .align 2
|
||
997 .L77:
|
||
998 00f8 00040240 .word 1073873920
|
||
999 00fc 00000000 .word Sweep_state
|
||
1000 0100 00000000 .word ADC_proc
|
||
1001 0104 00000000 .word ADC1_buff_circular
|
||
1002 0108 00000000 .word ADC_proc_shadow
|
||
1003 .cfi_endproc
|
||
1004 .LFE253:
|
||
1006 .text
|
||
1007 .Letext0:
|
||
1008 .file 2 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h"
|
||
1009 .file 3 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h"
|
||
1010 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
|
||
1011 .file 5 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h"
|
||
1012 .file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h"
|
||
1013 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h"
|
||
1014 .file 8 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h"
|
||
1015 .file 9 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h"
|
||
1016 .file 10 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h"
|
||
1017 .file 11 "Core/Inc/main.h"
|
||
1018 .file 12 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h"
|
||
ARM GAS /tmp/ccLQihDm.s page 29
|
||
|
||
|
||
DEFINED SYMBOLS
|
||
*ABS*:00000000 stm32f4xx_it.c
|
||
/tmp/ccLQihDm.s:21 .text.NMI_Handler:00000000 $t
|
||
/tmp/ccLQihDm.s:27 .text.NMI_Handler:00000000 NMI_Handler
|
||
/tmp/ccLQihDm.s:44 .text.HardFault_Handler:00000000 $t
|
||
/tmp/ccLQihDm.s:50 .text.HardFault_Handler:00000000 HardFault_Handler
|
||
/tmp/ccLQihDm.s:67 .text.MemManage_Handler:00000000 $t
|
||
/tmp/ccLQihDm.s:73 .text.MemManage_Handler:00000000 MemManage_Handler
|
||
/tmp/ccLQihDm.s:90 .text.BusFault_Handler:00000000 $t
|
||
/tmp/ccLQihDm.s:96 .text.BusFault_Handler:00000000 BusFault_Handler
|
||
/tmp/ccLQihDm.s:113 .text.UsageFault_Handler:00000000 $t
|
||
/tmp/ccLQihDm.s:119 .text.UsageFault_Handler:00000000 UsageFault_Handler
|
||
/tmp/ccLQihDm.s:136 .text.SVC_Handler:00000000 $t
|
||
/tmp/ccLQihDm.s:142 .text.SVC_Handler:00000000 SVC_Handler
|
||
/tmp/ccLQihDm.s:155 .text.DebugMon_Handler:00000000 $t
|
||
/tmp/ccLQihDm.s:161 .text.DebugMon_Handler:00000000 DebugMon_Handler
|
||
/tmp/ccLQihDm.s:174 .text.PendSV_Handler:00000000 $t
|
||
/tmp/ccLQihDm.s:180 .text.PendSV_Handler:00000000 PendSV_Handler
|
||
/tmp/ccLQihDm.s:193 .text.SysTick_Handler:00000000 $t
|
||
/tmp/ccLQihDm.s:199 .text.SysTick_Handler:00000000 SysTick_Handler
|
||
/tmp/ccLQihDm.s:219 .text.EXTI0_IRQHandler:00000000 $t
|
||
/tmp/ccLQihDm.s:225 .text.EXTI0_IRQHandler:00000000 EXTI0_IRQHandler
|
||
/tmp/ccLQihDm.s:282 .text.EXTI0_IRQHandler:00000034 $d
|
||
/tmp/ccLQihDm.s:288 .text.EXTI3_IRQHandler:00000000 $t
|
||
/tmp/ccLQihDm.s:294 .text.EXTI3_IRQHandler:00000000 EXTI3_IRQHandler
|
||
/tmp/ccLQihDm.s:323 .text.EXTI3_IRQHandler:00000014 $d
|
||
/tmp/ccLQihDm.s:328 .text.DMA2_Stream0_IRQHandler:00000000 $t
|
||
/tmp/ccLQihDm.s:334 .text.DMA2_Stream0_IRQHandler:00000000 DMA2_Stream0_IRQHandler
|
||
/tmp/ccLQihDm.s:354 .text.DMA2_Stream0_IRQHandler:0000000c $d
|
||
/tmp/ccLQihDm.s:359 .text.OTG_FS_IRQHandler:00000000 $t
|
||
/tmp/ccLQihDm.s:365 .text.OTG_FS_IRQHandler:00000000 OTG_FS_IRQHandler
|
||
/tmp/ccLQihDm.s:385 .text.OTG_FS_IRQHandler:0000000c $d
|
||
/tmp/ccLQihDm.s:390 .text.HAL_ADC_ConvCpltCallback:00000000 $t
|
||
/tmp/ccLQihDm.s:396 .text.HAL_ADC_ConvCpltCallback:00000000 HAL_ADC_ConvCpltCallback
|
||
/tmp/ccLQihDm.s:723 .text.HAL_ADC_ConvCpltCallback:00000138 $d
|
||
/tmp/ccLQihDm.s:732 .text.HAL_ADC_ConvHalfCpltCallback:00000000 $t
|
||
/tmp/ccLQihDm.s:738 .text.HAL_ADC_ConvHalfCpltCallback:00000000 HAL_ADC_ConvHalfCpltCallback
|
||
/tmp/ccLQihDm.s:998 .text.HAL_ADC_ConvHalfCpltCallback:000000f8 $d
|
||
|
||
UNDEFINED SYMBOLS
|
||
HAL_IncTick
|
||
HAL_GPIO_EXTI_IRQHandler
|
||
hdma_adc1
|
||
Sweep_state
|
||
HAL_DMA_IRQHandler
|
||
HAL_PCD_IRQHandler
|
||
hpcd_USB_OTG_FS
|
||
HAL_GPIO_WritePin
|
||
ADC_proc
|
||
ADC1_buff_circular
|
||
ADC_proc_shadow
|
||
HAL_GPIO_TogglePin
|