580 lines
27 KiB
Plaintext
580 lines
27 KiB
Plaintext
ARM GAS /tmp/ccZXUiNz.s page 1
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1 .cpu cortex-m4
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2 .arch armv7e-m
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3 .fpu fpv4-sp-d16
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4 .eabi_attribute 27, 1
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5 .eabi_attribute 28, 1
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6 .eabi_attribute 20, 1
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7 .eabi_attribute 21, 1
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8 .eabi_attribute 23, 3
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9 .eabi_attribute 24, 1
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10 .eabi_attribute 25, 1
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11 .eabi_attribute 26, 1
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12 .eabi_attribute 30, 1
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13 .eabi_attribute 34, 1
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14 .eabi_attribute 18, 4
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15 .file "stm32f4xx_hal_msp.c"
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16 .text
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17 .Ltext0:
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18 .cfi_sections .debug_frame
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19 .file 1 "Core/Src/stm32f4xx_hal_msp.c"
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20 .section .text.HAL_MspInit,"ax",%progbits
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21 .align 1
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22 .global HAL_MspInit
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23 .syntax unified
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24 .thumb
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25 .thumb_func
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27 HAL_MspInit:
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28 .LFB239:
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1:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN Header */
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2:Core/Src/stm32f4xx_hal_msp.c **** /**
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3:Core/Src/stm32f4xx_hal_msp.c **** ******************************************************************************
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4:Core/Src/stm32f4xx_hal_msp.c **** * @file stm32f4xx_hal_msp.c
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5:Core/Src/stm32f4xx_hal_msp.c **** * @brief This file provides code for the MSP Initialization
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6:Core/Src/stm32f4xx_hal_msp.c **** * and de-Initialization codes.
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7:Core/Src/stm32f4xx_hal_msp.c **** ******************************************************************************
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8:Core/Src/stm32f4xx_hal_msp.c **** * @attention
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9:Core/Src/stm32f4xx_hal_msp.c **** *
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10:Core/Src/stm32f4xx_hal_msp.c **** * Copyright (c) 2025 STMicroelectronics.
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11:Core/Src/stm32f4xx_hal_msp.c **** * All rights reserved.
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12:Core/Src/stm32f4xx_hal_msp.c **** *
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13:Core/Src/stm32f4xx_hal_msp.c **** * This software is licensed under terms that can be found in the LICENSE file
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14:Core/Src/stm32f4xx_hal_msp.c **** * in the root directory of this software component.
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15:Core/Src/stm32f4xx_hal_msp.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
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16:Core/Src/stm32f4xx_hal_msp.c **** *
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17:Core/Src/stm32f4xx_hal_msp.c **** ******************************************************************************
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18:Core/Src/stm32f4xx_hal_msp.c **** */
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19:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END Header */
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20:Core/Src/stm32f4xx_hal_msp.c ****
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21:Core/Src/stm32f4xx_hal_msp.c **** /* Includes ------------------------------------------------------------------*/
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22:Core/Src/stm32f4xx_hal_msp.c **** #include "main.h"
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23:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN Includes */
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24:Core/Src/stm32f4xx_hal_msp.c ****
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25:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END Includes */
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26:Core/Src/stm32f4xx_hal_msp.c **** extern DMA_HandleTypeDef hdma_adc1;
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27:Core/Src/stm32f4xx_hal_msp.c ****
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28:Core/Src/stm32f4xx_hal_msp.c **** /* Private typedef -----------------------------------------------------------*/
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29:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN TD */
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30:Core/Src/stm32f4xx_hal_msp.c ****
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ARM GAS /tmp/ccZXUiNz.s page 2
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31:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END TD */
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32:Core/Src/stm32f4xx_hal_msp.c ****
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33:Core/Src/stm32f4xx_hal_msp.c **** /* Private define ------------------------------------------------------------*/
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34:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN Define */
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35:Core/Src/stm32f4xx_hal_msp.c ****
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36:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END Define */
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37:Core/Src/stm32f4xx_hal_msp.c ****
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38:Core/Src/stm32f4xx_hal_msp.c **** /* Private macro -------------------------------------------------------------*/
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39:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN Macro */
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40:Core/Src/stm32f4xx_hal_msp.c ****
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41:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END Macro */
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42:Core/Src/stm32f4xx_hal_msp.c ****
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43:Core/Src/stm32f4xx_hal_msp.c **** /* Private variables ---------------------------------------------------------*/
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44:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN PV */
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45:Core/Src/stm32f4xx_hal_msp.c ****
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46:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END PV */
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47:Core/Src/stm32f4xx_hal_msp.c ****
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48:Core/Src/stm32f4xx_hal_msp.c **** /* Private function prototypes -----------------------------------------------*/
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49:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN PFP */
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50:Core/Src/stm32f4xx_hal_msp.c ****
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51:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END PFP */
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52:Core/Src/stm32f4xx_hal_msp.c ****
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53:Core/Src/stm32f4xx_hal_msp.c **** /* External functions --------------------------------------------------------*/
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54:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN ExternalFunctions */
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55:Core/Src/stm32f4xx_hal_msp.c ****
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56:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END ExternalFunctions */
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57:Core/Src/stm32f4xx_hal_msp.c ****
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58:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN 0 */
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59:Core/Src/stm32f4xx_hal_msp.c ****
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60:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END 0 */
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61:Core/Src/stm32f4xx_hal_msp.c **** /**
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62:Core/Src/stm32f4xx_hal_msp.c **** * Initializes the Global MSP.
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63:Core/Src/stm32f4xx_hal_msp.c **** */
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64:Core/Src/stm32f4xx_hal_msp.c **** void HAL_MspInit(void)
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65:Core/Src/stm32f4xx_hal_msp.c **** {
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29 .loc 1 65 1 view -0
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30 .cfi_startproc
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31 @ args = 0, pretend = 0, frame = 8
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32 @ frame_needed = 0, uses_anonymous_args = 0
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33 @ link register save eliminated.
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34 0000 82B0 sub sp, sp, #8
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35 .LCFI0:
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36 .cfi_def_cfa_offset 8
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66:Core/Src/stm32f4xx_hal_msp.c ****
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67:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN MspInit 0 */
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68:Core/Src/stm32f4xx_hal_msp.c ****
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69:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END MspInit 0 */
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70:Core/Src/stm32f4xx_hal_msp.c ****
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71:Core/Src/stm32f4xx_hal_msp.c **** __HAL_RCC_SYSCFG_CLK_ENABLE();
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37 .loc 1 71 3 view .LVU1
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38 .LBB2:
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39 .loc 1 71 3 view .LVU2
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40 0002 0021 movs r1, #0
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41 0004 0091 str r1, [sp]
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42 .loc 1 71 3 view .LVU3
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43 0006 0B4B ldr r3, .L3
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44 0008 5A6C ldr r2, [r3, #68]
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ARM GAS /tmp/ccZXUiNz.s page 3
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45 000a 42F48042 orr r2, r2, #16384
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46 000e 5A64 str r2, [r3, #68]
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47 .loc 1 71 3 view .LVU4
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48 0010 5A6C ldr r2, [r3, #68]
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49 0012 02F48042 and r2, r2, #16384
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50 0016 0092 str r2, [sp]
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51 .loc 1 71 3 view .LVU5
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52 0018 009A ldr r2, [sp]
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53 .LBE2:
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54 .loc 1 71 3 view .LVU6
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72:Core/Src/stm32f4xx_hal_msp.c **** __HAL_RCC_PWR_CLK_ENABLE();
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55 .loc 1 72 3 view .LVU7
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56 .LBB3:
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57 .loc 1 72 3 view .LVU8
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58 001a 0191 str r1, [sp, #4]
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59 .loc 1 72 3 view .LVU9
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60 001c 1A6C ldr r2, [r3, #64]
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61 001e 42F08052 orr r2, r2, #268435456
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62 0022 1A64 str r2, [r3, #64]
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63 .loc 1 72 3 view .LVU10
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64 0024 1B6C ldr r3, [r3, #64]
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65 0026 03F08053 and r3, r3, #268435456
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66 002a 0193 str r3, [sp, #4]
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67 .loc 1 72 3 view .LVU11
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68 002c 019B ldr r3, [sp, #4]
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69 .LBE3:
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70 .loc 1 72 3 view .LVU12
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73:Core/Src/stm32f4xx_hal_msp.c ****
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74:Core/Src/stm32f4xx_hal_msp.c **** /* System interrupt init*/
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75:Core/Src/stm32f4xx_hal_msp.c ****
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76:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN MspInit 1 */
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77:Core/Src/stm32f4xx_hal_msp.c ****
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78:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END MspInit 1 */
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79:Core/Src/stm32f4xx_hal_msp.c **** }
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71 .loc 1 79 1 is_stmt 0 view .LVU13
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72 002e 02B0 add sp, sp, #8
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73 .LCFI1:
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74 .cfi_def_cfa_offset 0
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75 @ sp needed
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76 0030 7047 bx lr
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77 .L4:
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78 0032 00BF .align 2
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79 .L3:
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80 0034 00380240 .word 1073887232
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81 .cfi_endproc
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82 .LFE239:
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84 .section .text.HAL_ADC_MspInit,"ax",%progbits
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85 .align 1
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86 .global HAL_ADC_MspInit
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87 .syntax unified
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88 .thumb
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89 .thumb_func
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91 HAL_ADC_MspInit:
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92 .LVL0:
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93 .LFB240:
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80:Core/Src/stm32f4xx_hal_msp.c ****
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81:Core/Src/stm32f4xx_hal_msp.c **** /**
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ARM GAS /tmp/ccZXUiNz.s page 4
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82:Core/Src/stm32f4xx_hal_msp.c **** * @brief ADC MSP Initialization
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83:Core/Src/stm32f4xx_hal_msp.c **** * This function configures the hardware resources used in this example
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84:Core/Src/stm32f4xx_hal_msp.c **** * @param hadc: ADC handle pointer
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85:Core/Src/stm32f4xx_hal_msp.c **** * @retval None
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86:Core/Src/stm32f4xx_hal_msp.c **** */
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87:Core/Src/stm32f4xx_hal_msp.c **** void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
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88:Core/Src/stm32f4xx_hal_msp.c **** {
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94 .loc 1 88 1 is_stmt 1 view -0
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95 .cfi_startproc
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96 @ args = 0, pretend = 0, frame = 32
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97 @ frame_needed = 0, uses_anonymous_args = 0
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98 .loc 1 88 1 is_stmt 0 view .LVU15
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99 0000 30B5 push {r4, r5, lr}
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100 .LCFI2:
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101 .cfi_def_cfa_offset 12
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102 .cfi_offset 4, -12
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103 .cfi_offset 5, -8
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104 .cfi_offset 14, -4
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105 0002 89B0 sub sp, sp, #36
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106 .LCFI3:
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107 .cfi_def_cfa_offset 48
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89:Core/Src/stm32f4xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
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108 .loc 1 89 3 is_stmt 1 view .LVU16
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109 .loc 1 89 20 is_stmt 0 view .LVU17
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110 0004 0023 movs r3, #0
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111 0006 0393 str r3, [sp, #12]
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112 0008 0493 str r3, [sp, #16]
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113 000a 0593 str r3, [sp, #20]
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114 000c 0693 str r3, [sp, #24]
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115 000e 0793 str r3, [sp, #28]
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90:Core/Src/stm32f4xx_hal_msp.c **** if(hadc->Instance==ADC1)
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116 .loc 1 90 3 is_stmt 1 view .LVU18
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117 .loc 1 90 10 is_stmt 0 view .LVU19
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118 0010 0268 ldr r2, [r0]
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119 .loc 1 90 5 view .LVU20
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120 0012 03F18043 add r3, r3, #1073741824
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121 0016 03F59033 add r3, r3, #73728
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122 001a 9A42 cmp r2, r3
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123 001c 01D0 beq .L9
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124 .LVL1:
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125 .L5:
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91:Core/Src/stm32f4xx_hal_msp.c **** {
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92:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN ADC1_MspInit 0 */
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93:Core/Src/stm32f4xx_hal_msp.c ****
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94:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END ADC1_MspInit 0 */
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95:Core/Src/stm32f4xx_hal_msp.c **** /* Peripheral clock enable */
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96:Core/Src/stm32f4xx_hal_msp.c **** __HAL_RCC_ADC1_CLK_ENABLE();
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97:Core/Src/stm32f4xx_hal_msp.c ****
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98:Core/Src/stm32f4xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
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99:Core/Src/stm32f4xx_hal_msp.c **** /**ADC1 GPIO Configuration
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100:Core/Src/stm32f4xx_hal_msp.c **** PA3 ------> ADC1_IN3
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101:Core/Src/stm32f4xx_hal_msp.c **** */
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102:Core/Src/stm32f4xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_3;
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103:Core/Src/stm32f4xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
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104:Core/Src/stm32f4xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
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105:Core/Src/stm32f4xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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106:Core/Src/stm32f4xx_hal_msp.c ****
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ARM GAS /tmp/ccZXUiNz.s page 5
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107:Core/Src/stm32f4xx_hal_msp.c **** /* ADC1 DMA Init */
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108:Core/Src/stm32f4xx_hal_msp.c **** /* ADC1 Init */
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109:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Instance = DMA2_Stream0;
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110:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Channel = DMA_CHANNEL_0;
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111:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
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112:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
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113:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
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114:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
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115:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
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116:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Mode = DMA_CIRCULAR;
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117:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
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118:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
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119:Core/Src/stm32f4xx_hal_msp.c **** if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
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120:Core/Src/stm32f4xx_hal_msp.c **** {
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121:Core/Src/stm32f4xx_hal_msp.c **** Error_Handler();
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122:Core/Src/stm32f4xx_hal_msp.c **** }
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123:Core/Src/stm32f4xx_hal_msp.c ****
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124:Core/Src/stm32f4xx_hal_msp.c **** __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1);
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125:Core/Src/stm32f4xx_hal_msp.c ****
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126:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN ADC1_MspInit 1 */
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127:Core/Src/stm32f4xx_hal_msp.c ****
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128:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END ADC1_MspInit 1 */
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129:Core/Src/stm32f4xx_hal_msp.c ****
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130:Core/Src/stm32f4xx_hal_msp.c **** }
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131:Core/Src/stm32f4xx_hal_msp.c ****
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132:Core/Src/stm32f4xx_hal_msp.c **** }
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126 .loc 1 132 1 view .LVU21
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127 001e 09B0 add sp, sp, #36
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128 .LCFI4:
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129 .cfi_remember_state
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130 .cfi_def_cfa_offset 12
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131 @ sp needed
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132 0020 30BD pop {r4, r5, pc}
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133 .LVL2:
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134 .L9:
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135 .LCFI5:
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136 .cfi_restore_state
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137 .loc 1 132 1 view .LVU22
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138 0022 0446 mov r4, r0
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96:Core/Src/stm32f4xx_hal_msp.c ****
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139 .loc 1 96 5 is_stmt 1 view .LVU23
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140 .LBB4:
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96:Core/Src/stm32f4xx_hal_msp.c ****
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141 .loc 1 96 5 view .LVU24
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142 0024 0025 movs r5, #0
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143 0026 0195 str r5, [sp, #4]
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96:Core/Src/stm32f4xx_hal_msp.c ****
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144 .loc 1 96 5 view .LVU25
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145 0028 03F58C33 add r3, r3, #71680
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146 002c 5A6C ldr r2, [r3, #68]
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147 002e 42F48072 orr r2, r2, #256
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148 0032 5A64 str r2, [r3, #68]
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96:Core/Src/stm32f4xx_hal_msp.c ****
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149 .loc 1 96 5 view .LVU26
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150 0034 5A6C ldr r2, [r3, #68]
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151 0036 02F48072 and r2, r2, #256
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152 003a 0192 str r2, [sp, #4]
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ARM GAS /tmp/ccZXUiNz.s page 6
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96:Core/Src/stm32f4xx_hal_msp.c ****
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153 .loc 1 96 5 view .LVU27
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154 003c 019A ldr r2, [sp, #4]
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155 .LBE4:
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96:Core/Src/stm32f4xx_hal_msp.c ****
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156 .loc 1 96 5 view .LVU28
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98:Core/Src/stm32f4xx_hal_msp.c **** /**ADC1 GPIO Configuration
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157 .loc 1 98 5 view .LVU29
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158 .LBB5:
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98:Core/Src/stm32f4xx_hal_msp.c **** /**ADC1 GPIO Configuration
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159 .loc 1 98 5 view .LVU30
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160 003e 0295 str r5, [sp, #8]
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98:Core/Src/stm32f4xx_hal_msp.c **** /**ADC1 GPIO Configuration
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161 .loc 1 98 5 view .LVU31
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162 0040 1A6B ldr r2, [r3, #48]
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163 0042 42F00102 orr r2, r2, #1
|
||
164 0046 1A63 str r2, [r3, #48]
|
||
98:Core/Src/stm32f4xx_hal_msp.c **** /**ADC1 GPIO Configuration
|
||
165 .loc 1 98 5 view .LVU32
|
||
166 0048 1B6B ldr r3, [r3, #48]
|
||
167 004a 03F00103 and r3, r3, #1
|
||
168 004e 0293 str r3, [sp, #8]
|
||
98:Core/Src/stm32f4xx_hal_msp.c **** /**ADC1 GPIO Configuration
|
||
169 .loc 1 98 5 view .LVU33
|
||
170 0050 029B ldr r3, [sp, #8]
|
||
171 .LBE5:
|
||
98:Core/Src/stm32f4xx_hal_msp.c **** /**ADC1 GPIO Configuration
|
||
172 .loc 1 98 5 view .LVU34
|
||
102:Core/Src/stm32f4xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
||
173 .loc 1 102 5 view .LVU35
|
||
102:Core/Src/stm32f4xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
||
174 .loc 1 102 25 is_stmt 0 view .LVU36
|
||
175 0052 0823 movs r3, #8
|
||
176 0054 0393 str r3, [sp, #12]
|
||
103:Core/Src/stm32f4xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
177 .loc 1 103 5 is_stmt 1 view .LVU37
|
||
103:Core/Src/stm32f4xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
178 .loc 1 103 26 is_stmt 0 view .LVU38
|
||
179 0056 0323 movs r3, #3
|
||
180 0058 0493 str r3, [sp, #16]
|
||
104:Core/Src/stm32f4xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||
181 .loc 1 104 5 is_stmt 1 view .LVU39
|
||
105:Core/Src/stm32f4xx_hal_msp.c ****
|
||
182 .loc 1 105 5 view .LVU40
|
||
183 005a 03A9 add r1, sp, #12
|
||
184 005c 1048 ldr r0, .L11
|
||
185 .LVL3:
|
||
105:Core/Src/stm32f4xx_hal_msp.c ****
|
||
186 .loc 1 105 5 is_stmt 0 view .LVU41
|
||
187 005e FFF7FEFF bl HAL_GPIO_Init
|
||
188 .LVL4:
|
||
109:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Channel = DMA_CHANNEL_0;
|
||
189 .loc 1 109 5 is_stmt 1 view .LVU42
|
||
109:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Channel = DMA_CHANNEL_0;
|
||
190 .loc 1 109 24 is_stmt 0 view .LVU43
|
||
191 0062 1048 ldr r0, .L11+4
|
||
192 0064 104B ldr r3, .L11+8
|
||
ARM GAS /tmp/ccZXUiNz.s page 7
|
||
|
||
|
||
193 0066 0360 str r3, [r0]
|
||
110:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
||
194 .loc 1 110 5 is_stmt 1 view .LVU44
|
||
110:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
||
195 .loc 1 110 28 is_stmt 0 view .LVU45
|
||
196 0068 4560 str r5, [r0, #4]
|
||
111:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
|
||
197 .loc 1 111 5 is_stmt 1 view .LVU46
|
||
111:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
|
||
198 .loc 1 111 30 is_stmt 0 view .LVU47
|
||
199 006a 8560 str r5, [r0, #8]
|
||
112:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
|
||
200 .loc 1 112 5 is_stmt 1 view .LVU48
|
||
112:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
|
||
201 .loc 1 112 30 is_stmt 0 view .LVU49
|
||
202 006c C560 str r5, [r0, #12]
|
||
113:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
|
||
203 .loc 1 113 5 is_stmt 1 view .LVU50
|
||
113:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
|
||
204 .loc 1 113 27 is_stmt 0 view .LVU51
|
||
205 006e 4FF48063 mov r3, #1024
|
||
206 0072 0361 str r3, [r0, #16]
|
||
114:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
|
||
207 .loc 1 114 5 is_stmt 1 view .LVU52
|
||
114:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
|
||
208 .loc 1 114 40 is_stmt 0 view .LVU53
|
||
209 0074 4FF40063 mov r3, #2048
|
||
210 0078 4361 str r3, [r0, #20]
|
||
115:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Mode = DMA_CIRCULAR;
|
||
211 .loc 1 115 5 is_stmt 1 view .LVU54
|
||
115:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Mode = DMA_CIRCULAR;
|
||
212 .loc 1 115 37 is_stmt 0 view .LVU55
|
||
213 007a 4FF40053 mov r3, #8192
|
||
214 007e 8361 str r3, [r0, #24]
|
||
116:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
|
||
215 .loc 1 116 5 is_stmt 1 view .LVU56
|
||
116:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
|
||
216 .loc 1 116 25 is_stmt 0 view .LVU57
|
||
217 0080 4FF48073 mov r3, #256
|
||
218 0084 C361 str r3, [r0, #28]
|
||
117:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
||
219 .loc 1 117 5 is_stmt 1 view .LVU58
|
||
117:Core/Src/stm32f4xx_hal_msp.c **** hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
||
220 .loc 1 117 29 is_stmt 0 view .LVU59
|
||
221 0086 0562 str r5, [r0, #32]
|
||
118:Core/Src/stm32f4xx_hal_msp.c **** if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
|
||
222 .loc 1 118 5 is_stmt 1 view .LVU60
|
||
118:Core/Src/stm32f4xx_hal_msp.c **** if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
|
||
223 .loc 1 118 29 is_stmt 0 view .LVU61
|
||
224 0088 4562 str r5, [r0, #36]
|
||
119:Core/Src/stm32f4xx_hal_msp.c **** {
|
||
225 .loc 1 119 5 is_stmt 1 view .LVU62
|
||
119:Core/Src/stm32f4xx_hal_msp.c **** {
|
||
226 .loc 1 119 9 is_stmt 0 view .LVU63
|
||
227 008a FFF7FEFF bl HAL_DMA_Init
|
||
228 .LVL5:
|
||
119:Core/Src/stm32f4xx_hal_msp.c **** {
|
||
ARM GAS /tmp/ccZXUiNz.s page 8
|
||
|
||
|
||
229 .loc 1 119 8 discriminator 1 view .LVU64
|
||
230 008e 18B9 cbnz r0, .L10
|
||
231 .L7:
|
||
124:Core/Src/stm32f4xx_hal_msp.c ****
|
||
232 .loc 1 124 5 is_stmt 1 view .LVU65
|
||
124:Core/Src/stm32f4xx_hal_msp.c ****
|
||
233 .loc 1 124 5 view .LVU66
|
||
234 0090 044B ldr r3, .L11+4
|
||
235 0092 A363 str r3, [r4, #56]
|
||
124:Core/Src/stm32f4xx_hal_msp.c ****
|
||
236 .loc 1 124 5 view .LVU67
|
||
237 0094 9C63 str r4, [r3, #56]
|
||
124:Core/Src/stm32f4xx_hal_msp.c ****
|
||
238 .loc 1 124 5 discriminator 1 view .LVU68
|
||
239 .loc 1 132 1 is_stmt 0 view .LVU69
|
||
240 0096 C2E7 b .L5
|
||
241 .L10:
|
||
121:Core/Src/stm32f4xx_hal_msp.c **** }
|
||
242 .loc 1 121 7 is_stmt 1 view .LVU70
|
||
243 0098 FFF7FEFF bl Error_Handler
|
||
244 .LVL6:
|
||
245 009c F8E7 b .L7
|
||
246 .L12:
|
||
247 009e 00BF .align 2
|
||
248 .L11:
|
||
249 00a0 00000240 .word 1073872896
|
||
250 00a4 00000000 .word hdma_adc1
|
||
251 00a8 10640240 .word 1073898512
|
||
252 .cfi_endproc
|
||
253 .LFE240:
|
||
255 .section .text.HAL_ADC_MspDeInit,"ax",%progbits
|
||
256 .align 1
|
||
257 .global HAL_ADC_MspDeInit
|
||
258 .syntax unified
|
||
259 .thumb
|
||
260 .thumb_func
|
||
262 HAL_ADC_MspDeInit:
|
||
263 .LVL7:
|
||
264 .LFB241:
|
||
133:Core/Src/stm32f4xx_hal_msp.c ****
|
||
134:Core/Src/stm32f4xx_hal_msp.c **** /**
|
||
135:Core/Src/stm32f4xx_hal_msp.c **** * @brief ADC MSP De-Initialization
|
||
136:Core/Src/stm32f4xx_hal_msp.c **** * This function freeze the hardware resources used in this example
|
||
137:Core/Src/stm32f4xx_hal_msp.c **** * @param hadc: ADC handle pointer
|
||
138:Core/Src/stm32f4xx_hal_msp.c **** * @retval None
|
||
139:Core/Src/stm32f4xx_hal_msp.c **** */
|
||
140:Core/Src/stm32f4xx_hal_msp.c **** void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
|
||
141:Core/Src/stm32f4xx_hal_msp.c **** {
|
||
265 .loc 1 141 1 view -0
|
||
266 .cfi_startproc
|
||
267 @ args = 0, pretend = 0, frame = 0
|
||
268 @ frame_needed = 0, uses_anonymous_args = 0
|
||
142:Core/Src/stm32f4xx_hal_msp.c **** if(hadc->Instance==ADC1)
|
||
269 .loc 1 142 3 view .LVU72
|
||
270 .loc 1 142 10 is_stmt 0 view .LVU73
|
||
271 0000 0268 ldr r2, [r0]
|
||
272 .loc 1 142 5 view .LVU74
|
||
ARM GAS /tmp/ccZXUiNz.s page 9
|
||
|
||
|
||
273 0002 094B ldr r3, .L20
|
||
274 0004 9A42 cmp r2, r3
|
||
275 0006 00D0 beq .L19
|
||
276 0008 7047 bx lr
|
||
277 .L19:
|
||
141:Core/Src/stm32f4xx_hal_msp.c **** if(hadc->Instance==ADC1)
|
||
278 .loc 1 141 1 view .LVU75
|
||
279 000a 10B5 push {r4, lr}
|
||
280 .LCFI6:
|
||
281 .cfi_def_cfa_offset 8
|
||
282 .cfi_offset 4, -8
|
||
283 .cfi_offset 14, -4
|
||
284 000c 0446 mov r4, r0
|
||
143:Core/Src/stm32f4xx_hal_msp.c **** {
|
||
144:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN ADC1_MspDeInit 0 */
|
||
145:Core/Src/stm32f4xx_hal_msp.c ****
|
||
146:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END ADC1_MspDeInit 0 */
|
||
147:Core/Src/stm32f4xx_hal_msp.c **** /* Peripheral clock disable */
|
||
148:Core/Src/stm32f4xx_hal_msp.c **** __HAL_RCC_ADC1_CLK_DISABLE();
|
||
285 .loc 1 148 5 is_stmt 1 view .LVU76
|
||
286 000e 074A ldr r2, .L20+4
|
||
287 0010 536C ldr r3, [r2, #68]
|
||
288 0012 23F48073 bic r3, r3, #256
|
||
289 0016 5364 str r3, [r2, #68]
|
||
149:Core/Src/stm32f4xx_hal_msp.c ****
|
||
150:Core/Src/stm32f4xx_hal_msp.c **** /**ADC1 GPIO Configuration
|
||
151:Core/Src/stm32f4xx_hal_msp.c **** PA3 ------> ADC1_IN3
|
||
152:Core/Src/stm32f4xx_hal_msp.c **** */
|
||
153:Core/Src/stm32f4xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOA, GPIO_PIN_3);
|
||
290 .loc 1 153 5 view .LVU77
|
||
291 0018 0821 movs r1, #8
|
||
292 001a 0548 ldr r0, .L20+8
|
||
293 .LVL8:
|
||
294 .loc 1 153 5 is_stmt 0 view .LVU78
|
||
295 001c FFF7FEFF bl HAL_GPIO_DeInit
|
||
296 .LVL9:
|
||
154:Core/Src/stm32f4xx_hal_msp.c ****
|
||
155:Core/Src/stm32f4xx_hal_msp.c **** /* ADC1 DMA DeInit */
|
||
156:Core/Src/stm32f4xx_hal_msp.c **** HAL_DMA_DeInit(hadc->DMA_Handle);
|
||
297 .loc 1 156 5 is_stmt 1 view .LVU79
|
||
298 0020 A06B ldr r0, [r4, #56]
|
||
299 0022 FFF7FEFF bl HAL_DMA_DeInit
|
||
300 .LVL10:
|
||
157:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE BEGIN ADC1_MspDeInit 1 */
|
||
158:Core/Src/stm32f4xx_hal_msp.c ****
|
||
159:Core/Src/stm32f4xx_hal_msp.c **** /* USER CODE END ADC1_MspDeInit 1 */
|
||
160:Core/Src/stm32f4xx_hal_msp.c **** }
|
||
161:Core/Src/stm32f4xx_hal_msp.c ****
|
||
162:Core/Src/stm32f4xx_hal_msp.c **** }
|
||
301 .loc 1 162 1 is_stmt 0 view .LVU80
|
||
302 0026 10BD pop {r4, pc}
|
||
303 .LVL11:
|
||
304 .L21:
|
||
305 .loc 1 162 1 view .LVU81
|
||
306 .align 2
|
||
307 .L20:
|
||
308 0028 00200140 .word 1073815552
|
||
ARM GAS /tmp/ccZXUiNz.s page 10
|
||
|
||
|
||
309 002c 00380240 .word 1073887232
|
||
310 0030 00000240 .word 1073872896
|
||
311 .cfi_endproc
|
||
312 .LFE241:
|
||
314 .text
|
||
315 .Letext0:
|
||
316 .file 2 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h"
|
||
317 .file 3 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h"
|
||
318 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
|
||
319 .file 5 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h"
|
||
320 .file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h"
|
||
321 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h"
|
||
322 .file 8 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h"
|
||
323 .file 9 "Core/Inc/main.h"
|
||
ARM GAS /tmp/ccZXUiNz.s page 11
|
||
|
||
|
||
DEFINED SYMBOLS
|
||
*ABS*:00000000 stm32f4xx_hal_msp.c
|
||
/tmp/ccZXUiNz.s:21 .text.HAL_MspInit:00000000 $t
|
||
/tmp/ccZXUiNz.s:27 .text.HAL_MspInit:00000000 HAL_MspInit
|
||
/tmp/ccZXUiNz.s:80 .text.HAL_MspInit:00000034 $d
|
||
/tmp/ccZXUiNz.s:85 .text.HAL_ADC_MspInit:00000000 $t
|
||
/tmp/ccZXUiNz.s:91 .text.HAL_ADC_MspInit:00000000 HAL_ADC_MspInit
|
||
/tmp/ccZXUiNz.s:249 .text.HAL_ADC_MspInit:000000a0 $d
|
||
/tmp/ccZXUiNz.s:256 .text.HAL_ADC_MspDeInit:00000000 $t
|
||
/tmp/ccZXUiNz.s:262 .text.HAL_ADC_MspDeInit:00000000 HAL_ADC_MspDeInit
|
||
/tmp/ccZXUiNz.s:308 .text.HAL_ADC_MspDeInit:00000028 $d
|
||
|
||
UNDEFINED SYMBOLS
|
||
HAL_GPIO_Init
|
||
HAL_DMA_Init
|
||
Error_Handler
|
||
hdma_adc1
|
||
HAL_GPIO_DeInit
|
||
HAL_DMA_DeInit
|