ChTheo/RFG_stm32_ADC_STM32F429
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RFG_stm32_ADC_STM32F429/build/stm32f4xx_it.lst

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ARM GAS /tmp/cceMYWsz.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "stm32f4xx_it.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .file 1 "Core/Src/stm32f4xx_it.c"
20 .section .text.NMI_Handler,"ax",%progbits
21 .align 1
22 .global NMI_Handler
23 .syntax unified
24 .thumb
25 .thumb_func
27 NMI_Handler:
28 .LFB239:
1:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN Header */
2:Core/Src/stm32f4xx_it.c **** /**
3:Core/Src/stm32f4xx_it.c **** ******************************************************************************
4:Core/Src/stm32f4xx_it.c **** * @file stm32f4xx_it.c
5:Core/Src/stm32f4xx_it.c **** * @brief Interrupt Service Routines.
6:Core/Src/stm32f4xx_it.c **** ******************************************************************************
7:Core/Src/stm32f4xx_it.c **** * @attention
8:Core/Src/stm32f4xx_it.c **** *
9:Core/Src/stm32f4xx_it.c **** * Copyright (c) 2025 STMicroelectronics.
10:Core/Src/stm32f4xx_it.c **** * All rights reserved.
11:Core/Src/stm32f4xx_it.c **** *
12:Core/Src/stm32f4xx_it.c **** * This software is licensed under terms that can be found in the LICENSE file
13:Core/Src/stm32f4xx_it.c **** * in the root directory of this software component.
14:Core/Src/stm32f4xx_it.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
15:Core/Src/stm32f4xx_it.c **** *
16:Core/Src/stm32f4xx_it.c **** ******************************************************************************
17:Core/Src/stm32f4xx_it.c **** */
18:Core/Src/stm32f4xx_it.c **** /* USER CODE END Header */
19:Core/Src/stm32f4xx_it.c ****
20:Core/Src/stm32f4xx_it.c **** /* Includes ------------------------------------------------------------------*/
21:Core/Src/stm32f4xx_it.c **** #include "main.h"
22:Core/Src/stm32f4xx_it.c **** #include "stm32f4xx_it.h"
23:Core/Src/stm32f4xx_it.c **** /* Private includes ----------------------------------------------------------*/
24:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN Includes */
25:Core/Src/stm32f4xx_it.c **** /* USER CODE END Includes */
26:Core/Src/stm32f4xx_it.c ****
27:Core/Src/stm32f4xx_it.c **** /* Private typedef -----------------------------------------------------------*/
28:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN TD */
29:Core/Src/stm32f4xx_it.c ****
30:Core/Src/stm32f4xx_it.c **** /* USER CODE END TD */
ARM GAS /tmp/cceMYWsz.s page 2
31:Core/Src/stm32f4xx_it.c ****
32:Core/Src/stm32f4xx_it.c **** /* Private define ------------------------------------------------------------*/
33:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PD */
34:Core/Src/stm32f4xx_it.c ****
35:Core/Src/stm32f4xx_it.c **** /* USER CODE END PD */
36:Core/Src/stm32f4xx_it.c ****
37:Core/Src/stm32f4xx_it.c **** /* Private macro -------------------------------------------------------------*/
38:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PM */
39:Core/Src/stm32f4xx_it.c ****
40:Core/Src/stm32f4xx_it.c **** /* USER CODE END PM */
41:Core/Src/stm32f4xx_it.c ****
42:Core/Src/stm32f4xx_it.c **** /* Private variables ---------------------------------------------------------*/
43:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PV */
44:Core/Src/stm32f4xx_it.c ****
45:Core/Src/stm32f4xx_it.c **** /* USER CODE END PV */
46:Core/Src/stm32f4xx_it.c ****
47:Core/Src/stm32f4xx_it.c **** /* Private function prototypes -----------------------------------------------*/
48:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PFP */
49:Core/Src/stm32f4xx_it.c ****
50:Core/Src/stm32f4xx_it.c **** /* USER CODE END PFP */
51:Core/Src/stm32f4xx_it.c ****
52:Core/Src/stm32f4xx_it.c **** /* Private user code ---------------------------------------------------------*/
53:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN 0 */
54:Core/Src/stm32f4xx_it.c ****
55:Core/Src/stm32f4xx_it.c **** /* USER CODE END 0 */
56:Core/Src/stm32f4xx_it.c ****
57:Core/Src/stm32f4xx_it.c **** /* External variables --------------------------------------------------------*/
58:Core/Src/stm32f4xx_it.c **** extern PCD_HandleTypeDef hpcd_USB_OTG_FS;
59:Core/Src/stm32f4xx_it.c **** extern DMA_HandleTypeDef hdma_adc1;
60:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN EV */
61:Core/Src/stm32f4xx_it.c **** /* Externs are provided via main.h; no extra declarations needed here */
62:Core/Src/stm32f4xx_it.c **** /* USER CODE END EV */
63:Core/Src/stm32f4xx_it.c ****
64:Core/Src/stm32f4xx_it.c **** /******************************************************************************/
65:Core/Src/stm32f4xx_it.c **** /* Cortex-M4 Processor Interruption and Exception Handlers */
66:Core/Src/stm32f4xx_it.c **** /******************************************************************************/
67:Core/Src/stm32f4xx_it.c **** /**
68:Core/Src/stm32f4xx_it.c **** * @brief This function handles Non maskable interrupt.
69:Core/Src/stm32f4xx_it.c **** */
70:Core/Src/stm32f4xx_it.c **** void NMI_Handler(void)
71:Core/Src/stm32f4xx_it.c **** {
29 .loc 1 71 1 view -0
30 .cfi_startproc
31 @ Volatile: function does not return.
32 @ args = 0, pretend = 0, frame = 0
33 @ frame_needed = 0, uses_anonymous_args = 0
34 @ link register save eliminated.
35 .L2:
72:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
73:Core/Src/stm32f4xx_it.c ****
74:Core/Src/stm32f4xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 0 */
75:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
76:Core/Src/stm32f4xx_it.c **** while (1)
36 .loc 1 76 4 view .LVU1
77:Core/Src/stm32f4xx_it.c **** {
78:Core/Src/stm32f4xx_it.c **** }
37 .loc 1 78 3 view .LVU2
ARM GAS /tmp/cceMYWsz.s page 3
76:Core/Src/stm32f4xx_it.c **** {
38 .loc 1 76 10 view .LVU3
39 0000 FEE7 b .L2
40 .cfi_endproc
41 .LFE239:
43 .section .text.HardFault_Handler,"ax",%progbits
44 .align 1
45 .global HardFault_Handler
46 .syntax unified
47 .thumb
48 .thumb_func
50 HardFault_Handler:
51 .LFB240:
79:Core/Src/stm32f4xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 1 */
80:Core/Src/stm32f4xx_it.c **** }
81:Core/Src/stm32f4xx_it.c ****
82:Core/Src/stm32f4xx_it.c **** /**
83:Core/Src/stm32f4xx_it.c **** * @brief This function handles Hard fault interrupt.
84:Core/Src/stm32f4xx_it.c **** */
85:Core/Src/stm32f4xx_it.c **** void HardFault_Handler(void)
86:Core/Src/stm32f4xx_it.c **** {
52 .loc 1 86 1 view -0
53 .cfi_startproc
54 @ Volatile: function does not return.
55 @ args = 0, pretend = 0, frame = 0
56 @ frame_needed = 0, uses_anonymous_args = 0
57 @ link register save eliminated.
58 .L4:
87:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN HardFault_IRQn 0 */
88:Core/Src/stm32f4xx_it.c ****
89:Core/Src/stm32f4xx_it.c **** /* USER CODE END HardFault_IRQn 0 */
90:Core/Src/stm32f4xx_it.c **** while (1)
59 .loc 1 90 3 view .LVU5
91:Core/Src/stm32f4xx_it.c **** {
92:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_HardFault_IRQn 0 */
93:Core/Src/stm32f4xx_it.c **** /* USER CODE END W1_HardFault_IRQn 0 */
94:Core/Src/stm32f4xx_it.c **** }
60 .loc 1 94 3 view .LVU6
90:Core/Src/stm32f4xx_it.c **** {
61 .loc 1 90 9 view .LVU7
62 0000 FEE7 b .L4
63 .cfi_endproc
64 .LFE240:
66 .section .text.MemManage_Handler,"ax",%progbits
67 .align 1
68 .global MemManage_Handler
69 .syntax unified
70 .thumb
71 .thumb_func
73 MemManage_Handler:
74 .LFB241:
95:Core/Src/stm32f4xx_it.c **** }
96:Core/Src/stm32f4xx_it.c ****
97:Core/Src/stm32f4xx_it.c **** /**
98:Core/Src/stm32f4xx_it.c **** * @brief This function handles Memory management fault.
99:Core/Src/stm32f4xx_it.c **** */
100:Core/Src/stm32f4xx_it.c **** void MemManage_Handler(void)
ARM GAS /tmp/cceMYWsz.s page 4
101:Core/Src/stm32f4xx_it.c **** {
75 .loc 1 101 1 view -0
76 .cfi_startproc
77 @ Volatile: function does not return.
78 @ args = 0, pretend = 0, frame = 0
79 @ frame_needed = 0, uses_anonymous_args = 0
80 @ link register save eliminated.
81 .L6:
102:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN MemoryManagement_IRQn 0 */
103:Core/Src/stm32f4xx_it.c ****
104:Core/Src/stm32f4xx_it.c **** /* USER CODE END MemoryManagement_IRQn 0 */
105:Core/Src/stm32f4xx_it.c **** while (1)
82 .loc 1 105 3 view .LVU9
106:Core/Src/stm32f4xx_it.c **** {
107:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
108:Core/Src/stm32f4xx_it.c **** /* USER CODE END W1_MemoryManagement_IRQn 0 */
109:Core/Src/stm32f4xx_it.c **** }
83 .loc 1 109 3 view .LVU10
105:Core/Src/stm32f4xx_it.c **** {
84 .loc 1 105 9 view .LVU11
85 0000 FEE7 b .L6
86 .cfi_endproc
87 .LFE241:
89 .section .text.BusFault_Handler,"ax",%progbits
90 .align 1
91 .global BusFault_Handler
92 .syntax unified
93 .thumb
94 .thumb_func
96 BusFault_Handler:
97 .LFB242:
110:Core/Src/stm32f4xx_it.c **** }
111:Core/Src/stm32f4xx_it.c ****
112:Core/Src/stm32f4xx_it.c **** /**
113:Core/Src/stm32f4xx_it.c **** * @brief This function handles Pre-fetch fault, memory access fault.
114:Core/Src/stm32f4xx_it.c **** */
115:Core/Src/stm32f4xx_it.c **** void BusFault_Handler(void)
116:Core/Src/stm32f4xx_it.c **** {
98 .loc 1 116 1 view -0
99 .cfi_startproc
100 @ Volatile: function does not return.
101 @ args = 0, pretend = 0, frame = 0
102 @ frame_needed = 0, uses_anonymous_args = 0
103 @ link register save eliminated.
104 .L8:
117:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN BusFault_IRQn 0 */
118:Core/Src/stm32f4xx_it.c ****
119:Core/Src/stm32f4xx_it.c **** /* USER CODE END BusFault_IRQn 0 */
120:Core/Src/stm32f4xx_it.c **** while (1)
105 .loc 1 120 3 view .LVU13
121:Core/Src/stm32f4xx_it.c **** {
122:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_BusFault_IRQn 0 */
123:Core/Src/stm32f4xx_it.c **** /* USER CODE END W1_BusFault_IRQn 0 */
124:Core/Src/stm32f4xx_it.c **** }
106 .loc 1 124 3 view .LVU14
120:Core/Src/stm32f4xx_it.c **** {
107 .loc 1 120 9 view .LVU15
ARM GAS /tmp/cceMYWsz.s page 5
108 0000 FEE7 b .L8
109 .cfi_endproc
110 .LFE242:
112 .section .text.UsageFault_Handler,"ax",%progbits
113 .align 1
114 .global UsageFault_Handler
115 .syntax unified
116 .thumb
117 .thumb_func
119 UsageFault_Handler:
120 .LFB243:
125:Core/Src/stm32f4xx_it.c **** }
126:Core/Src/stm32f4xx_it.c ****
127:Core/Src/stm32f4xx_it.c **** /**
128:Core/Src/stm32f4xx_it.c **** * @brief This function handles Undefined instruction or illegal state.
129:Core/Src/stm32f4xx_it.c **** */
130:Core/Src/stm32f4xx_it.c **** void UsageFault_Handler(void)
131:Core/Src/stm32f4xx_it.c **** {
121 .loc 1 131 1 view -0
122 .cfi_startproc
123 @ Volatile: function does not return.
124 @ args = 0, pretend = 0, frame = 0
125 @ frame_needed = 0, uses_anonymous_args = 0
126 @ link register save eliminated.
127 .L10:
132:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN UsageFault_IRQn 0 */
133:Core/Src/stm32f4xx_it.c ****
134:Core/Src/stm32f4xx_it.c **** /* USER CODE END UsageFault_IRQn 0 */
135:Core/Src/stm32f4xx_it.c **** while (1)
128 .loc 1 135 3 view .LVU17
136:Core/Src/stm32f4xx_it.c **** {
137:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
138:Core/Src/stm32f4xx_it.c **** /* USER CODE END W1_UsageFault_IRQn 0 */
139:Core/Src/stm32f4xx_it.c **** }
129 .loc 1 139 3 view .LVU18
135:Core/Src/stm32f4xx_it.c **** {
130 .loc 1 135 9 view .LVU19
131 0000 FEE7 b .L10
132 .cfi_endproc
133 .LFE243:
135 .section .text.SVC_Handler,"ax",%progbits
136 .align 1
137 .global SVC_Handler
138 .syntax unified
139 .thumb
140 .thumb_func
142 SVC_Handler:
143 .LFB244:
140:Core/Src/stm32f4xx_it.c **** }
141:Core/Src/stm32f4xx_it.c ****
142:Core/Src/stm32f4xx_it.c **** /**
143:Core/Src/stm32f4xx_it.c **** * @brief This function handles System service call via SWI instruction.
144:Core/Src/stm32f4xx_it.c **** */
145:Core/Src/stm32f4xx_it.c **** void SVC_Handler(void)
146:Core/Src/stm32f4xx_it.c **** {
144 .loc 1 146 1 view -0
145 .cfi_startproc
ARM GAS /tmp/cceMYWsz.s page 6
146 @ args = 0, pretend = 0, frame = 0
147 @ frame_needed = 0, uses_anonymous_args = 0
148 @ link register save eliminated.
147:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 0 */
148:Core/Src/stm32f4xx_it.c ****
149:Core/Src/stm32f4xx_it.c **** /* USER CODE END SVCall_IRQn 0 */
150:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 1 */
151:Core/Src/stm32f4xx_it.c ****
152:Core/Src/stm32f4xx_it.c **** /* USER CODE END SVCall_IRQn 1 */
153:Core/Src/stm32f4xx_it.c **** }
149 .loc 1 153 1 view .LVU21
150 0000 7047 bx lr
151 .cfi_endproc
152 .LFE244:
154 .section .text.DebugMon_Handler,"ax",%progbits
155 .align 1
156 .global DebugMon_Handler
157 .syntax unified
158 .thumb
159 .thumb_func
161 DebugMon_Handler:
162 .LFB245:
154:Core/Src/stm32f4xx_it.c ****
155:Core/Src/stm32f4xx_it.c **** /**
156:Core/Src/stm32f4xx_it.c **** * @brief This function handles Debug monitor.
157:Core/Src/stm32f4xx_it.c **** */
158:Core/Src/stm32f4xx_it.c **** void DebugMon_Handler(void)
159:Core/Src/stm32f4xx_it.c **** {
163 .loc 1 159 1 view -0
164 .cfi_startproc
165 @ args = 0, pretend = 0, frame = 0
166 @ frame_needed = 0, uses_anonymous_args = 0
167 @ link register save eliminated.
160:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 0 */
161:Core/Src/stm32f4xx_it.c ****
162:Core/Src/stm32f4xx_it.c **** /* USER CODE END DebugMonitor_IRQn 0 */
163:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 1 */
164:Core/Src/stm32f4xx_it.c ****
165:Core/Src/stm32f4xx_it.c **** /* USER CODE END DebugMonitor_IRQn 1 */
166:Core/Src/stm32f4xx_it.c **** }
168 .loc 1 166 1 view .LVU23
169 0000 7047 bx lr
170 .cfi_endproc
171 .LFE245:
173 .section .text.PendSV_Handler,"ax",%progbits
174 .align 1
175 .global PendSV_Handler
176 .syntax unified
177 .thumb
178 .thumb_func
180 PendSV_Handler:
181 .LFB246:
167:Core/Src/stm32f4xx_it.c ****
168:Core/Src/stm32f4xx_it.c **** /**
169:Core/Src/stm32f4xx_it.c **** * @brief This function handles Pendable request for system service.
170:Core/Src/stm32f4xx_it.c **** */
171:Core/Src/stm32f4xx_it.c **** void PendSV_Handler(void)
ARM GAS /tmp/cceMYWsz.s page 7
172:Core/Src/stm32f4xx_it.c **** {
182 .loc 1 172 1 view -0
183 .cfi_startproc
184 @ args = 0, pretend = 0, frame = 0
185 @ frame_needed = 0, uses_anonymous_args = 0
186 @ link register save eliminated.
173:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 0 */
174:Core/Src/stm32f4xx_it.c ****
175:Core/Src/stm32f4xx_it.c **** /* USER CODE END PendSV_IRQn 0 */
176:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 1 */
177:Core/Src/stm32f4xx_it.c ****
178:Core/Src/stm32f4xx_it.c **** /* USER CODE END PendSV_IRQn 1 */
179:Core/Src/stm32f4xx_it.c **** }
187 .loc 1 179 1 view .LVU25
188 0000 7047 bx lr
189 .cfi_endproc
190 .LFE246:
192 .section .text.SysTick_Handler,"ax",%progbits
193 .align 1
194 .global SysTick_Handler
195 .syntax unified
196 .thumb
197 .thumb_func
199 SysTick_Handler:
200 .LFB247:
180:Core/Src/stm32f4xx_it.c ****
181:Core/Src/stm32f4xx_it.c **** /**
182:Core/Src/stm32f4xx_it.c **** * @brief This function handles System tick timer.
183:Core/Src/stm32f4xx_it.c **** */
184:Core/Src/stm32f4xx_it.c **** void SysTick_Handler(void)
185:Core/Src/stm32f4xx_it.c **** {
201 .loc 1 185 1 view -0
202 .cfi_startproc
203 @ args = 0, pretend = 0, frame = 0
204 @ frame_needed = 0, uses_anonymous_args = 0
205 0000 08B5 push {r3, lr}
206 .LCFI0:
207 .cfi_def_cfa_offset 8
208 .cfi_offset 3, -8
209 .cfi_offset 14, -4
186:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 0 */
187:Core/Src/stm32f4xx_it.c ****
188:Core/Src/stm32f4xx_it.c **** /* USER CODE END SysTick_IRQn 0 */
189:Core/Src/stm32f4xx_it.c **** HAL_IncTick();
210 .loc 1 189 3 view .LVU27
211 0002 FFF7FEFF bl HAL_IncTick
212 .LVL0:
190:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 1 */
191:Core/Src/stm32f4xx_it.c ****
192:Core/Src/stm32f4xx_it.c **** /* USER CODE END SysTick_IRQn 1 */
193:Core/Src/stm32f4xx_it.c **** }
213 .loc 1 193 1 is_stmt 0 view .LVU28
214 0006 08BD pop {r3, pc}
215 .cfi_endproc
216 .LFE247:
218 .section .text.EXTI0_IRQHandler,"ax",%progbits
219 .align 1
ARM GAS /tmp/cceMYWsz.s page 8
220 .global EXTI0_IRQHandler
221 .syntax unified
222 .thumb
223 .thumb_func
225 EXTI0_IRQHandler:
226 .LFB248:
194:Core/Src/stm32f4xx_it.c ****
195:Core/Src/stm32f4xx_it.c **** /******************************************************************************/
196:Core/Src/stm32f4xx_it.c **** /* STM32F4xx Peripheral Interrupt Handlers */
197:Core/Src/stm32f4xx_it.c **** /* Add here the Interrupt Handlers for the used peripherals. */
198:Core/Src/stm32f4xx_it.c **** /* For the available peripheral interrupt handler names, */
199:Core/Src/stm32f4xx_it.c **** /* please refer to the startup file (startup_stm32f4xx.s). */
200:Core/Src/stm32f4xx_it.c **** /******************************************************************************/
201:Core/Src/stm32f4xx_it.c ****
202:Core/Src/stm32f4xx_it.c **** /**
203:Core/Src/stm32f4xx_it.c **** * @brief This function handles EXTI line0 interrupt.
204:Core/Src/stm32f4xx_it.c **** */
205:Core/Src/stm32f4xx_it.c **** void EXTI0_IRQHandler(void)
206:Core/Src/stm32f4xx_it.c **** {
227 .loc 1 206 1 is_stmt 1 view -0
228 .cfi_startproc
229 @ args = 0, pretend = 0, frame = 0
230 @ frame_needed = 0, uses_anonymous_args = 0
231 0000 08B5 push {r3, lr}
232 .LCFI1:
233 .cfi_def_cfa_offset 8
234 .cfi_offset 3, -8
235 .cfi_offset 14, -4
207:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN EXTI0_IRQn 0 */
208:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_start_DMA_N = ADC_BUFF_SIZE - hdma_adc1.Instance->NDTR;
236 .loc 1 208 3 view .LVU30
237 .loc 1 208 64 is_stmt 0 view .LVU31
238 0002 0C4B ldr r3, .L20
239 0004 1B68 ldr r3, [r3]
240 .loc 1 208 73 view .LVU32
241 0006 5B68 ldr r3, [r3, #4]
242 .loc 1 208 53 view .LVU33
243 0008 C3F14003 rsb r3, r3, #64
244 .loc 1 208 37 view .LVU34
245 000c 0A4A ldr r2, .L20+4
246 000e 9360 str r3, [r2, #8]
209:Core/Src/stm32f4xx_it.c **** if (Sweep_state.curr_step_start_DMA_N < ADC_BUFF_SIZE/2) {
247 .loc 1 209 3 is_stmt 1 view .LVU35
248 .loc 1 209 18 is_stmt 0 view .LVU36
249 0010 9368 ldr r3, [r2, #8]
250 .loc 1 209 6 view .LVU37
251 0012 1F2B cmp r3, #31
252 0014 0AD8 bhi .L17
210:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag =1; // first half DMA buffer
253 .loc 1 210 5 is_stmt 1 view .LVU38
254 .loc 1 210 40 is_stmt 0 view .LVU39
255 0016 1346 mov r3, r2
256 0018 0122 movs r2, #1
257 001a 1A71 strb r2, [r3, #4]
258 .L18:
211:Core/Src/stm32f4xx_it.c **** } else{
212:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag =2; // second half DMA buffer
ARM GAS /tmp/cceMYWsz.s page 9
213:Core/Src/stm32f4xx_it.c **** }
214:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_N++;
259 .loc 1 214 3 is_stmt 1 view .LVU40
260 .loc 1 214 14 is_stmt 0 view .LVU41
261 001c 064A ldr r2, .L20+4
262 001e 1368 ldr r3, [r2]
263 .loc 1 214 26 view .LVU42
264 0020 0133 adds r3, r3, #1
265 0022 1360 str r3, [r2]
215:Core/Src/stm32f4xx_it.c **** /* USER CODE END EXTI0_IRQn 0 */
216:Core/Src/stm32f4xx_it.c **** HAL_GPIO_EXTI_IRQHandler(CURR_STEP_START_TRG_Pin);
266 .loc 1 216 3 is_stmt 1 view .LVU43
267 0024 0120 movs r0, #1
268 0026 FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler
269 .LVL1:
217:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN EXTI0_IRQn 1 */
218:Core/Src/stm32f4xx_it.c ****
219:Core/Src/stm32f4xx_it.c **** /* USER CODE END EXTI0_IRQn 1 */
220:Core/Src/stm32f4xx_it.c **** }
270 .loc 1 220 1 is_stmt 0 view .LVU44
271 002a 08BD pop {r3, pc}
272 .L17:
212:Core/Src/stm32f4xx_it.c **** }
273 .loc 1 212 5 is_stmt 1 view .LVU45
212:Core/Src/stm32f4xx_it.c **** }
274 .loc 1 212 40 is_stmt 0 view .LVU46
275 002c 024B ldr r3, .L20+4
276 002e 0222 movs r2, #2
277 0030 1A71 strb r2, [r3, #4]
278 0032 F3E7 b .L18
279 .L21:
280 .align 2
281 .L20:
282 0034 00000000 .word hdma_adc1
283 0038 00000000 .word Sweep_state
284 .cfi_endproc
285 .LFE248:
287 .section .text.EXTI3_IRQHandler,"ax",%progbits
288 .align 1
289 .global EXTI3_IRQHandler
290 .syntax unified
291 .thumb
292 .thumb_func
294 EXTI3_IRQHandler:
295 .LFB249:
221:Core/Src/stm32f4xx_it.c ****
222:Core/Src/stm32f4xx_it.c **** /**
223:Core/Src/stm32f4xx_it.c **** * @brief This function handles EXTI line3 interrupt.
224:Core/Src/stm32f4xx_it.c **** */
225:Core/Src/stm32f4xx_it.c **** void EXTI3_IRQHandler(void)
226:Core/Src/stm32f4xx_it.c **** {
296 .loc 1 226 1 is_stmt 1 view -0
297 .cfi_startproc
298 @ args = 0, pretend = 0, frame = 0
299 @ frame_needed = 0, uses_anonymous_args = 0
300 0000 08B5 push {r3, lr}
301 .LCFI2:
ARM GAS /tmp/cceMYWsz.s page 10
302 .cfi_def_cfa_offset 8
303 .cfi_offset 3, -8
304 .cfi_offset 14, -4
227:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN EXTI3_IRQn 0 */
228:Core/Src/stm32f4xx_it.c **** Sweep_state.sweep_cycle_started_flag = 1; //sweep cycle started
305 .loc 1 228 3 view .LVU48
306 .loc 1 228 40 is_stmt 0 view .LVU49
307 0002 044B ldr r3, .L24
308 0004 0122 movs r2, #1
309 0006 1A73 strb r2, [r3, #12]
229:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_N = 0;
310 .loc 1 229 3 is_stmt 1 view .LVU50
311 .loc 1 229 27 is_stmt 0 view .LVU51
312 0008 0022 movs r2, #0
313 000a 1A60 str r2, [r3]
230:Core/Src/stm32f4xx_it.c **** /* USER CODE END EXTI3_IRQn 0 */
231:Core/Src/stm32f4xx_it.c **** HAL_GPIO_EXTI_IRQHandler(SWEEP_CYCLE_START_TRG_Pin);
314 .loc 1 231 3 is_stmt 1 view .LVU52
315 000c 0820 movs r0, #8
316 000e FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler
317 .LVL2:
232:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN EXTI3_IRQn 1 */
233:Core/Src/stm32f4xx_it.c ****
234:Core/Src/stm32f4xx_it.c **** /* USER CODE END EXTI3_IRQn 1 */
235:Core/Src/stm32f4xx_it.c **** }
318 .loc 1 235 1 is_stmt 0 view .LVU53
319 0012 08BD pop {r3, pc}
320 .L25:
321 .align 2
322 .L24:
323 0014 00000000 .word Sweep_state
324 .cfi_endproc
325 .LFE249:
327 .section .text.DMA2_Stream0_IRQHandler,"ax",%progbits
328 .align 1
329 .global DMA2_Stream0_IRQHandler
330 .syntax unified
331 .thumb
332 .thumb_func
334 DMA2_Stream0_IRQHandler:
335 .LFB250:
236:Core/Src/stm32f4xx_it.c ****
237:Core/Src/stm32f4xx_it.c **** /**
238:Core/Src/stm32f4xx_it.c **** * @brief This function handles DMA2 stream0 global interrupt.
239:Core/Src/stm32f4xx_it.c **** */
240:Core/Src/stm32f4xx_it.c **** void DMA2_Stream0_IRQHandler(void)
241:Core/Src/stm32f4xx_it.c **** {
336 .loc 1 241 1 is_stmt 1 view -0
337 .cfi_startproc
338 @ args = 0, pretend = 0, frame = 0
339 @ frame_needed = 0, uses_anonymous_args = 0
340 0000 08B5 push {r3, lr}
341 .LCFI3:
342 .cfi_def_cfa_offset 8
343 .cfi_offset 3, -8
344 .cfi_offset 14, -4
242:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN DMA2_Stream0_IRQn 0 */
ARM GAS /tmp/cceMYWsz.s page 11
243:Core/Src/stm32f4xx_it.c ****
244:Core/Src/stm32f4xx_it.c **** /* USER CODE END DMA2_Stream0_IRQn 0 */
245:Core/Src/stm32f4xx_it.c **** HAL_DMA_IRQHandler(&hdma_adc1);
345 .loc 1 245 3 view .LVU55
346 0002 0248 ldr r0, .L28
347 0004 FFF7FEFF bl HAL_DMA_IRQHandler
348 .LVL3:
246:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN DMA2_Stream0_IRQn 1 */
247:Core/Src/stm32f4xx_it.c ****
248:Core/Src/stm32f4xx_it.c **** /* USER CODE END DMA2_Stream0_IRQn 1 */
249:Core/Src/stm32f4xx_it.c **** }
349 .loc 1 249 1 is_stmt 0 view .LVU56
350 0008 08BD pop {r3, pc}
351 .L29:
352 000a 00BF .align 2
353 .L28:
354 000c 00000000 .word hdma_adc1
355 .cfi_endproc
356 .LFE250:
358 .section .text.OTG_FS_IRQHandler,"ax",%progbits
359 .align 1
360 .global OTG_FS_IRQHandler
361 .syntax unified
362 .thumb
363 .thumb_func
365 OTG_FS_IRQHandler:
366 .LFB251:
250:Core/Src/stm32f4xx_it.c ****
251:Core/Src/stm32f4xx_it.c **** /**
252:Core/Src/stm32f4xx_it.c **** * @brief This function handles USB On The Go FS global interrupt.
253:Core/Src/stm32f4xx_it.c **** */
254:Core/Src/stm32f4xx_it.c **** void OTG_FS_IRQHandler(void)
255:Core/Src/stm32f4xx_it.c **** {
367 .loc 1 255 1 is_stmt 1 view -0
368 .cfi_startproc
369 @ args = 0, pretend = 0, frame = 0
370 @ frame_needed = 0, uses_anonymous_args = 0
371 0000 08B5 push {r3, lr}
372 .LCFI4:
373 .cfi_def_cfa_offset 8
374 .cfi_offset 3, -8
375 .cfi_offset 14, -4
256:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN OTG_FS_IRQn 0 */
257:Core/Src/stm32f4xx_it.c ****
258:Core/Src/stm32f4xx_it.c **** /* USER CODE END OTG_FS_IRQn 0 */
259:Core/Src/stm32f4xx_it.c **** HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS);
376 .loc 1 259 3 view .LVU58
377 0002 0248 ldr r0, .L32
378 0004 FFF7FEFF bl HAL_PCD_IRQHandler
379 .LVL4:
260:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN OTG_FS_IRQn 1 */
261:Core/Src/stm32f4xx_it.c ****
262:Core/Src/stm32f4xx_it.c **** /* USER CODE END OTG_FS_IRQn 1 */
263:Core/Src/stm32f4xx_it.c **** }
380 .loc 1 263 1 is_stmt 0 view .LVU59
381 0008 08BD pop {r3, pc}
382 .L33:
ARM GAS /tmp/cceMYWsz.s page 12
383 000a 00BF .align 2
384 .L32:
385 000c 00000000 .word hpcd_USB_OTG_FS
386 .cfi_endproc
387 .LFE251:
389 .section .text.HAL_ADC_ConvCpltCallback,"ax",%progbits
390 .align 1
391 .global HAL_ADC_ConvCpltCallback
392 .syntax unified
393 .thumb
394 .thumb_func
396 HAL_ADC_ConvCpltCallback:
397 .LVL5:
398 .LFB252:
264:Core/Src/stm32f4xx_it.c ****
265:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN 1 */
266:Core/Src/stm32f4xx_it.c ****
267:Core/Src/stm32f4xx_it.c **** #ifdef SYNC_DET_ON
268:Core/Src/stm32f4xx_it.c ****
269:Core/Src/stm32f4xx_it.c ****
270:Core/Src/stm32f4xx_it.c ****
271:Core/Src/stm32f4xx_it.c ****
272:Core/Src/stm32f4xx_it.c **** void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
273:Core/Src/stm32f4xx_it.c **** {
399 .loc 1 273 1 is_stmt 1 view -0
400 .cfi_startproc
401 @ args = 0, pretend = 0, frame = 0
402 @ frame_needed = 0, uses_anonymous_args = 0
403 .loc 1 273 1 is_stmt 0 view .LVU61
404 0000 10B5 push {r4, lr}
405 .LCFI5:
406 .cfi_def_cfa_offset 8
407 .cfi_offset 4, -8
408 .cfi_offset 14, -4
274:Core/Src/stm32f4xx_it.c **** HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_SET);
409 .loc 1 274 3 is_stmt 1 view .LVU62
410 0002 0122 movs r2, #1
411 0004 8021 movs r1, #128
412 0006 5C48 ldr r0, .L55
413 .LVL6:
414 .loc 1 274 3 is_stmt 0 view .LVU63
415 0008 FFF7FEFF bl HAL_GPIO_WritePin
416 .LVL7:
275:Core/Src/stm32f4xx_it.c ****
276:Core/Src/stm32f4xx_it.c **** if (Sweep_state.curr_step_started_flag == 2) {
417 .loc 1 276 3 is_stmt 1 view .LVU64
418 .loc 1 276 18 is_stmt 0 view .LVU65
419 000c 5B4B ldr r3, .L55+4
420 000e 1B79 ldrb r3, [r3, #4] @ zero_extendqisi2
421 0010 DBB2 uxtb r3, r3
422 .loc 1 276 6 view .LVU66
423 0012 022B cmp r3, #2
424 0014 01D0 beq .L51
425 .LBB2:
277:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag = 0; // reset flag after processing second half
278:Core/Src/stm32f4xx_it.c **** for (uint32_t i = ADC_BUFF_SIZE/2; i < Sweep_state.curr_step_start_DMA_N; i++) {
279:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
ARM GAS /tmp/cceMYWsz.s page 13
280:Core/Src/stm32f4xx_it.c **** uint32_t s = sample_seq++;
281:Core/Src/stm32f4xx_it.c **** if ((s & 1) != 0) { ADC_proc.sum_ON += v; ADC_proc.N_on++; } else { ADC_proc.sum_OFF += v; AD
282:Core/Src/stm32f4xx_it.c **** }
283:Core/Src/stm32f4xx_it.c ****
284:Core/Src/stm32f4xx_it.c **** ADC_proc.N += (Sweep_state.curr_step_start_DMA_N - ADC_BUFF_SIZE/2)/2;
285:Core/Src/stm32f4xx_it.c ****
286:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_ON = ADC_proc.sum_ON;
287:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
288:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
289:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
290:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
291:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N_on = ADC_proc.N_on;
292:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N_off = ADC_proc.N_off;
293:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
294:Core/Src/stm32f4xx_it.c ****
295:Core/Src/stm32f4xx_it.c ****
296:Core/Src/stm32f4xx_it.c **** ADC_proc.sum = 0;
297:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON = 0;
298:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF = 0;
299:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0;
300:Core/Src/stm32f4xx_it.c **** ADC_proc.N_on = 0;
301:Core/Src/stm32f4xx_it.c **** ADC_proc.N_off = 0;
302:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_ON = 0;
303:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_OFF = 0;
304:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data
305:Core/Src/stm32f4xx_it.c ****
306:Core/Src/stm32f4xx_it.c **** for (uint32_t i = Sweep_state.curr_step_start_DMA_N; i < ADC_BUFF_SIZE; i++) {
307:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
308:Core/Src/stm32f4xx_it.c **** uint32_t s = sample_seq++;
309:Core/Src/stm32f4xx_it.c **** if ((s & 1) != 0) { ADC_proc.sum_ON += v; ADC_proc.N_on++; } else { ADC_proc.sum_OFF += v; AD
310:Core/Src/stm32f4xx_it.c **** }
311:Core/Src/stm32f4xx_it.c **** ADC_proc.N = (ADC_BUFF_SIZE - Sweep_state.curr_step_start_DMA_N)/2;
312:Core/Src/stm32f4xx_it.c ****
313:Core/Src/stm32f4xx_it.c ****
314:Core/Src/stm32f4xx_it.c **** }else{
315:Core/Src/stm32f4xx_it.c **** for (uint32_t i = ADC_BUFF_SIZE/2; i < ADC_BUFF_SIZE; i++) {
426 .loc 1 315 19 view .LVU67
427 0016 2023 movs r3, #32
428 0018 74E0 b .L35
429 .L51:
430 .LBE2:
277:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag = 0; // reset flag after processing second half
431 .loc 1 277 5 is_stmt 1 view .LVU68
277:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag = 0; // reset flag after processing second half
432 .loc 1 277 40 is_stmt 0 view .LVU69
433 001a 584B ldr r3, .L55+4
434 001c 0022 movs r2, #0
435 001e 1A71 strb r2, [r3, #4]
278:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
436 .loc 1 278 5 is_stmt 1 view .LVU70
437 .LBB5:
278:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
438 .loc 1 278 10 view .LVU71
439 .LVL8:
278:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
440 .loc 1 278 19 is_stmt 0 view .LVU72
441 0020 2023 movs r3, #32
ARM GAS /tmp/cceMYWsz.s page 14
278:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
442 .loc 1 278 5 view .LVU73
443 0022 07E0 b .L36
444 .LVL9:
445 .L37:
446 .LBB6:
281:Core/Src/stm32f4xx_it.c **** }
447 .loc 1 281 75 is_stmt 1 discriminator 2 view .LVU74
281:Core/Src/stm32f4xx_it.c **** }
448 .loc 1 281 83 is_stmt 0 discriminator 2 view .LVU75
449 0024 5649 ldr r1, .L55+8
450 .LVL10:
281:Core/Src/stm32f4xx_it.c **** }
451 .loc 1 281 83 discriminator 2 view .LVU76
452 0026 C868 ldr r0, [r1, #12]
281:Core/Src/stm32f4xx_it.c **** }
453 .loc 1 281 92 discriminator 2 view .LVU77
454 0028 0244 add r2, r2, r0
455 .LVL11:
281:Core/Src/stm32f4xx_it.c **** }
456 .loc 1 281 92 discriminator 2 view .LVU78
457 002a CA60 str r2, [r1, #12]
281:Core/Src/stm32f4xx_it.c **** }
458 .loc 1 281 98 is_stmt 1 discriminator 2 view .LVU79
281:Core/Src/stm32f4xx_it.c **** }
459 .loc 1 281 106 is_stmt 0 discriminator 2 view .LVU80
460 002c 0A6A ldr r2, [r1, #32]
281:Core/Src/stm32f4xx_it.c **** }
461 .loc 1 281 112 discriminator 2 view .LVU81
462 002e 0132 adds r2, r2, #1
463 0030 0A62 str r2, [r1, #32]
464 .L38:
281:Core/Src/stm32f4xx_it.c **** }
465 .loc 1 281 112 discriminator 2 view .LVU82
466 .LBE6:
278:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
467 .loc 1 278 80 is_stmt 1 discriminator 2 view .LVU83
468 0032 0133 adds r3, r3, #1
469 .LVL12:
470 .L36:
278:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
471 .loc 1 278 42 discriminator 1 view .LVU84
278:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
472 .loc 1 278 55 is_stmt 0 discriminator 1 view .LVU85
473 0034 514A ldr r2, .L55+4
474 0036 9268 ldr r2, [r2, #8]
278:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
475 .loc 1 278 42 discriminator 1 view .LVU86
476 0038 9A42 cmp r2, r3
477 003a 11D9 bls .L52
478 .LBB7:
279:Core/Src/stm32f4xx_it.c **** uint32_t s = sample_seq++;
479 .loc 1 279 7 is_stmt 1 view .LVU87
279:Core/Src/stm32f4xx_it.c **** uint32_t s = sample_seq++;
480 .loc 1 279 16 is_stmt 0 view .LVU88
481 003c 514A ldr r2, .L55+12
482 003e 32F81320 ldrh r2, [r2, r3, lsl #1]
ARM GAS /tmp/cceMYWsz.s page 15
483 .LVL13:
280:Core/Src/stm32f4xx_it.c **** if ((s & 1) != 0) { ADC_proc.sum_ON += v; ADC_proc.N_on++; } else { ADC_proc.sum_OFF += v; AD
484 .loc 1 280 7 is_stmt 1 view .LVU89
280:Core/Src/stm32f4xx_it.c **** if ((s & 1) != 0) { ADC_proc.sum_ON += v; ADC_proc.N_on++; } else { ADC_proc.sum_OFF += v; AD
485 .loc 1 280 30 is_stmt 0 view .LVU90
486 0042 5148 ldr r0, .L55+16
487 0044 0168 ldr r1, [r0]
488 0046 4C1C adds r4, r1, #1
489 0048 0460 str r4, [r0]
490 .LVL14:
281:Core/Src/stm32f4xx_it.c **** }
491 .loc 1 281 7 is_stmt 1 view .LVU91
281:Core/Src/stm32f4xx_it.c **** }
492 .loc 1 281 10 is_stmt 0 view .LVU92
493 004a 11F0010F tst r1, #1
494 004e E9D0 beq .L37
281:Core/Src/stm32f4xx_it.c **** }
495 .loc 1 281 27 is_stmt 1 discriminator 1 view .LVU93
281:Core/Src/stm32f4xx_it.c **** }
496 .loc 1 281 35 is_stmt 0 discriminator 1 view .LVU94
497 0050 4B49 ldr r1, .L55+8
498 .LVL15:
281:Core/Src/stm32f4xx_it.c **** }
499 .loc 1 281 35 discriminator 1 view .LVU95
500 0052 8868 ldr r0, [r1, #8]
281:Core/Src/stm32f4xx_it.c **** }
501 .loc 1 281 43 discriminator 1 view .LVU96
502 0054 0244 add r2, r2, r0
503 .LVL16:
281:Core/Src/stm32f4xx_it.c **** }
504 .loc 1 281 43 discriminator 1 view .LVU97
505 0056 8A60 str r2, [r1, #8]
281:Core/Src/stm32f4xx_it.c **** }
506 .loc 1 281 49 is_stmt 1 discriminator 1 view .LVU98
281:Core/Src/stm32f4xx_it.c **** }
507 .loc 1 281 57 is_stmt 0 discriminator 1 view .LVU99
508 0058 CA69 ldr r2, [r1, #28]
281:Core/Src/stm32f4xx_it.c **** }
509 .loc 1 281 62 discriminator 1 view .LVU100
510 005a 0132 adds r2, r2, #1
511 005c CA61 str r2, [r1, #28]
512 005e E8E7 b .L38
513 .LVL17:
514 .L52:
281:Core/Src/stm32f4xx_it.c **** }
515 .loc 1 281 62 discriminator 1 view .LVU101
516 .LBE7:
517 .LBE5:
284:Core/Src/stm32f4xx_it.c ****
518 .loc 1 284 5 is_stmt 1 view .LVU102
284:Core/Src/stm32f4xx_it.c ****
519 .loc 1 284 31 is_stmt 0 view .LVU103
520 0060 4648 ldr r0, .L55+4
521 0062 8168 ldr r1, [r0, #8]
284:Core/Src/stm32f4xx_it.c ****
522 .loc 1 284 54 view .LVU104
523 0064 2039 subs r1, r1, #32
ARM GAS /tmp/cceMYWsz.s page 16
284:Core/Src/stm32f4xx_it.c ****
524 .loc 1 284 13 view .LVU105
525 0066 464B ldr r3, .L55+8
526 .LVL18:
284:Core/Src/stm32f4xx_it.c ****
527 .loc 1 284 13 view .LVU106
528 0068 9A69 ldr r2, [r3, #24]
284:Core/Src/stm32f4xx_it.c ****
529 .loc 1 284 16 view .LVU107
530 006a 02EB5102 add r2, r2, r1, lsr #1
531 006e 9A61 str r2, [r3, #24]
286:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
532 .loc 1 286 5 is_stmt 1 view .LVU108
286:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
533 .loc 1 286 38 is_stmt 0 view .LVU109
534 0070 9968 ldr r1, [r3, #8]
286:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
535 .loc 1 286 28 view .LVU110
536 0072 464A ldr r2, .L55+20
537 0074 9160 str r1, [r2, #8]
287:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
538 .loc 1 287 5 is_stmt 1 view .LVU111
287:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
539 .loc 1 287 39 is_stmt 0 view .LVU112
540 0076 D968 ldr r1, [r3, #12]
287:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
541 .loc 1 287 29 view .LVU113
542 0078 D160 str r1, [r2, #12]
288:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
543 .loc 1 288 5 is_stmt 1 view .LVU114
288:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
544 .loc 1 288 38 is_stmt 0 view .LVU115
545 007a 1969 ldr r1, [r3, #16]
288:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
546 .loc 1 288 28 view .LVU116
547 007c 1161 str r1, [r2, #16]
289:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
548 .loc 1 289 5 is_stmt 1 view .LVU117
289:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
549 .loc 1 289 39 is_stmt 0 view .LVU118
550 007e 5969 ldr r1, [r3, #20]
289:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
551 .loc 1 289 29 view .LVU119
552 0080 5161 str r1, [r2, #20]
290:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N_on = ADC_proc.N_on;
553 .loc 1 290 5 is_stmt 1 view .LVU120
290:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N_on = ADC_proc.N_on;
554 .loc 1 290 33 is_stmt 0 view .LVU121
555 0082 9969 ldr r1, [r3, #24]
290:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N_on = ADC_proc.N_on;
556 .loc 1 290 23 view .LVU122
557 0084 9161 str r1, [r2, #24]
291:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N_off = ADC_proc.N_off;
558 .loc 1 291 5 is_stmt 1 view .LVU123
291:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N_off = ADC_proc.N_off;
559 .loc 1 291 36 is_stmt 0 view .LVU124
560 0086 D969 ldr r1, [r3, #28]
ARM GAS /tmp/cceMYWsz.s page 17
291:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N_off = ADC_proc.N_off;
561 .loc 1 291 26 view .LVU125
562 0088 D161 str r1, [r2, #28]
292:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
563 .loc 1 292 5 is_stmt 1 view .LVU126
292:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
564 .loc 1 292 37 is_stmt 0 view .LVU127
565 008a 196A ldr r1, [r3, #32]
292:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
566 .loc 1 292 27 view .LVU128
567 008c 1162 str r1, [r2, #32]
293:Core/Src/stm32f4xx_it.c ****
568 .loc 1 293 5 is_stmt 1 view .LVU129
293:Core/Src/stm32f4xx_it.c ****
569 .loc 1 293 28 is_stmt 0 view .LVU130
570 008e 0221 movs r1, #2
571 0090 1170 strb r1, [r2]
296:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON = 0;
572 .loc 1 296 5 is_stmt 1 view .LVU131
296:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON = 0;
573 .loc 1 296 18 is_stmt 0 view .LVU132
574 0092 0022 movs r2, #0
575 0094 5A60 str r2, [r3, #4]
297:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF = 0;
576 .loc 1 297 5 is_stmt 1 view .LVU133
297:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF = 0;
577 .loc 1 297 21 is_stmt 0 view .LVU134
578 0096 9A60 str r2, [r3, #8]
298:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0;
579 .loc 1 298 5 is_stmt 1 view .LVU135
298:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0;
580 .loc 1 298 22 is_stmt 0 view .LVU136
581 0098 DA60 str r2, [r3, #12]
299:Core/Src/stm32f4xx_it.c **** ADC_proc.N_on = 0;
582 .loc 1 299 5 is_stmt 1 view .LVU137
299:Core/Src/stm32f4xx_it.c **** ADC_proc.N_on = 0;
583 .loc 1 299 16 is_stmt 0 view .LVU138
584 009a 9A61 str r2, [r3, #24]
300:Core/Src/stm32f4xx_it.c **** ADC_proc.N_off = 0;
585 .loc 1 300 5 is_stmt 1 view .LVU139
300:Core/Src/stm32f4xx_it.c **** ADC_proc.N_off = 0;
586 .loc 1 300 19 is_stmt 0 view .LVU140
587 009c DA61 str r2, [r3, #28]
301:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_ON = 0;
588 .loc 1 301 5 is_stmt 1 view .LVU141
301:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_ON = 0;
589 .loc 1 301 20 is_stmt 0 view .LVU142
590 009e 1A62 str r2, [r3, #32]
302:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_OFF = 0;
591 .loc 1 302 5 is_stmt 1 view .LVU143
302:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_OFF = 0;
592 .loc 1 302 21 is_stmt 0 view .LVU144
593 00a0 1A61 str r2, [r3, #16]
303:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data
594 .loc 1 303 5 is_stmt 1 view .LVU145
303:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data
595 .loc 1 303 22 is_stmt 0 view .LVU146
ARM GAS /tmp/cceMYWsz.s page 18
596 00a2 5A61 str r2, [r3, #20]
304:Core/Src/stm32f4xx_it.c ****
597 .loc 1 304 5 is_stmt 1 view .LVU147
304:Core/Src/stm32f4xx_it.c ****
598 .loc 1 304 21 is_stmt 0 view .LVU148
599 00a4 0122 movs r2, #1
600 00a6 1A70 strb r2, [r3]
306:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
601 .loc 1 306 5 is_stmt 1 view .LVU149
602 .LBB8:
306:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
603 .loc 1 306 10 view .LVU150
306:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
604 .loc 1 306 19 is_stmt 0 view .LVU151
605 00a8 8368 ldr r3, [r0, #8]
606 .LVL19:
306:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
607 .loc 1 306 5 view .LVU152
608 00aa 07E0 b .L40
609 .LVL20:
610 .L41:
611 .LBB9:
309:Core/Src/stm32f4xx_it.c **** }
612 .loc 1 309 75 is_stmt 1 discriminator 2 view .LVU153
309:Core/Src/stm32f4xx_it.c **** }
613 .loc 1 309 83 is_stmt 0 discriminator 2 view .LVU154
614 00ac 3449 ldr r1, .L55+8
615 .LVL21:
309:Core/Src/stm32f4xx_it.c **** }
616 .loc 1 309 83 discriminator 2 view .LVU155
617 00ae C868 ldr r0, [r1, #12]
309:Core/Src/stm32f4xx_it.c **** }
618 .loc 1 309 92 discriminator 2 view .LVU156
619 00b0 0244 add r2, r2, r0
620 .LVL22:
309:Core/Src/stm32f4xx_it.c **** }
621 .loc 1 309 92 discriminator 2 view .LVU157
622 00b2 CA60 str r2, [r1, #12]
309:Core/Src/stm32f4xx_it.c **** }
623 .loc 1 309 98 is_stmt 1 discriminator 2 view .LVU158
309:Core/Src/stm32f4xx_it.c **** }
624 .loc 1 309 106 is_stmt 0 discriminator 2 view .LVU159
625 00b4 0A6A ldr r2, [r1, #32]
309:Core/Src/stm32f4xx_it.c **** }
626 .loc 1 309 112 discriminator 2 view .LVU160
627 00b6 0132 adds r2, r2, #1
628 00b8 0A62 str r2, [r1, #32]
629 .L42:
309:Core/Src/stm32f4xx_it.c **** }
630 .loc 1 309 112 discriminator 2 view .LVU161
631 .LBE9:
306:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
632 .loc 1 306 78 is_stmt 1 discriminator 2 view .LVU162
633 00ba 0133 adds r3, r3, #1
634 .LVL23:
635 .L40:
306:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
ARM GAS /tmp/cceMYWsz.s page 19
636 .loc 1 306 60 discriminator 1 view .LVU163
637 00bc 3F2B cmp r3, #63
638 00be 11D8 bhi .L53
639 .LBB10:
307:Core/Src/stm32f4xx_it.c **** uint32_t s = sample_seq++;
640 .loc 1 307 7 view .LVU164
307:Core/Src/stm32f4xx_it.c **** uint32_t s = sample_seq++;
641 .loc 1 307 16 is_stmt 0 view .LVU165
642 00c0 304A ldr r2, .L55+12
643 00c2 32F81320 ldrh r2, [r2, r3, lsl #1]
644 .LVL24:
308:Core/Src/stm32f4xx_it.c **** if ((s & 1) != 0) { ADC_proc.sum_ON += v; ADC_proc.N_on++; } else { ADC_proc.sum_OFF += v; AD
645 .loc 1 308 7 is_stmt 1 view .LVU166
308:Core/Src/stm32f4xx_it.c **** if ((s & 1) != 0) { ADC_proc.sum_ON += v; ADC_proc.N_on++; } else { ADC_proc.sum_OFF += v; AD
646 .loc 1 308 30 is_stmt 0 view .LVU167
647 00c6 3048 ldr r0, .L55+16
648 00c8 0168 ldr r1, [r0]
649 00ca 4C1C adds r4, r1, #1
650 00cc 0460 str r4, [r0]
651 .LVL25:
309:Core/Src/stm32f4xx_it.c **** }
652 .loc 1 309 7 is_stmt 1 view .LVU168
309:Core/Src/stm32f4xx_it.c **** }
653 .loc 1 309 10 is_stmt 0 view .LVU169
654 00ce 11F0010F tst r1, #1
655 00d2 EBD0 beq .L41
309:Core/Src/stm32f4xx_it.c **** }
656 .loc 1 309 27 is_stmt 1 discriminator 1 view .LVU170
309:Core/Src/stm32f4xx_it.c **** }
657 .loc 1 309 35 is_stmt 0 discriminator 1 view .LVU171
658 00d4 2A49 ldr r1, .L55+8
659 .LVL26:
309:Core/Src/stm32f4xx_it.c **** }
660 .loc 1 309 35 discriminator 1 view .LVU172
661 00d6 8868 ldr r0, [r1, #8]
309:Core/Src/stm32f4xx_it.c **** }
662 .loc 1 309 43 discriminator 1 view .LVU173
663 00d8 0244 add r2, r2, r0
664 .LVL27:
309:Core/Src/stm32f4xx_it.c **** }
665 .loc 1 309 43 discriminator 1 view .LVU174
666 00da 8A60 str r2, [r1, #8]
309:Core/Src/stm32f4xx_it.c **** }
667 .loc 1 309 49 is_stmt 1 discriminator 1 view .LVU175
309:Core/Src/stm32f4xx_it.c **** }
668 .loc 1 309 57 is_stmt 0 discriminator 1 view .LVU176
669 00dc CA69 ldr r2, [r1, #28]
309:Core/Src/stm32f4xx_it.c **** }
670 .loc 1 309 62 discriminator 1 view .LVU177
671 00de 0132 adds r2, r2, #1
672 00e0 CA61 str r2, [r1, #28]
673 00e2 EAE7 b .L42
674 .LVL28:
675 .L53:
309:Core/Src/stm32f4xx_it.c **** }
676 .loc 1 309 62 discriminator 1 view .LVU178
677 .LBE10:
ARM GAS /tmp/cceMYWsz.s page 20
678 .LBE8:
311:Core/Src/stm32f4xx_it.c ****
679 .loc 1 311 5 is_stmt 1 view .LVU179
311:Core/Src/stm32f4xx_it.c ****
680 .loc 1 311 46 is_stmt 0 view .LVU180
681 00e4 254B ldr r3, .L55+4
682 .LVL29:
311:Core/Src/stm32f4xx_it.c ****
683 .loc 1 311 46 view .LVU181
684 00e6 9B68 ldr r3, [r3, #8]
311:Core/Src/stm32f4xx_it.c ****
685 .loc 1 311 33 view .LVU182
686 00e8 C3F14003 rsb r3, r3, #64
311:Core/Src/stm32f4xx_it.c ****
687 .loc 1 311 69 view .LVU183
688 00ec 5B08 lsrs r3, r3, #1
311:Core/Src/stm32f4xx_it.c ****
689 .loc 1 311 16 view .LVU184
690 00ee 244A ldr r2, .L55+8
691 00f0 9361 str r3, [r2, #24]
692 00f2 1FE0 b .L44
693 .LVL30:
694 .L45:
695 .LBB11:
696 .LBB3:
316:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
317:Core/Src/stm32f4xx_it.c **** uint32_t s = sample_seq++;
318:Core/Src/stm32f4xx_it.c **** if ((s & 1) != 0) { ADC_proc.sum_ON += v; ADC_proc.N_on++; } else { ADC_proc.sum_OFF += v; AD
697 .loc 1 318 75 is_stmt 1 discriminator 2 view .LVU185
698 .loc 1 318 83 is_stmt 0 discriminator 2 view .LVU186
699 00f4 2249 ldr r1, .L55+8
700 .LVL31:
701 .loc 1 318 83 discriminator 2 view .LVU187
702 00f6 C868 ldr r0, [r1, #12]
703 .loc 1 318 92 discriminator 2 view .LVU188
704 00f8 0244 add r2, r2, r0
705 .LVL32:
706 .loc 1 318 92 discriminator 2 view .LVU189
707 00fa CA60 str r2, [r1, #12]
708 .loc 1 318 98 is_stmt 1 discriminator 2 view .LVU190
709 .loc 1 318 106 is_stmt 0 discriminator 2 view .LVU191
710 00fc 0A6A ldr r2, [r1, #32]
711 .loc 1 318 112 discriminator 2 view .LVU192
712 00fe 0132 adds r2, r2, #1
713 0100 0A62 str r2, [r1, #32]
714 .L46:
715 .loc 1 318 112 discriminator 2 view .LVU193
716 .LBE3:
315:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
717 .loc 1 315 60 is_stmt 1 discriminator 2 view .LVU194
718 0102 0133 adds r3, r3, #1
719 .LVL33:
720 .L35:
315:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
721 .loc 1 315 42 discriminator 1 view .LVU195
722 0104 3F2B cmp r3, #63
723 0106 11D8 bhi .L54
ARM GAS /tmp/cceMYWsz.s page 21
724 .LBB4:
316:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
725 .loc 1 316 7 view .LVU196
316:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
726 .loc 1 316 16 is_stmt 0 view .LVU197
727 0108 1E4A ldr r2, .L55+12
728 010a 32F81320 ldrh r2, [r2, r3, lsl #1]
729 .LVL34:
317:Core/Src/stm32f4xx_it.c **** if ((s & 1) != 0) { ADC_proc.sum_ON += v; ADC_proc.N_on++; } else { ADC_proc.sum_OFF += v; AD
730 .loc 1 317 7 is_stmt 1 view .LVU198
317:Core/Src/stm32f4xx_it.c **** if ((s & 1) != 0) { ADC_proc.sum_ON += v; ADC_proc.N_on++; } else { ADC_proc.sum_OFF += v; AD
731 .loc 1 317 30 is_stmt 0 view .LVU199
732 010e 1E48 ldr r0, .L55+16
733 0110 0168 ldr r1, [r0]
734 0112 4C1C adds r4, r1, #1
735 0114 0460 str r4, [r0]
736 .LVL35:
737 .loc 1 318 7 is_stmt 1 view .LVU200
738 .loc 1 318 10 is_stmt 0 view .LVU201
739 0116 11F0010F tst r1, #1
740 011a EBD0 beq .L45
741 .loc 1 318 27 is_stmt 1 discriminator 1 view .LVU202
742 .loc 1 318 35 is_stmt 0 discriminator 1 view .LVU203
743 011c 1849 ldr r1, .L55+8
744 .LVL36:
745 .loc 1 318 35 discriminator 1 view .LVU204
746 011e 8868 ldr r0, [r1, #8]
747 .loc 1 318 43 discriminator 1 view .LVU205
748 0120 0244 add r2, r2, r0
749 .LVL37:
750 .loc 1 318 43 discriminator 1 view .LVU206
751 0122 8A60 str r2, [r1, #8]
752 .loc 1 318 49 is_stmt 1 discriminator 1 view .LVU207
753 .loc 1 318 57 is_stmt 0 discriminator 1 view .LVU208
754 0124 CA69 ldr r2, [r1, #28]
755 .loc 1 318 62 discriminator 1 view .LVU209
756 0126 0132 adds r2, r2, #1
757 0128 CA61 str r2, [r1, #28]
758 012a EAE7 b .L46
759 .LVL38:
760 .L54:
761 .loc 1 318 62 discriminator 1 view .LVU210
762 .LBE4:
763 .LBE11:
319:Core/Src/stm32f4xx_it.c **** }
320:Core/Src/stm32f4xx_it.c **** ADC_proc.N += (ADC_BUFF_SIZE - ADC_BUFF_SIZE/2)/2;
764 .loc 1 320 5 is_stmt 1 view .LVU211
765 .loc 1 320 13 is_stmt 0 view .LVU212
766 012c 144A ldr r2, .L55+8
767 012e 9369 ldr r3, [r2, #24]
768 .LVL39:
769 .loc 1 320 16 view .LVU213
770 0130 1033 adds r3, r3, #16
771 0132 9361 str r3, [r2, #24]
772 .LVL40:
773 .L44:
321:Core/Src/stm32f4xx_it.c **** }
ARM GAS /tmp/cceMYWsz.s page 22
322:Core/Src/stm32f4xx_it.c ****
323:Core/Src/stm32f4xx_it.c **** //if (0){
324:Core/Src/stm32f4xx_it.c **** if (ADC_proc.N >= ADC_BUFF_SIZE*100){
774 .loc 1 324 3 is_stmt 1 view .LVU214
775 .loc 1 324 15 is_stmt 0 view .LVU215
776 0134 124B ldr r3, .L55+8
777 0136 9B69 ldr r3, [r3, #24]
778 .loc 1 324 6 view .LVU216
779 0138 B3F5C85F cmp r3, #6400
780 013c 1BD3 bcc .L34
325:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
781 .loc 1 325 5 is_stmt 1 view .LVU217
782 .loc 1 325 39 is_stmt 0 view .LVU218
783 013e 104B ldr r3, .L55+8
784 0140 D968 ldr r1, [r3, #12]
785 .loc 1 325 29 view .LVU219
786 0142 124A ldr r2, .L55+20
787 0144 D160 str r1, [r2, #12]
326:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_ON = ADC_proc.sum_ON;
788 .loc 1 326 5 is_stmt 1 view .LVU220
789 .loc 1 326 38 is_stmt 0 view .LVU221
790 0146 9968 ldr r1, [r3, #8]
791 .loc 1 326 28 view .LVU222
792 0148 9160 str r1, [r2, #8]
327:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
793 .loc 1 327 5 is_stmt 1 view .LVU223
794 .loc 1 327 38 is_stmt 0 view .LVU224
795 014a 1969 ldr r1, [r3, #16]
796 .loc 1 327 28 view .LVU225
797 014c 1161 str r1, [r2, #16]
328:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
798 .loc 1 328 5 is_stmt 1 view .LVU226
799 .loc 1 328 39 is_stmt 0 view .LVU227
800 014e 5969 ldr r1, [r3, #20]
801 .loc 1 328 29 view .LVU228
802 0150 5161 str r1, [r2, #20]
329:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
803 .loc 1 329 5 is_stmt 1 view .LVU229
804 .loc 1 329 33 is_stmt 0 view .LVU230
805 0152 9969 ldr r1, [r3, #24]
806 .loc 1 329 23 view .LVU231
807 0154 9161 str r1, [r2, #24]
330:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N_on = ADC_proc.N_on;
808 .loc 1 330 5 is_stmt 1 view .LVU232
809 .loc 1 330 36 is_stmt 0 view .LVU233
810 0156 D969 ldr r1, [r3, #28]
811 .loc 1 330 26 view .LVU234
812 0158 D161 str r1, [r2, #28]
331:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N_off = ADC_proc.N_off;
813 .loc 1 331 5 is_stmt 1 view .LVU235
814 .loc 1 331 37 is_stmt 0 view .LVU236
815 015a 196A ldr r1, [r3, #32]
816 .loc 1 331 27 view .LVU237
817 015c 1162 str r1, [r2, #32]
332:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
818 .loc 1 332 5 is_stmt 1 view .LVU238
819 .loc 1 332 28 is_stmt 0 view .LVU239
ARM GAS /tmp/cceMYWsz.s page 23
820 015e 0221 movs r1, #2
821 0160 1170 strb r1, [r2]
333:Core/Src/stm32f4xx_it.c ****
334:Core/Src/stm32f4xx_it.c ****
335:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF = 0;
822 .loc 1 335 5 is_stmt 1 view .LVU240
823 .loc 1 335 22 is_stmt 0 view .LVU241
824 0162 0022 movs r2, #0
825 0164 DA60 str r2, [r3, #12]
336:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON = 0;
826 .loc 1 336 5 is_stmt 1 view .LVU242
827 .loc 1 336 21 is_stmt 0 view .LVU243
828 0166 9A60 str r2, [r3, #8]
337:Core/Src/stm32f4xx_it.c ****
338:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0;
829 .loc 1 338 5 is_stmt 1 view .LVU244
830 .loc 1 338 16 is_stmt 0 view .LVU245
831 0168 9A61 str r2, [r3, #24]
339:Core/Src/stm32f4xx_it.c **** ADC_proc.N_on = 0;
832 .loc 1 339 5 is_stmt 1 view .LVU246
833 .loc 1 339 19 is_stmt 0 view .LVU247
834 016a DA61 str r2, [r3, #28]
340:Core/Src/stm32f4xx_it.c **** ADC_proc.N_off = 0;
835 .loc 1 340 5 is_stmt 1 view .LVU248
836 .loc 1 340 20 is_stmt 0 view .LVU249
837 016c 1A62 str r2, [r3, #32]
341:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_ON = 0;
838 .loc 1 341 5 is_stmt 1 view .LVU250
839 .loc 1 341 21 is_stmt 0 view .LVU251
840 016e 1A61 str r2, [r3, #16]
342:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_OFF = 0;
841 .loc 1 342 5 is_stmt 1 view .LVU252
842 .loc 1 342 22 is_stmt 0 view .LVU253
843 0170 5A61 str r2, [r3, #20]
343:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data
844 .loc 1 343 5 is_stmt 1 view .LVU254
845 .loc 1 343 21 is_stmt 0 view .LVU255
846 0172 0122 movs r2, #1
847 0174 1A70 strb r2, [r3]
848 .L34:
344:Core/Src/stm32f4xx_it.c **** }
345:Core/Src/stm32f4xx_it.c **** // This function is called when the first half of the ADC buffer is filled
346:Core/Src/stm32f4xx_it.c **** // You can process the first half of ADC1_buff_circular here
347:Core/Src/stm32f4xx_it.c **** }
849 .loc 1 347 1 view .LVU256
850 0176 10BD pop {r4, pc}
851 .L56:
852 .align 2
853 .L55:
854 0178 00040240 .word 1073873920
855 017c 00000000 .word Sweep_state
856 0180 00000000 .word ADC_proc
857 0184 00000000 .word ADC1_buff_circular
858 0188 00000000 .word sample_seq
859 018c 00000000 .word ADC_proc_shadow
860 .cfi_endproc
861 .LFE252:
ARM GAS /tmp/cceMYWsz.s page 24
863 .section .text.HAL_ADC_ConvHalfCpltCallback,"ax",%progbits
864 .align 1
865 .global HAL_ADC_ConvHalfCpltCallback
866 .syntax unified
867 .thumb
868 .thumb_func
870 HAL_ADC_ConvHalfCpltCallback:
871 .LVL41:
872 .LFB253:
348:Core/Src/stm32f4xx_it.c ****
349:Core/Src/stm32f4xx_it.c **** void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
350:Core/Src/stm32f4xx_it.c **** {
873 .loc 1 350 1 is_stmt 1 view -0
874 .cfi_startproc
875 @ args = 0, pretend = 0, frame = 0
876 @ frame_needed = 0, uses_anonymous_args = 0
877 .loc 1 350 1 is_stmt 0 view .LVU258
878 0000 10B5 push {r4, lr}
879 .LCFI6:
880 .cfi_def_cfa_offset 8
881 .cfi_offset 4, -8
882 .cfi_offset 14, -4
351:Core/Src/stm32f4xx_it.c **** //HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_RESET);
352:Core/Src/stm32f4xx_it.c ****
353:Core/Src/stm32f4xx_it.c **** HAL_GPIO_TogglePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin);
883 .loc 1 353 3 is_stmt 1 view .LVU259
884 0002 8021 movs r1, #128
885 0004 4A48 ldr r0, .L77
886 .LVL42:
887 .loc 1 353 3 is_stmt 0 view .LVU260
888 0006 FFF7FEFF bl HAL_GPIO_TogglePin
889 .LVL43:
354:Core/Src/stm32f4xx_it.c **** if (Sweep_state.curr_step_started_flag == 1) {
890 .loc 1 354 3 is_stmt 1 view .LVU261
891 .loc 1 354 18 is_stmt 0 view .LVU262
892 000a 4A4B ldr r3, .L77+4
893 000c 1B79 ldrb r3, [r3, #4] @ zero_extendqisi2
894 000e DBB2 uxtb r3, r3
895 .loc 1 354 6 view .LVU263
896 0010 012B cmp r3, #1
897 0012 01D0 beq .L73
898 .LBB12:
355:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag = 0;
356:Core/Src/stm32f4xx_it.c **** for (uint32_t i = 0; i < Sweep_state.curr_step_start_DMA_N; i++) {
357:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
358:Core/Src/stm32f4xx_it.c **** uint32_t s = sample_seq++;
359:Core/Src/stm32f4xx_it.c **** if ((s & 1) != 0) { ADC_proc.sum_ON += v; ADC_proc.N_on++; } else { ADC_proc.sum_OFF += v; AD
360:Core/Src/stm32f4xx_it.c **** }
361:Core/Src/stm32f4xx_it.c ****
362:Core/Src/stm32f4xx_it.c **** ADC_proc.N += (Sweep_state.curr_step_start_DMA_N)/2;
363:Core/Src/stm32f4xx_it.c ****
364:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_ON = ADC_proc.sum_ON;
365:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
366:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
367:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
368:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
369:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N_on = ADC_proc.N_on;
ARM GAS /tmp/cceMYWsz.s page 25
370:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N_off = ADC_proc.N_off;
371:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
372:Core/Src/stm32f4xx_it.c ****
373:Core/Src/stm32f4xx_it.c ****
374:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_ON = 0;
375:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF = 0;
376:Core/Src/stm32f4xx_it.c **** ADC_proc.sum = 0;
377:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0;
378:Core/Src/stm32f4xx_it.c **** ADC_proc.N_on = 0;
379:Core/Src/stm32f4xx_it.c **** ADC_proc.N_off = 0;
380:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_OFF = 0;
381:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_ON = 0;
382:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data
383:Core/Src/stm32f4xx_it.c ****
384:Core/Src/stm32f4xx_it.c **** for (uint32_t i = Sweep_state.curr_step_start_DMA_N; i < ADC_BUFF_SIZE/2; i++) {
385:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
386:Core/Src/stm32f4xx_it.c **** uint32_t s = sample_seq++;
387:Core/Src/stm32f4xx_it.c **** if ((s & 1) != 0) { ADC_proc.sum_ON += v; ADC_proc.N_on++; } else { ADC_proc.sum_OFF += v; AD
388:Core/Src/stm32f4xx_it.c **** }
389:Core/Src/stm32f4xx_it.c **** ADC_proc.N = (ADC_BUFF_SIZE/2 - Sweep_state.curr_step_start_DMA_N)/2;
390:Core/Src/stm32f4xx_it.c ****
391:Core/Src/stm32f4xx_it.c **** }else{
392:Core/Src/stm32f4xx_it.c **** for (uint32_t i = 0; i < ADC_BUFF_SIZE/2; i++) {
899 .loc 1 392 19 view .LVU264
900 0014 0023 movs r3, #0
901 0016 72E0 b .L58
902 .L73:
903 .LBE12:
355:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag = 0;
904 .loc 1 355 5 is_stmt 1 view .LVU265
355:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag = 0;
905 .loc 1 355 40 is_stmt 0 view .LVU266
906 0018 0023 movs r3, #0
907 001a 464A ldr r2, .L77+4
908 001c 1371 strb r3, [r2, #4]
356:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
909 .loc 1 356 5 is_stmt 1 view .LVU267
910 .LBB15:
356:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
911 .loc 1 356 10 view .LVU268
912 .LVL44:
356:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
913 .loc 1 356 5 is_stmt 0 view .LVU269
914 001e 07E0 b .L59
915 .LVL45:
916 .L60:
917 .LBB16:
359:Core/Src/stm32f4xx_it.c **** }
918 .loc 1 359 75 is_stmt 1 discriminator 2 view .LVU270
359:Core/Src/stm32f4xx_it.c **** }
919 .loc 1 359 83 is_stmt 0 discriminator 2 view .LVU271
920 0020 4549 ldr r1, .L77+8
921 .LVL46:
359:Core/Src/stm32f4xx_it.c **** }
922 .loc 1 359 83 discriminator 2 view .LVU272
923 0022 C868 ldr r0, [r1, #12]
359:Core/Src/stm32f4xx_it.c **** }
ARM GAS /tmp/cceMYWsz.s page 26
924 .loc 1 359 92 discriminator 2 view .LVU273
925 0024 0244 add r2, r2, r0
926 .LVL47:
359:Core/Src/stm32f4xx_it.c **** }
927 .loc 1 359 92 discriminator 2 view .LVU274
928 0026 CA60 str r2, [r1, #12]
359:Core/Src/stm32f4xx_it.c **** }
929 .loc 1 359 98 is_stmt 1 discriminator 2 view .LVU275
359:Core/Src/stm32f4xx_it.c **** }
930 .loc 1 359 106 is_stmt 0 discriminator 2 view .LVU276
931 0028 0A6A ldr r2, [r1, #32]
359:Core/Src/stm32f4xx_it.c **** }
932 .loc 1 359 112 discriminator 2 view .LVU277
933 002a 0132 adds r2, r2, #1
934 002c 0A62 str r2, [r1, #32]
935 .L61:
359:Core/Src/stm32f4xx_it.c **** }
936 .loc 1 359 112 discriminator 2 view .LVU278
937 .LBE16:
356:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
938 .loc 1 356 66 is_stmt 1 discriminator 2 view .LVU279
939 002e 0133 adds r3, r3, #1
940 .LVL48:
941 .L59:
356:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
942 .loc 1 356 28 discriminator 1 view .LVU280
356:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
943 .loc 1 356 41 is_stmt 0 discriminator 1 view .LVU281
944 0030 404A ldr r2, .L77+4
945 0032 9268 ldr r2, [r2, #8]
356:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
946 .loc 1 356 28 discriminator 1 view .LVU282
947 0034 9A42 cmp r2, r3
948 0036 11D9 bls .L74
949 .LBB17:
357:Core/Src/stm32f4xx_it.c **** uint32_t s = sample_seq++;
950 .loc 1 357 7 is_stmt 1 view .LVU283
357:Core/Src/stm32f4xx_it.c **** uint32_t s = sample_seq++;
951 .loc 1 357 16 is_stmt 0 view .LVU284
952 0038 404A ldr r2, .L77+12
953 003a 32F81320 ldrh r2, [r2, r3, lsl #1]
954 .LVL49:
358:Core/Src/stm32f4xx_it.c **** if ((s & 1) != 0) { ADC_proc.sum_ON += v; ADC_proc.N_on++; } else { ADC_proc.sum_OFF += v; AD
955 .loc 1 358 7 is_stmt 1 view .LVU285
358:Core/Src/stm32f4xx_it.c **** if ((s & 1) != 0) { ADC_proc.sum_ON += v; ADC_proc.N_on++; } else { ADC_proc.sum_OFF += v; AD
956 .loc 1 358 30 is_stmt 0 view .LVU286
957 003e 4048 ldr r0, .L77+16
958 0040 0168 ldr r1, [r0]
959 0042 4C1C adds r4, r1, #1
960 0044 0460 str r4, [r0]
961 .LVL50:
359:Core/Src/stm32f4xx_it.c **** }
962 .loc 1 359 7 is_stmt 1 view .LVU287
359:Core/Src/stm32f4xx_it.c **** }
963 .loc 1 359 10 is_stmt 0 view .LVU288
964 0046 11F0010F tst r1, #1
965 004a E9D0 beq .L60
ARM GAS /tmp/cceMYWsz.s page 27
359:Core/Src/stm32f4xx_it.c **** }
966 .loc 1 359 27 is_stmt 1 discriminator 1 view .LVU289
359:Core/Src/stm32f4xx_it.c **** }
967 .loc 1 359 35 is_stmt 0 discriminator 1 view .LVU290
968 004c 3A49 ldr r1, .L77+8
969 .LVL51:
359:Core/Src/stm32f4xx_it.c **** }
970 .loc 1 359 35 discriminator 1 view .LVU291
971 004e 8868 ldr r0, [r1, #8]
359:Core/Src/stm32f4xx_it.c **** }
972 .loc 1 359 43 discriminator 1 view .LVU292
973 0050 0244 add r2, r2, r0
974 .LVL52:
359:Core/Src/stm32f4xx_it.c **** }
975 .loc 1 359 43 discriminator 1 view .LVU293
976 0052 8A60 str r2, [r1, #8]
359:Core/Src/stm32f4xx_it.c **** }
977 .loc 1 359 49 is_stmt 1 discriminator 1 view .LVU294
359:Core/Src/stm32f4xx_it.c **** }
978 .loc 1 359 57 is_stmt 0 discriminator 1 view .LVU295
979 0054 CA69 ldr r2, [r1, #28]
359:Core/Src/stm32f4xx_it.c **** }
980 .loc 1 359 62 discriminator 1 view .LVU296
981 0056 0132 adds r2, r2, #1
982 0058 CA61 str r2, [r1, #28]
983 005a E8E7 b .L61
984 .LVL53:
985 .L74:
359:Core/Src/stm32f4xx_it.c **** }
986 .loc 1 359 62 discriminator 1 view .LVU297
987 .LBE17:
988 .LBE15:
362:Core/Src/stm32f4xx_it.c ****
989 .loc 1 362 5 is_stmt 1 view .LVU298
362:Core/Src/stm32f4xx_it.c ****
990 .loc 1 362 31 is_stmt 0 view .LVU299
991 005c 3549 ldr r1, .L77+4
992 005e 8868 ldr r0, [r1, #8]
362:Core/Src/stm32f4xx_it.c ****
993 .loc 1 362 13 view .LVU300
994 0060 354B ldr r3, .L77+8
995 .LVL54:
362:Core/Src/stm32f4xx_it.c ****
996 .loc 1 362 13 view .LVU301
997 0062 9A69 ldr r2, [r3, #24]
362:Core/Src/stm32f4xx_it.c ****
998 .loc 1 362 16 view .LVU302
999 0064 02EB5002 add r2, r2, r0, lsr #1
1000 0068 9A61 str r2, [r3, #24]
364:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
1001 .loc 1 364 5 is_stmt 1 view .LVU303
364:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
1002 .loc 1 364 38 is_stmt 0 view .LVU304
1003 006a 9868 ldr r0, [r3, #8]
364:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_ON = ADC_proc.avg_ON;
1004 .loc 1 364 28 view .LVU305
1005 006c 354A ldr r2, .L77+20
ARM GAS /tmp/cceMYWsz.s page 28
1006 006e 9060 str r0, [r2, #8]
365:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
1007 .loc 1 365 5 is_stmt 1 view .LVU306
365:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
1008 .loc 1 365 38 is_stmt 0 view .LVU307
1009 0070 1869 ldr r0, [r3, #16]
365:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum_OFF = ADC_proc.sum_OFF;
1010 .loc 1 365 28 view .LVU308
1011 0072 1061 str r0, [r2, #16]
366:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
1012 .loc 1 366 5 is_stmt 1 view .LVU309
366:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
1013 .loc 1 366 39 is_stmt 0 view .LVU310
1014 0074 D868 ldr r0, [r3, #12]
366:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg_OFF = ADC_proc.avg_OFF;
1015 .loc 1 366 29 view .LVU311
1016 0076 D060 str r0, [r2, #12]
367:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
1017 .loc 1 367 5 is_stmt 1 view .LVU312
367:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
1018 .loc 1 367 39 is_stmt 0 view .LVU313
1019 0078 5869 ldr r0, [r3, #20]
367:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N;
1020 .loc 1 367 29 view .LVU314
1021 007a 5061 str r0, [r2, #20]
368:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N_on = ADC_proc.N_on;
1022 .loc 1 368 5 is_stmt 1 view .LVU315
368:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N_on = ADC_proc.N_on;
1023 .loc 1 368 33 is_stmt 0 view .LVU316
1024 007c 9869 ldr r0, [r3, #24]
368:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N_on = ADC_proc.N_on;
1025 .loc 1 368 23 view .LVU317
1026 007e 9061 str r0, [r2, #24]
369:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N_off = ADC_proc.N_off;
1027 .loc 1 369 5 is_stmt 1 view .LVU318
369:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N_off = ADC_proc.N_off;
1028 .loc 1 369 36 is_stmt 0 view .LVU319
1029 0080 D869 ldr r0, [r3, #28]
369:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N_off = ADC_proc.N_off;
1030 .loc 1 369 26 view .LVU320
1031 0082 D061 str r0, [r2, #28]
370:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
1032 .loc 1 370 5 is_stmt 1 view .LVU321
370:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
1033 .loc 1 370 37 is_stmt 0 view .LVU322
1034 0084 186A ldr r0, [r3, #32]
370:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled
1035 .loc 1 370 27 view .LVU323
1036 0086 1062 str r0, [r2, #32]
371:Core/Src/stm32f4xx_it.c ****
1037 .loc 1 371 5 is_stmt 1 view .LVU324
371:Core/Src/stm32f4xx_it.c ****
1038 .loc 1 371 28 is_stmt 0 view .LVU325
1039 0088 0220 movs r0, #2
1040 008a 1070 strb r0, [r2]
374:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF = 0;
1041 .loc 1 374 5 is_stmt 1 view .LVU326
ARM GAS /tmp/cceMYWsz.s page 29
374:Core/Src/stm32f4xx_it.c **** ADC_proc.sum_OFF = 0;
1042 .loc 1 374 21 is_stmt 0 view .LVU327
1043 008c 0022 movs r2, #0
1044 008e 9A60 str r2, [r3, #8]
375:Core/Src/stm32f4xx_it.c **** ADC_proc.sum = 0;
1045 .loc 1 375 5 is_stmt 1 view .LVU328
375:Core/Src/stm32f4xx_it.c **** ADC_proc.sum = 0;
1046 .loc 1 375 22 is_stmt 0 view .LVU329
1047 0090 DA60 str r2, [r3, #12]
376:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0;
1048 .loc 1 376 5 is_stmt 1 view .LVU330
376:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0;
1049 .loc 1 376 18 is_stmt 0 view .LVU331
1050 0092 5A60 str r2, [r3, #4]
377:Core/Src/stm32f4xx_it.c **** ADC_proc.N_on = 0;
1051 .loc 1 377 5 is_stmt 1 view .LVU332
377:Core/Src/stm32f4xx_it.c **** ADC_proc.N_on = 0;
1052 .loc 1 377 16 is_stmt 0 view .LVU333
1053 0094 9A61 str r2, [r3, #24]
378:Core/Src/stm32f4xx_it.c **** ADC_proc.N_off = 0;
1054 .loc 1 378 5 is_stmt 1 view .LVU334
378:Core/Src/stm32f4xx_it.c **** ADC_proc.N_off = 0;
1055 .loc 1 378 19 is_stmt 0 view .LVU335
1056 0096 DA61 str r2, [r3, #28]
379:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_OFF = 0;
1057 .loc 1 379 5 is_stmt 1 view .LVU336
379:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_OFF = 0;
1058 .loc 1 379 20 is_stmt 0 view .LVU337
1059 0098 1A62 str r2, [r3, #32]
380:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_ON = 0;
1060 .loc 1 380 5 is_stmt 1 view .LVU338
380:Core/Src/stm32f4xx_it.c **** ADC_proc.avg_ON = 0;
1061 .loc 1 380 22 is_stmt 0 view .LVU339
1062 009a 5A61 str r2, [r3, #20]
381:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data
1063 .loc 1 381 5 is_stmt 1 view .LVU340
381:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data
1064 .loc 1 381 21 is_stmt 0 view .LVU341
1065 009c 1A61 str r2, [r3, #16]
382:Core/Src/stm32f4xx_it.c ****
1066 .loc 1 382 5 is_stmt 1 view .LVU342
382:Core/Src/stm32f4xx_it.c ****
1067 .loc 1 382 21 is_stmt 0 view .LVU343
1068 009e 0122 movs r2, #1
1069 00a0 1A70 strb r2, [r3]
384:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
1070 .loc 1 384 5 is_stmt 1 view .LVU344
1071 .LBB18:
384:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
1072 .loc 1 384 10 view .LVU345
384:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
1073 .loc 1 384 19 is_stmt 0 view .LVU346
1074 00a2 8B68 ldr r3, [r1, #8]
1075 .LVL55:
384:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
1076 .loc 1 384 5 view .LVU347
1077 00a4 07E0 b .L63
ARM GAS /tmp/cceMYWsz.s page 30
1078 .LVL56:
1079 .L64:
1080 .LBB19:
387:Core/Src/stm32f4xx_it.c **** }
1081 .loc 1 387 75 is_stmt 1 discriminator 2 view .LVU348
387:Core/Src/stm32f4xx_it.c **** }
1082 .loc 1 387 83 is_stmt 0 discriminator 2 view .LVU349
1083 00a6 2449 ldr r1, .L77+8
1084 .LVL57:
387:Core/Src/stm32f4xx_it.c **** }
1085 .loc 1 387 83 discriminator 2 view .LVU350
1086 00a8 C868 ldr r0, [r1, #12]
387:Core/Src/stm32f4xx_it.c **** }
1087 .loc 1 387 92 discriminator 2 view .LVU351
1088 00aa 0244 add r2, r2, r0
1089 .LVL58:
387:Core/Src/stm32f4xx_it.c **** }
1090 .loc 1 387 92 discriminator 2 view .LVU352
1091 00ac CA60 str r2, [r1, #12]
387:Core/Src/stm32f4xx_it.c **** }
1092 .loc 1 387 98 is_stmt 1 discriminator 2 view .LVU353
387:Core/Src/stm32f4xx_it.c **** }
1093 .loc 1 387 106 is_stmt 0 discriminator 2 view .LVU354
1094 00ae 0A6A ldr r2, [r1, #32]
387:Core/Src/stm32f4xx_it.c **** }
1095 .loc 1 387 112 discriminator 2 view .LVU355
1096 00b0 0132 adds r2, r2, #1
1097 00b2 0A62 str r2, [r1, #32]
1098 .L65:
387:Core/Src/stm32f4xx_it.c **** }
1099 .loc 1 387 112 discriminator 2 view .LVU356
1100 .LBE19:
384:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
1101 .loc 1 384 80 is_stmt 1 discriminator 2 view .LVU357
1102 00b4 0133 adds r3, r3, #1
1103 .LVL59:
1104 .L63:
384:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
1105 .loc 1 384 60 discriminator 1 view .LVU358
1106 00b6 1F2B cmp r3, #31
1107 00b8 11D8 bhi .L75
1108 .LBB20:
385:Core/Src/stm32f4xx_it.c **** uint32_t s = sample_seq++;
1109 .loc 1 385 7 view .LVU359
385:Core/Src/stm32f4xx_it.c **** uint32_t s = sample_seq++;
1110 .loc 1 385 16 is_stmt 0 view .LVU360
1111 00ba 204A ldr r2, .L77+12
1112 00bc 32F81320 ldrh r2, [r2, r3, lsl #1]
1113 .LVL60:
386:Core/Src/stm32f4xx_it.c **** if ((s & 1) != 0) { ADC_proc.sum_ON += v; ADC_proc.N_on++; } else { ADC_proc.sum_OFF += v; AD
1114 .loc 1 386 7 is_stmt 1 view .LVU361
386:Core/Src/stm32f4xx_it.c **** if ((s & 1) != 0) { ADC_proc.sum_ON += v; ADC_proc.N_on++; } else { ADC_proc.sum_OFF += v; AD
1115 .loc 1 386 30 is_stmt 0 view .LVU362
1116 00c0 1F48 ldr r0, .L77+16
1117 00c2 0168 ldr r1, [r0]
1118 00c4 4C1C adds r4, r1, #1
1119 00c6 0460 str r4, [r0]
ARM GAS /tmp/cceMYWsz.s page 31
1120 .LVL61:
387:Core/Src/stm32f4xx_it.c **** }
1121 .loc 1 387 7 is_stmt 1 view .LVU363
387:Core/Src/stm32f4xx_it.c **** }
1122 .loc 1 387 10 is_stmt 0 view .LVU364
1123 00c8 11F0010F tst r1, #1
1124 00cc EBD0 beq .L64
387:Core/Src/stm32f4xx_it.c **** }
1125 .loc 1 387 27 is_stmt 1 discriminator 1 view .LVU365
387:Core/Src/stm32f4xx_it.c **** }
1126 .loc 1 387 35 is_stmt 0 discriminator 1 view .LVU366
1127 00ce 1A49 ldr r1, .L77+8
1128 .LVL62:
387:Core/Src/stm32f4xx_it.c **** }
1129 .loc 1 387 35 discriminator 1 view .LVU367
1130 00d0 8868 ldr r0, [r1, #8]
387:Core/Src/stm32f4xx_it.c **** }
1131 .loc 1 387 43 discriminator 1 view .LVU368
1132 00d2 0244 add r2, r2, r0
1133 .LVL63:
387:Core/Src/stm32f4xx_it.c **** }
1134 .loc 1 387 43 discriminator 1 view .LVU369
1135 00d4 8A60 str r2, [r1, #8]
387:Core/Src/stm32f4xx_it.c **** }
1136 .loc 1 387 49 is_stmt 1 discriminator 1 view .LVU370
387:Core/Src/stm32f4xx_it.c **** }
1137 .loc 1 387 57 is_stmt 0 discriminator 1 view .LVU371
1138 00d6 CA69 ldr r2, [r1, #28]
387:Core/Src/stm32f4xx_it.c **** }
1139 .loc 1 387 62 discriminator 1 view .LVU372
1140 00d8 0132 adds r2, r2, #1
1141 00da CA61 str r2, [r1, #28]
1142 00dc EAE7 b .L65
1143 .LVL64:
1144 .L75:
387:Core/Src/stm32f4xx_it.c **** }
1145 .loc 1 387 62 discriminator 1 view .LVU373
1146 .LBE20:
1147 .LBE18:
389:Core/Src/stm32f4xx_it.c ****
1148 .loc 1 389 5 is_stmt 1 view .LVU374
389:Core/Src/stm32f4xx_it.c ****
1149 .loc 1 389 48 is_stmt 0 view .LVU375
1150 00de 154B ldr r3, .L77+4
1151 .LVL65:
389:Core/Src/stm32f4xx_it.c ****
1152 .loc 1 389 48 view .LVU376
1153 00e0 9B68 ldr r3, [r3, #8]
389:Core/Src/stm32f4xx_it.c ****
1154 .loc 1 389 35 view .LVU377
1155 00e2 C3F12003 rsb r3, r3, #32
389:Core/Src/stm32f4xx_it.c ****
1156 .loc 1 389 71 view .LVU378
1157 00e6 5B08 lsrs r3, r3, #1
389:Core/Src/stm32f4xx_it.c ****
1158 .loc 1 389 16 view .LVU379
1159 00e8 134A ldr r2, .L77+8
ARM GAS /tmp/cceMYWsz.s page 32
1160 00ea 9361 str r3, [r2, #24]
1161 00ec 1FE0 b .L57
1162 .LVL66:
1163 .L68:
1164 .LBB21:
1165 .LBB13:
393:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
394:Core/Src/stm32f4xx_it.c **** uint32_t s = sample_seq++;
395:Core/Src/stm32f4xx_it.c **** if ((s & 1) != 0) { ADC_proc.sum_ON += v; ADC_proc.N_on++; } else { ADC_proc.sum_OFF += v; AD
1166 .loc 1 395 75 is_stmt 1 discriminator 2 view .LVU380
1167 .loc 1 395 83 is_stmt 0 discriminator 2 view .LVU381
1168 00ee 1249 ldr r1, .L77+8
1169 .LVL67:
1170 .loc 1 395 83 discriminator 2 view .LVU382
1171 00f0 C868 ldr r0, [r1, #12]
1172 .loc 1 395 92 discriminator 2 view .LVU383
1173 00f2 0244 add r2, r2, r0
1174 .LVL68:
1175 .loc 1 395 92 discriminator 2 view .LVU384
1176 00f4 CA60 str r2, [r1, #12]
1177 .loc 1 395 98 is_stmt 1 discriminator 2 view .LVU385
1178 .loc 1 395 106 is_stmt 0 discriminator 2 view .LVU386
1179 00f6 0A6A ldr r2, [r1, #32]
1180 .loc 1 395 112 discriminator 2 view .LVU387
1181 00f8 0132 adds r2, r2, #1
1182 00fa 0A62 str r2, [r1, #32]
1183 .L69:
1184 .loc 1 395 112 discriminator 2 view .LVU388
1185 .LBE13:
392:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
1186 .loc 1 392 48 is_stmt 1 discriminator 2 view .LVU389
1187 00fc 0133 adds r3, r3, #1
1188 .LVL69:
1189 .L58:
392:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
1190 .loc 1 392 28 discriminator 1 view .LVU390
1191 00fe 1F2B cmp r3, #31
1192 0100 11D8 bhi .L76
1193 .LBB14:
393:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
1194 .loc 1 393 7 view .LVU391
393:Core/Src/stm32f4xx_it.c **** uint16_t v = ADC1_buff_circular[i];
1195 .loc 1 393 16 is_stmt 0 view .LVU392
1196 0102 0E4A ldr r2, .L77+12
1197 0104 32F81320 ldrh r2, [r2, r3, lsl #1]
1198 .LVL70:
394:Core/Src/stm32f4xx_it.c **** if ((s & 1) != 0) { ADC_proc.sum_ON += v; ADC_proc.N_on++; } else { ADC_proc.sum_OFF += v; AD
1199 .loc 1 394 7 is_stmt 1 view .LVU393
394:Core/Src/stm32f4xx_it.c **** if ((s & 1) != 0) { ADC_proc.sum_ON += v; ADC_proc.N_on++; } else { ADC_proc.sum_OFF += v; AD
1200 .loc 1 394 30 is_stmt 0 view .LVU394
1201 0108 0D48 ldr r0, .L77+16
1202 010a 0168 ldr r1, [r0]
1203 010c 4C1C adds r4, r1, #1
1204 010e 0460 str r4, [r0]
1205 .LVL71:
1206 .loc 1 395 7 is_stmt 1 view .LVU395
1207 .loc 1 395 10 is_stmt 0 view .LVU396
ARM GAS /tmp/cceMYWsz.s page 33
1208 0110 11F0010F tst r1, #1
1209 0114 EBD0 beq .L68
1210 .loc 1 395 27 is_stmt 1 discriminator 1 view .LVU397
1211 .loc 1 395 35 is_stmt 0 discriminator 1 view .LVU398
1212 0116 0849 ldr r1, .L77+8
1213 .LVL72:
1214 .loc 1 395 35 discriminator 1 view .LVU399
1215 0118 8868 ldr r0, [r1, #8]
1216 .loc 1 395 43 discriminator 1 view .LVU400
1217 011a 0244 add r2, r2, r0
1218 .LVL73:
1219 .loc 1 395 43 discriminator 1 view .LVU401
1220 011c 8A60 str r2, [r1, #8]
1221 .loc 1 395 49 is_stmt 1 discriminator 1 view .LVU402
1222 .loc 1 395 57 is_stmt 0 discriminator 1 view .LVU403
1223 011e CA69 ldr r2, [r1, #28]
1224 .loc 1 395 62 discriminator 1 view .LVU404
1225 0120 0132 adds r2, r2, #1
1226 0122 CA61 str r2, [r1, #28]
1227 0124 EAE7 b .L69
1228 .LVL74:
1229 .L76:
1230 .loc 1 395 62 discriminator 1 view .LVU405
1231 .LBE14:
1232 .LBE21:
396:Core/Src/stm32f4xx_it.c **** }
397:Core/Src/stm32f4xx_it.c **** ADC_proc.N += (ADC_BUFF_SIZE/2)/2;
1233 .loc 1 397 5 is_stmt 1 view .LVU406
1234 .loc 1 397 13 is_stmt 0 view .LVU407
1235 0126 044A ldr r2, .L77+8
1236 0128 9369 ldr r3, [r2, #24]
1237 .LVL75:
1238 .loc 1 397 16 view .LVU408
1239 012a 1033 adds r3, r3, #16
1240 012c 9361 str r3, [r2, #24]
1241 .LVL76:
1242 .L57:
398:Core/Src/stm32f4xx_it.c **** }
399:Core/Src/stm32f4xx_it.c **** // This function is called when the first half of the ADC buffer is filled
400:Core/Src/stm32f4xx_it.c **** // You can process the first half of ADC1_buff_circular here
401:Core/Src/stm32f4xx_it.c **** }
1243 .loc 1 401 1 view .LVU409
1244 012e 10BD pop {r4, pc}
1245 .L78:
1246 .align 2
1247 .L77:
1248 0130 00040240 .word 1073873920
1249 0134 00000000 .word Sweep_state
1250 0138 00000000 .word ADC_proc
1251 013c 00000000 .word ADC1_buff_circular
1252 0140 00000000 .word sample_seq
1253 0144 00000000 .word ADC_proc_shadow
1254 .cfi_endproc
1255 .LFE253:
1257 .text
1258 .Letext0:
1259 .file 2 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h"
ARM GAS /tmp/cceMYWsz.s page 34
1260 .file 3 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h"
1261 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
1262 .file 5 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h"
1263 .file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h"
1264 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h"
1265 .file 8 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h"
1266 .file 9 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h"
1267 .file 10 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h"
1268 .file 11 "Core/Inc/main.h"
1269 .file 12 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h"
ARM GAS /tmp/cceMYWsz.s page 35
DEFINED SYMBOLS
*ABS*:00000000 stm32f4xx_it.c
/tmp/cceMYWsz.s:21 .text.NMI_Handler:00000000 $t
/tmp/cceMYWsz.s:27 .text.NMI_Handler:00000000 NMI_Handler
/tmp/cceMYWsz.s:44 .text.HardFault_Handler:00000000 $t
/tmp/cceMYWsz.s:50 .text.HardFault_Handler:00000000 HardFault_Handler
/tmp/cceMYWsz.s:67 .text.MemManage_Handler:00000000 $t
/tmp/cceMYWsz.s:73 .text.MemManage_Handler:00000000 MemManage_Handler
/tmp/cceMYWsz.s:90 .text.BusFault_Handler:00000000 $t
/tmp/cceMYWsz.s:96 .text.BusFault_Handler:00000000 BusFault_Handler
/tmp/cceMYWsz.s:113 .text.UsageFault_Handler:00000000 $t
/tmp/cceMYWsz.s:119 .text.UsageFault_Handler:00000000 UsageFault_Handler
/tmp/cceMYWsz.s:136 .text.SVC_Handler:00000000 $t
/tmp/cceMYWsz.s:142 .text.SVC_Handler:00000000 SVC_Handler
/tmp/cceMYWsz.s:155 .text.DebugMon_Handler:00000000 $t
/tmp/cceMYWsz.s:161 .text.DebugMon_Handler:00000000 DebugMon_Handler
/tmp/cceMYWsz.s:174 .text.PendSV_Handler:00000000 $t
/tmp/cceMYWsz.s:180 .text.PendSV_Handler:00000000 PendSV_Handler
/tmp/cceMYWsz.s:193 .text.SysTick_Handler:00000000 $t
/tmp/cceMYWsz.s:199 .text.SysTick_Handler:00000000 SysTick_Handler
/tmp/cceMYWsz.s:219 .text.EXTI0_IRQHandler:00000000 $t
/tmp/cceMYWsz.s:225 .text.EXTI0_IRQHandler:00000000 EXTI0_IRQHandler
/tmp/cceMYWsz.s:282 .text.EXTI0_IRQHandler:00000034 $d
/tmp/cceMYWsz.s:288 .text.EXTI3_IRQHandler:00000000 $t
/tmp/cceMYWsz.s:294 .text.EXTI3_IRQHandler:00000000 EXTI3_IRQHandler
/tmp/cceMYWsz.s:323 .text.EXTI3_IRQHandler:00000014 $d
/tmp/cceMYWsz.s:328 .text.DMA2_Stream0_IRQHandler:00000000 $t
/tmp/cceMYWsz.s:334 .text.DMA2_Stream0_IRQHandler:00000000 DMA2_Stream0_IRQHandler
/tmp/cceMYWsz.s:354 .text.DMA2_Stream0_IRQHandler:0000000c $d
/tmp/cceMYWsz.s:359 .text.OTG_FS_IRQHandler:00000000 $t
/tmp/cceMYWsz.s:365 .text.OTG_FS_IRQHandler:00000000 OTG_FS_IRQHandler
/tmp/cceMYWsz.s:385 .text.OTG_FS_IRQHandler:0000000c $d
/tmp/cceMYWsz.s:390 .text.HAL_ADC_ConvCpltCallback:00000000 $t
/tmp/cceMYWsz.s:396 .text.HAL_ADC_ConvCpltCallback:00000000 HAL_ADC_ConvCpltCallback
/tmp/cceMYWsz.s:854 .text.HAL_ADC_ConvCpltCallback:00000178 $d
/tmp/cceMYWsz.s:864 .text.HAL_ADC_ConvHalfCpltCallback:00000000 $t
/tmp/cceMYWsz.s:870 .text.HAL_ADC_ConvHalfCpltCallback:00000000 HAL_ADC_ConvHalfCpltCallback
/tmp/cceMYWsz.s:1248 .text.HAL_ADC_ConvHalfCpltCallback:00000130 $d
UNDEFINED SYMBOLS
HAL_IncTick
HAL_GPIO_EXTI_IRQHandler
hdma_adc1
Sweep_state
HAL_DMA_IRQHandler
HAL_PCD_IRQHandler
hpcd_USB_OTG_FS
HAL_GPIO_WritePin
ADC_proc
ADC1_buff_circular
sample_seq
ADC_proc_shadow
HAL_GPIO_TogglePin
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