589 lines
32 KiB
Plaintext
589 lines
32 KiB
Plaintext
ARM GAS /tmp/ccmB5bES.s page 1
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1 .cpu cortex-m4
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2 .arch armv7e-m
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3 .fpu fpv4-sp-d16
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4 .eabi_attribute 27, 1
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5 .eabi_attribute 28, 1
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6 .eabi_attribute 20, 1
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7 .eabi_attribute 21, 1
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8 .eabi_attribute 23, 3
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9 .eabi_attribute 24, 1
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10 .eabi_attribute 25, 1
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11 .eabi_attribute 26, 1
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12 .eabi_attribute 30, 1
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13 .eabi_attribute 34, 1
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14 .eabi_attribute 18, 4
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15 .file "system_stm32f4xx.c"
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16 .text
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17 .Ltext0:
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18 .cfi_sections .debug_frame
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19 .file 1 "Core/Src/system_stm32f4xx.c"
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20 .section .text.SystemInit,"ax",%progbits
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21 .align 1
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22 .global SystemInit
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23 .syntax unified
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24 .thumb
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25 .thumb_func
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27 SystemInit:
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28 .LFB239:
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1:Core/Src/system_stm32f4xx.c **** /**
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2:Core/Src/system_stm32f4xx.c **** ******************************************************************************
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3:Core/Src/system_stm32f4xx.c **** * @file system_stm32f4xx.c
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4:Core/Src/system_stm32f4xx.c **** * @author MCD Application Team
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5:Core/Src/system_stm32f4xx.c **** * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
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6:Core/Src/system_stm32f4xx.c **** *
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7:Core/Src/system_stm32f4xx.c **** * This file provides two functions and one global variable to be called from
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8:Core/Src/system_stm32f4xx.c **** * user application:
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9:Core/Src/system_stm32f4xx.c **** * - SystemInit(): This function is called at startup just after reset and
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10:Core/Src/system_stm32f4xx.c **** * before branch to main program. This call is made inside
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11:Core/Src/system_stm32f4xx.c **** * the "startup_stm32f4xx.s" file.
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12:Core/Src/system_stm32f4xx.c **** *
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13:Core/Src/system_stm32f4xx.c **** * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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14:Core/Src/system_stm32f4xx.c **** * by the user application to setup the SysTick
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15:Core/Src/system_stm32f4xx.c **** * timer or configure other parameters.
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16:Core/Src/system_stm32f4xx.c **** *
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17:Core/Src/system_stm32f4xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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18:Core/Src/system_stm32f4xx.c **** * be called whenever the core clock is changed
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19:Core/Src/system_stm32f4xx.c **** * during program execution.
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20:Core/Src/system_stm32f4xx.c **** *
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21:Core/Src/system_stm32f4xx.c **** *
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22:Core/Src/system_stm32f4xx.c **** ******************************************************************************
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23:Core/Src/system_stm32f4xx.c **** * @attention
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24:Core/Src/system_stm32f4xx.c **** *
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25:Core/Src/system_stm32f4xx.c **** * Copyright (c) 2017 STMicroelectronics.
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26:Core/Src/system_stm32f4xx.c **** * All rights reserved.
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27:Core/Src/system_stm32f4xx.c **** *
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28:Core/Src/system_stm32f4xx.c **** * This software is licensed under terms that can be found in the LICENSE file
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29:Core/Src/system_stm32f4xx.c **** * in the root directory of this software component.
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30:Core/Src/system_stm32f4xx.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
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ARM GAS /tmp/ccmB5bES.s page 2
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31:Core/Src/system_stm32f4xx.c **** *
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32:Core/Src/system_stm32f4xx.c **** ******************************************************************************
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33:Core/Src/system_stm32f4xx.c **** */
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34:Core/Src/system_stm32f4xx.c ****
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35:Core/Src/system_stm32f4xx.c **** /** @addtogroup CMSIS
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36:Core/Src/system_stm32f4xx.c **** * @{
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37:Core/Src/system_stm32f4xx.c **** */
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38:Core/Src/system_stm32f4xx.c ****
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39:Core/Src/system_stm32f4xx.c **** /** @addtogroup stm32f4xx_system
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40:Core/Src/system_stm32f4xx.c **** * @{
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41:Core/Src/system_stm32f4xx.c **** */
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42:Core/Src/system_stm32f4xx.c ****
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43:Core/Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Includes
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44:Core/Src/system_stm32f4xx.c **** * @{
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45:Core/Src/system_stm32f4xx.c **** */
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46:Core/Src/system_stm32f4xx.c ****
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47:Core/Src/system_stm32f4xx.c ****
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48:Core/Src/system_stm32f4xx.c **** #include "stm32f4xx.h"
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49:Core/Src/system_stm32f4xx.c ****
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50:Core/Src/system_stm32f4xx.c **** #if !defined (HSE_VALUE)
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51:Core/Src/system_stm32f4xx.c **** #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
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52:Core/Src/system_stm32f4xx.c **** #endif /* HSE_VALUE */
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53:Core/Src/system_stm32f4xx.c ****
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54:Core/Src/system_stm32f4xx.c **** #if !defined (HSI_VALUE)
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55:Core/Src/system_stm32f4xx.c **** #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
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56:Core/Src/system_stm32f4xx.c **** #endif /* HSI_VALUE */
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57:Core/Src/system_stm32f4xx.c ****
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58:Core/Src/system_stm32f4xx.c **** /**
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59:Core/Src/system_stm32f4xx.c **** * @}
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60:Core/Src/system_stm32f4xx.c **** */
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61:Core/Src/system_stm32f4xx.c ****
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62:Core/Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
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63:Core/Src/system_stm32f4xx.c **** * @{
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64:Core/Src/system_stm32f4xx.c **** */
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65:Core/Src/system_stm32f4xx.c ****
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66:Core/Src/system_stm32f4xx.c **** /**
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67:Core/Src/system_stm32f4xx.c **** * @}
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68:Core/Src/system_stm32f4xx.c **** */
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69:Core/Src/system_stm32f4xx.c ****
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70:Core/Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Defines
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71:Core/Src/system_stm32f4xx.c **** * @{
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72:Core/Src/system_stm32f4xx.c **** */
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73:Core/Src/system_stm32f4xx.c ****
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74:Core/Src/system_stm32f4xx.c **** /************************* Miscellaneous Configuration ************************/
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75:Core/Src/system_stm32f4xx.c **** /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
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76:Core/Src/system_stm32f4xx.c **** #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
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77:Core/Src/system_stm32f4xx.c **** || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
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78:Core/Src/system_stm32f4xx.c **** || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
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79:Core/Src/system_stm32f4xx.c **** /* #define DATA_IN_ExtSRAM */
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80:Core/Src/system_stm32f4xx.c **** #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||
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81:Core/Src/system_stm32f4xx.c **** STM32F412Zx || STM32F412Vx */
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82:Core/Src/system_stm32f4xx.c ****
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83:Core/Src/system_stm32f4xx.c **** #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
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84:Core/Src/system_stm32f4xx.c **** || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
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85:Core/Src/system_stm32f4xx.c **** /* #define DATA_IN_ExtSDRAM */
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86:Core/Src/system_stm32f4xx.c **** #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||
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87:Core/Src/system_stm32f4xx.c **** STM32F479xx */
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ARM GAS /tmp/ccmB5bES.s page 3
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88:Core/Src/system_stm32f4xx.c ****
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89:Core/Src/system_stm32f4xx.c **** /* Note: Following vector table addresses must be defined in line with linker
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90:Core/Src/system_stm32f4xx.c **** configuration. */
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91:Core/Src/system_stm32f4xx.c **** /*!< Uncomment the following line if you need to relocate the vector table
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92:Core/Src/system_stm32f4xx.c **** anywhere in Flash or Sram, else the vector table is kept at the automatic
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93:Core/Src/system_stm32f4xx.c **** remap of boot address selected */
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94:Core/Src/system_stm32f4xx.c **** /* #define USER_VECT_TAB_ADDRESS */
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95:Core/Src/system_stm32f4xx.c ****
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96:Core/Src/system_stm32f4xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
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97:Core/Src/system_stm32f4xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table
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98:Core/Src/system_stm32f4xx.c **** in Sram else user remap will be done in Flash. */
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99:Core/Src/system_stm32f4xx.c **** /* #define VECT_TAB_SRAM */
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100:Core/Src/system_stm32f4xx.c **** #if defined(VECT_TAB_SRAM)
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101:Core/Src/system_stm32f4xx.c **** #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
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102:Core/Src/system_stm32f4xx.c **** This value must be a multiple of 0x200. */
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103:Core/Src/system_stm32f4xx.c **** #else
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104:Core/Src/system_stm32f4xx.c **** #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
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105:Core/Src/system_stm32f4xx.c **** This value must be a multiple of 0x200. */
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106:Core/Src/system_stm32f4xx.c **** #endif /* VECT_TAB_SRAM */
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107:Core/Src/system_stm32f4xx.c **** #if !defined(VECT_TAB_OFFSET)
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108:Core/Src/system_stm32f4xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field.
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109:Core/Src/system_stm32f4xx.c **** This value must be a multiple of 0x200. */
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110:Core/Src/system_stm32f4xx.c **** #endif /* VECT_TAB_OFFSET */
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111:Core/Src/system_stm32f4xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
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112:Core/Src/system_stm32f4xx.c **** /******************************************************************************/
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113:Core/Src/system_stm32f4xx.c ****
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114:Core/Src/system_stm32f4xx.c **** /**
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115:Core/Src/system_stm32f4xx.c **** * @}
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116:Core/Src/system_stm32f4xx.c **** */
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117:Core/Src/system_stm32f4xx.c ****
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118:Core/Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Macros
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119:Core/Src/system_stm32f4xx.c **** * @{
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120:Core/Src/system_stm32f4xx.c **** */
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121:Core/Src/system_stm32f4xx.c ****
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122:Core/Src/system_stm32f4xx.c **** /**
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123:Core/Src/system_stm32f4xx.c **** * @}
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124:Core/Src/system_stm32f4xx.c **** */
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125:Core/Src/system_stm32f4xx.c ****
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126:Core/Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Variables
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127:Core/Src/system_stm32f4xx.c **** * @{
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128:Core/Src/system_stm32f4xx.c **** */
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129:Core/Src/system_stm32f4xx.c **** /* This variable is updated in three ways:
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130:Core/Src/system_stm32f4xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate()
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131:Core/Src/system_stm32f4xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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132:Core/Src/system_stm32f4xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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133:Core/Src/system_stm32f4xx.c **** Note: If you use this function to configure the system clock; then there
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134:Core/Src/system_stm32f4xx.c **** is no need to call the 2 first functions listed above, since SystemCoreClock
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135:Core/Src/system_stm32f4xx.c **** variable is updated automatically.
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136:Core/Src/system_stm32f4xx.c **** */
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137:Core/Src/system_stm32f4xx.c **** uint32_t SystemCoreClock = 16000000;
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138:Core/Src/system_stm32f4xx.c **** const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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139:Core/Src/system_stm32f4xx.c **** const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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140:Core/Src/system_stm32f4xx.c **** /**
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141:Core/Src/system_stm32f4xx.c **** * @}
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142:Core/Src/system_stm32f4xx.c **** */
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143:Core/Src/system_stm32f4xx.c ****
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144:Core/Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
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ARM GAS /tmp/ccmB5bES.s page 4
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145:Core/Src/system_stm32f4xx.c **** * @{
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146:Core/Src/system_stm32f4xx.c **** */
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147:Core/Src/system_stm32f4xx.c ****
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148:Core/Src/system_stm32f4xx.c **** #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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149:Core/Src/system_stm32f4xx.c **** static void SystemInit_ExtMemCtl(void);
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150:Core/Src/system_stm32f4xx.c **** #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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151:Core/Src/system_stm32f4xx.c ****
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152:Core/Src/system_stm32f4xx.c **** /**
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153:Core/Src/system_stm32f4xx.c **** * @}
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154:Core/Src/system_stm32f4xx.c **** */
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155:Core/Src/system_stm32f4xx.c ****
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156:Core/Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Functions
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157:Core/Src/system_stm32f4xx.c **** * @{
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158:Core/Src/system_stm32f4xx.c **** */
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159:Core/Src/system_stm32f4xx.c ****
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160:Core/Src/system_stm32f4xx.c **** /**
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161:Core/Src/system_stm32f4xx.c **** * @brief Setup the microcontroller system
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162:Core/Src/system_stm32f4xx.c **** * Initialize the FPU setting, vector table location and External memory
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163:Core/Src/system_stm32f4xx.c **** * configuration.
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164:Core/Src/system_stm32f4xx.c **** * @param None
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165:Core/Src/system_stm32f4xx.c **** * @retval None
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166:Core/Src/system_stm32f4xx.c **** */
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167:Core/Src/system_stm32f4xx.c **** void SystemInit(void)
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168:Core/Src/system_stm32f4xx.c **** {
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29 .loc 1 168 1 view -0
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30 .cfi_startproc
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31 @ args = 0, pretend = 0, frame = 0
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32 @ frame_needed = 0, uses_anonymous_args = 0
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33 @ link register save eliminated.
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169:Core/Src/system_stm32f4xx.c **** /* FPU settings ------------------------------------------------------------*/
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170:Core/Src/system_stm32f4xx.c **** #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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171:Core/Src/system_stm32f4xx.c **** SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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34 .loc 1 171 5 view .LVU1
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35 .loc 1 171 8 is_stmt 0 view .LVU2
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36 0000 034A ldr r2, .L2
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37 0002 D2F88830 ldr r3, [r2, #136]
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38 .loc 1 171 16 view .LVU3
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39 0006 43F47003 orr r3, r3, #15728640
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40 000a C2F88830 str r3, [r2, #136]
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172:Core/Src/system_stm32f4xx.c **** #endif
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173:Core/Src/system_stm32f4xx.c ****
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174:Core/Src/system_stm32f4xx.c **** #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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175:Core/Src/system_stm32f4xx.c **** SystemInit_ExtMemCtl();
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176:Core/Src/system_stm32f4xx.c **** #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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177:Core/Src/system_stm32f4xx.c ****
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178:Core/Src/system_stm32f4xx.c **** /* Configure the Vector Table location -------------------------------------*/
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179:Core/Src/system_stm32f4xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
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180:Core/Src/system_stm32f4xx.c **** SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM
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181:Core/Src/system_stm32f4xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
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182:Core/Src/system_stm32f4xx.c **** }
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41 .loc 1 182 1 view .LVU4
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42 000e 7047 bx lr
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43 .L3:
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44 .align 2
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45 .L2:
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46 0010 00ED00E0 .word -536810240
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47 .cfi_endproc
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ARM GAS /tmp/ccmB5bES.s page 5
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48 .LFE239:
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50 .section .text.SystemCoreClockUpdate,"ax",%progbits
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51 .align 1
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52 .global SystemCoreClockUpdate
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53 .syntax unified
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54 .thumb
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55 .thumb_func
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57 SystemCoreClockUpdate:
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58 .LFB240:
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183:Core/Src/system_stm32f4xx.c ****
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184:Core/Src/system_stm32f4xx.c **** /**
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185:Core/Src/system_stm32f4xx.c **** * @brief Update SystemCoreClock variable according to Clock Register Values.
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186:Core/Src/system_stm32f4xx.c **** * The SystemCoreClock variable contains the core clock (HCLK), it can
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187:Core/Src/system_stm32f4xx.c **** * be used by the user application to setup the SysTick timer or configure
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188:Core/Src/system_stm32f4xx.c **** * other parameters.
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189:Core/Src/system_stm32f4xx.c **** *
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190:Core/Src/system_stm32f4xx.c **** * @note Each time the core clock (HCLK) changes, this function must be called
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191:Core/Src/system_stm32f4xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration
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192:Core/Src/system_stm32f4xx.c **** * based on this variable will be incorrect.
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193:Core/Src/system_stm32f4xx.c **** *
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194:Core/Src/system_stm32f4xx.c **** * @note - The system frequency computed by this function is not the real
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195:Core/Src/system_stm32f4xx.c **** * frequency in the chip. It is calculated based on the predefined
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196:Core/Src/system_stm32f4xx.c **** * constant and the selected clock source:
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197:Core/Src/system_stm32f4xx.c **** *
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198:Core/Src/system_stm32f4xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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199:Core/Src/system_stm32f4xx.c **** *
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200:Core/Src/system_stm32f4xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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201:Core/Src/system_stm32f4xx.c **** *
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202:Core/Src/system_stm32f4xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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203:Core/Src/system_stm32f4xx.c **** * or HSI_VALUE(*) multiplied/divided by the PLL factors.
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204:Core/Src/system_stm32f4xx.c **** *
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205:Core/Src/system_stm32f4xx.c **** * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
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206:Core/Src/system_stm32f4xx.c **** * 16 MHz) but the real value may vary depending on the variations
|
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207:Core/Src/system_stm32f4xx.c **** * in voltage and temperature.
|
||
208:Core/Src/system_stm32f4xx.c **** *
|
||
209:Core/Src/system_stm32f4xx.c **** * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
|
||
210:Core/Src/system_stm32f4xx.c **** * depends on the application requirements), user has to ensure that HSE_VALUE
|
||
211:Core/Src/system_stm32f4xx.c **** * is same as the real frequency of the crystal used. Otherwise, this function
|
||
212:Core/Src/system_stm32f4xx.c **** * may have wrong result.
|
||
213:Core/Src/system_stm32f4xx.c **** *
|
||
214:Core/Src/system_stm32f4xx.c **** * - The result of this function could be not correct when using fractional
|
||
215:Core/Src/system_stm32f4xx.c **** * value for HSE crystal.
|
||
216:Core/Src/system_stm32f4xx.c **** *
|
||
217:Core/Src/system_stm32f4xx.c **** * @param None
|
||
218:Core/Src/system_stm32f4xx.c **** * @retval None
|
||
219:Core/Src/system_stm32f4xx.c **** */
|
||
220:Core/Src/system_stm32f4xx.c **** void SystemCoreClockUpdate(void)
|
||
221:Core/Src/system_stm32f4xx.c **** {
|
||
59 .loc 1 221 1 is_stmt 1 view -0
|
||
60 .cfi_startproc
|
||
61 @ args = 0, pretend = 0, frame = 0
|
||
62 @ frame_needed = 0, uses_anonymous_args = 0
|
||
63 @ link register save eliminated.
|
||
222:Core/Src/system_stm32f4xx.c **** uint32_t tmp, pllvco, pllp, pllsource, pllm;
|
||
64 .loc 1 222 3 view .LVU6
|
||
223:Core/Src/system_stm32f4xx.c ****
|
||
224:Core/Src/system_stm32f4xx.c **** /* Get SYSCLK source -------------------------------------------------------*/
|
||
ARM GAS /tmp/ccmB5bES.s page 6
|
||
|
||
|
||
225:Core/Src/system_stm32f4xx.c **** tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||
65 .loc 1 225 3 view .LVU7
|
||
66 .loc 1 225 12 is_stmt 0 view .LVU8
|
||
67 0000 224B ldr r3, .L11
|
||
68 0002 9B68 ldr r3, [r3, #8]
|
||
69 .loc 1 225 7 view .LVU9
|
||
70 0004 03F00C03 and r3, r3, #12
|
||
71 .LVL0:
|
||
226:Core/Src/system_stm32f4xx.c ****
|
||
227:Core/Src/system_stm32f4xx.c **** switch (tmp)
|
||
72 .loc 1 227 3 is_stmt 1 view .LVU10
|
||
73 0008 042B cmp r3, #4
|
||
74 000a 11D0 beq .L5
|
||
75 000c 082B cmp r3, #8
|
||
76 000e 13D0 beq .L6
|
||
77 0010 002B cmp r3, #0
|
||
78 0012 37D1 bne .L7
|
||
228:Core/Src/system_stm32f4xx.c **** {
|
||
229:Core/Src/system_stm32f4xx.c **** case 0x00: /* HSI used as system clock source */
|
||
230:Core/Src/system_stm32f4xx.c **** SystemCoreClock = HSI_VALUE;
|
||
79 .loc 1 230 7 view .LVU11
|
||
80 .loc 1 230 23 is_stmt 0 view .LVU12
|
||
81 0014 1E4B ldr r3, .L11+4
|
||
82 .LVL1:
|
||
83 .loc 1 230 23 view .LVU13
|
||
84 0016 1F4A ldr r2, .L11+8
|
||
85 0018 1A60 str r2, [r3]
|
||
231:Core/Src/system_stm32f4xx.c **** break;
|
||
86 .loc 1 231 7 is_stmt 1 view .LVU14
|
||
87 .L8:
|
||
232:Core/Src/system_stm32f4xx.c **** case 0x04: /* HSE used as system clock source */
|
||
233:Core/Src/system_stm32f4xx.c **** SystemCoreClock = HSE_VALUE;
|
||
234:Core/Src/system_stm32f4xx.c **** break;
|
||
235:Core/Src/system_stm32f4xx.c **** case 0x08: /* PLL used as system clock source */
|
||
236:Core/Src/system_stm32f4xx.c ****
|
||
237:Core/Src/system_stm32f4xx.c **** /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
|
||
238:Core/Src/system_stm32f4xx.c **** SYSCLK = PLL_VCO / PLL_P
|
||
239:Core/Src/system_stm32f4xx.c **** */
|
||
240:Core/Src/system_stm32f4xx.c **** pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
|
||
241:Core/Src/system_stm32f4xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
||
242:Core/Src/system_stm32f4xx.c ****
|
||
243:Core/Src/system_stm32f4xx.c **** if (pllsource != 0)
|
||
244:Core/Src/system_stm32f4xx.c **** {
|
||
245:Core/Src/system_stm32f4xx.c **** /* HSE used as PLL clock source */
|
||
246:Core/Src/system_stm32f4xx.c **** pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||
247:Core/Src/system_stm32f4xx.c **** }
|
||
248:Core/Src/system_stm32f4xx.c **** else
|
||
249:Core/Src/system_stm32f4xx.c **** {
|
||
250:Core/Src/system_stm32f4xx.c **** /* HSI used as PLL clock source */
|
||
251:Core/Src/system_stm32f4xx.c **** pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||
252:Core/Src/system_stm32f4xx.c **** }
|
||
253:Core/Src/system_stm32f4xx.c ****
|
||
254:Core/Src/system_stm32f4xx.c **** pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
|
||
255:Core/Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp;
|
||
256:Core/Src/system_stm32f4xx.c **** break;
|
||
257:Core/Src/system_stm32f4xx.c **** default:
|
||
258:Core/Src/system_stm32f4xx.c **** SystemCoreClock = HSI_VALUE;
|
||
ARM GAS /tmp/ccmB5bES.s page 7
|
||
|
||
|
||
259:Core/Src/system_stm32f4xx.c **** break;
|
||
260:Core/Src/system_stm32f4xx.c **** }
|
||
261:Core/Src/system_stm32f4xx.c **** /* Compute HCLK frequency --------------------------------------------------*/
|
||
262:Core/Src/system_stm32f4xx.c **** /* Get HCLK prescaler */
|
||
263:Core/Src/system_stm32f4xx.c **** tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||
88 .loc 1 263 3 view .LVU15
|
||
89 .loc 1 263 28 is_stmt 0 view .LVU16
|
||
90 001a 1C4B ldr r3, .L11
|
||
91 001c 9B68 ldr r3, [r3, #8]
|
||
92 .loc 1 263 52 view .LVU17
|
||
93 001e C3F30313 ubfx r3, r3, #4, #4
|
||
94 .loc 1 263 22 view .LVU18
|
||
95 0022 1D4A ldr r2, .L11+12
|
||
96 0024 D15C ldrb r1, [r2, r3] @ zero_extendqisi2
|
||
97 .LVL2:
|
||
264:Core/Src/system_stm32f4xx.c **** /* HCLK frequency */
|
||
265:Core/Src/system_stm32f4xx.c **** SystemCoreClock >>= tmp;
|
||
98 .loc 1 265 3 is_stmt 1 view .LVU19
|
||
99 .loc 1 265 19 is_stmt 0 view .LVU20
|
||
100 0026 1A4A ldr r2, .L11+4
|
||
101 0028 1368 ldr r3, [r2]
|
||
102 002a CB40 lsrs r3, r3, r1
|
||
103 002c 1360 str r3, [r2]
|
||
266:Core/Src/system_stm32f4xx.c **** }
|
||
104 .loc 1 266 1 view .LVU21
|
||
105 002e 7047 bx lr
|
||
106 .LVL3:
|
||
107 .L5:
|
||
233:Core/Src/system_stm32f4xx.c **** break;
|
||
108 .loc 1 233 7 is_stmt 1 view .LVU22
|
||
233:Core/Src/system_stm32f4xx.c **** break;
|
||
109 .loc 1 233 23 is_stmt 0 view .LVU23
|
||
110 0030 174B ldr r3, .L11+4
|
||
111 .LVL4:
|
||
233:Core/Src/system_stm32f4xx.c **** break;
|
||
112 .loc 1 233 23 view .LVU24
|
||
113 0032 1A4A ldr r2, .L11+16
|
||
114 0034 1A60 str r2, [r3]
|
||
234:Core/Src/system_stm32f4xx.c **** case 0x08: /* PLL used as system clock source */
|
||
115 .loc 1 234 7 is_stmt 1 view .LVU25
|
||
116 0036 F0E7 b .L8
|
||
117 .LVL5:
|
||
118 .L6:
|
||
240:Core/Src/system_stm32f4xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
||
119 .loc 1 240 7 view .LVU26
|
||
240:Core/Src/system_stm32f4xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
||
120 .loc 1 240 23 is_stmt 0 view .LVU27
|
||
121 0038 144B ldr r3, .L11
|
||
122 .LVL6:
|
||
240:Core/Src/system_stm32f4xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
||
123 .loc 1 240 23 view .LVU28
|
||
124 003a 5968 ldr r1, [r3, #4]
|
||
125 .LVL7:
|
||
241:Core/Src/system_stm32f4xx.c ****
|
||
126 .loc 1 241 7 is_stmt 1 view .LVU29
|
||
241:Core/Src/system_stm32f4xx.c ****
|
||
127 .loc 1 241 17 is_stmt 0 view .LVU30
|
||
ARM GAS /tmp/ccmB5bES.s page 8
|
||
|
||
|
||
128 003c 5A68 ldr r2, [r3, #4]
|
||
241:Core/Src/system_stm32f4xx.c ****
|
||
129 .loc 1 241 12 view .LVU31
|
||
130 003e 02F03F02 and r2, r2, #63
|
||
131 .LVL8:
|
||
243:Core/Src/system_stm32f4xx.c **** {
|
||
132 .loc 1 243 7 is_stmt 1 view .LVU32
|
||
243:Core/Src/system_stm32f4xx.c **** {
|
||
133 .loc 1 243 10 is_stmt 0 view .LVU33
|
||
134 0042 11F4800F tst r1, #4194304
|
||
135 0046 13D0 beq .L9
|
||
246:Core/Src/system_stm32f4xx.c **** }
|
||
136 .loc 1 246 9 is_stmt 1 view .LVU34
|
||
246:Core/Src/system_stm32f4xx.c **** }
|
||
137 .loc 1 246 29 is_stmt 0 view .LVU35
|
||
138 0048 144B ldr r3, .L11+16
|
||
139 004a B3FBF2F3 udiv r3, r3, r2
|
||
246:Core/Src/system_stm32f4xx.c **** }
|
||
140 .loc 1 246 44 view .LVU36
|
||
141 004e 0F4A ldr r2, .L11
|
||
142 .LVL9:
|
||
246:Core/Src/system_stm32f4xx.c **** }
|
||
143 .loc 1 246 44 view .LVU37
|
||
144 0050 5268 ldr r2, [r2, #4]
|
||
246:Core/Src/system_stm32f4xx.c **** }
|
||
145 .loc 1 246 74 view .LVU38
|
||
146 0052 C2F38812 ubfx r2, r2, #6, #9
|
||
246:Core/Src/system_stm32f4xx.c **** }
|
||
147 .loc 1 246 16 view .LVU39
|
||
148 0056 02FB03F3 mul r3, r2, r3
|
||
149 .LVL10:
|
||
150 .L10:
|
||
254:Core/Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp;
|
||
151 .loc 1 254 7 is_stmt 1 view .LVU40
|
||
254:Core/Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp;
|
||
152 .loc 1 254 20 is_stmt 0 view .LVU41
|
||
153 005a 0C4A ldr r2, .L11
|
||
154 005c 5268 ldr r2, [r2, #4]
|
||
254:Core/Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp;
|
||
155 .loc 1 254 50 view .LVU42
|
||
156 005e C2F30142 ubfx r2, r2, #16, #2
|
||
254:Core/Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp;
|
||
157 .loc 1 254 56 view .LVU43
|
||
158 0062 0132 adds r2, r2, #1
|
||
254:Core/Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp;
|
||
159 .loc 1 254 12 view .LVU44
|
||
160 0064 5200 lsls r2, r2, #1
|
||
161 .LVL11:
|
||
255:Core/Src/system_stm32f4xx.c **** break;
|
||
162 .loc 1 255 7 is_stmt 1 view .LVU45
|
||
255:Core/Src/system_stm32f4xx.c **** break;
|
||
163 .loc 1 255 31 is_stmt 0 view .LVU46
|
||
164 0066 B3FBF2F3 udiv r3, r3, r2
|
||
165 .LVL12:
|
||
255:Core/Src/system_stm32f4xx.c **** break;
|
||
166 .loc 1 255 23 view .LVU47
|
||
167 006a 094A ldr r2, .L11+4
|
||
ARM GAS /tmp/ccmB5bES.s page 9
|
||
|
||
|
||
168 .LVL13:
|
||
255:Core/Src/system_stm32f4xx.c **** break;
|
||
169 .loc 1 255 23 view .LVU48
|
||
170 006c 1360 str r3, [r2]
|
||
256:Core/Src/system_stm32f4xx.c **** default:
|
||
171 .loc 1 256 7 is_stmt 1 view .LVU49
|
||
172 006e D4E7 b .L8
|
||
173 .LVL14:
|
||
174 .L9:
|
||
251:Core/Src/system_stm32f4xx.c **** }
|
||
175 .loc 1 251 9 view .LVU50
|
||
251:Core/Src/system_stm32f4xx.c **** }
|
||
176 .loc 1 251 29 is_stmt 0 view .LVU51
|
||
177 0070 084B ldr r3, .L11+8
|
||
178 0072 B3FBF2F3 udiv r3, r3, r2
|
||
251:Core/Src/system_stm32f4xx.c **** }
|
||
179 .loc 1 251 44 view .LVU52
|
||
180 0076 054A ldr r2, .L11
|
||
181 .LVL15:
|
||
251:Core/Src/system_stm32f4xx.c **** }
|
||
182 .loc 1 251 44 view .LVU53
|
||
183 0078 5268 ldr r2, [r2, #4]
|
||
251:Core/Src/system_stm32f4xx.c **** }
|
||
184 .loc 1 251 74 view .LVU54
|
||
185 007a C2F38812 ubfx r2, r2, #6, #9
|
||
251:Core/Src/system_stm32f4xx.c **** }
|
||
186 .loc 1 251 16 view .LVU55
|
||
187 007e 02FB03F3 mul r3, r2, r3
|
||
188 .LVL16:
|
||
251:Core/Src/system_stm32f4xx.c **** }
|
||
189 .loc 1 251 16 view .LVU56
|
||
190 0082 EAE7 b .L10
|
||
191 .LVL17:
|
||
192 .L7:
|
||
258:Core/Src/system_stm32f4xx.c **** break;
|
||
193 .loc 1 258 7 is_stmt 1 view .LVU57
|
||
258:Core/Src/system_stm32f4xx.c **** break;
|
||
194 .loc 1 258 23 is_stmt 0 view .LVU58
|
||
195 0084 024B ldr r3, .L11+4
|
||
196 .LVL18:
|
||
258:Core/Src/system_stm32f4xx.c **** break;
|
||
197 .loc 1 258 23 view .LVU59
|
||
198 0086 034A ldr r2, .L11+8
|
||
199 0088 1A60 str r2, [r3]
|
||
259:Core/Src/system_stm32f4xx.c **** }
|
||
200 .loc 1 259 7 is_stmt 1 view .LVU60
|
||
201 008a C6E7 b .L8
|
||
202 .L12:
|
||
203 .align 2
|
||
204 .L11:
|
||
205 008c 00380240 .word 1073887232
|
||
206 0090 00000000 .word SystemCoreClock
|
||
207 0094 0024F400 .word 16000000
|
||
208 0098 00000000 .word AHBPrescTable
|
||
209 009c 00127A00 .word 8000000
|
||
210 .cfi_endproc
|
||
211 .LFE240:
|
||
ARM GAS /tmp/ccmB5bES.s page 10
|
||
|
||
|
||
213 .global APBPrescTable
|
||
214 .section .rodata.APBPrescTable,"a"
|
||
215 .align 2
|
||
218 APBPrescTable:
|
||
219 0000 00000000 .ascii "\000\000\000\000\001\002\003\004"
|
||
219 01020304
|
||
220 .global AHBPrescTable
|
||
221 .section .rodata.AHBPrescTable,"a"
|
||
222 .align 2
|
||
225 AHBPrescTable:
|
||
226 0000 00000000 .ascii "\000\000\000\000\000\000\000\000\001\002\003\004\006"
|
||
226 00000000
|
||
226 01020304
|
||
226 06
|
||
227 000d 070809 .ascii "\007\010\011"
|
||
228 .global SystemCoreClock
|
||
229 .section .data.SystemCoreClock,"aw"
|
||
230 .align 2
|
||
233 SystemCoreClock:
|
||
234 0000 0024F400 .word 16000000
|
||
235 .text
|
||
236 .Letext0:
|
||
237 .file 2 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h"
|
||
238 .file 3 "Drivers/CMSIS/Include/core_cm4.h"
|
||
239 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h"
|
||
240 .file 5 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h"
|
||
ARM GAS /tmp/ccmB5bES.s page 11
|
||
|
||
|
||
DEFINED SYMBOLS
|
||
*ABS*:00000000 system_stm32f4xx.c
|
||
/tmp/ccmB5bES.s:21 .text.SystemInit:00000000 $t
|
||
/tmp/ccmB5bES.s:27 .text.SystemInit:00000000 SystemInit
|
||
/tmp/ccmB5bES.s:46 .text.SystemInit:00000010 $d
|
||
/tmp/ccmB5bES.s:51 .text.SystemCoreClockUpdate:00000000 $t
|
||
/tmp/ccmB5bES.s:57 .text.SystemCoreClockUpdate:00000000 SystemCoreClockUpdate
|
||
/tmp/ccmB5bES.s:205 .text.SystemCoreClockUpdate:0000008c $d
|
||
/tmp/ccmB5bES.s:233 .data.SystemCoreClock:00000000 SystemCoreClock
|
||
/tmp/ccmB5bES.s:225 .rodata.AHBPrescTable:00000000 AHBPrescTable
|
||
/tmp/ccmB5bES.s:218 .rodata.APBPrescTable:00000000 APBPrescTable
|
||
/tmp/ccmB5bES.s:215 .rodata.APBPrescTable:00000000 $d
|
||
/tmp/ccmB5bES.s:222 .rodata.AHBPrescTable:00000000 $d
|
||
/tmp/ccmB5bES.s:230 .data.SystemCoreClock:00000000 $d
|
||
|
||
NO UNDEFINED SYMBOLS
|