ARM GAS /tmp/ccdzv1TD.s page 1 1 .cpu cortex-m4 2 .arch armv7e-m 3 .fpu fpv4-sp-d16 4 .eabi_attribute 27, 1 5 .eabi_attribute 28, 1 6 .eabi_attribute 20, 1 7 .eabi_attribute 21, 1 8 .eabi_attribute 23, 3 9 .eabi_attribute 24, 1 10 .eabi_attribute 25, 1 11 .eabi_attribute 26, 1 12 .eabi_attribute 30, 1 13 .eabi_attribute 34, 1 14 .eabi_attribute 18, 4 15 .file "stm32f4xx_it.c" 16 .text 17 .Ltext0: 18 .cfi_sections .debug_frame 19 .file 1 "Core/Src/stm32f4xx_it.c" 20 .section .text.NMI_Handler,"ax",%progbits 21 .align 1 22 .global NMI_Handler 23 .syntax unified 24 .thumb 25 .thumb_func 27 NMI_Handler: 28 .LFB239: 1:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN Header */ 2:Core/Src/stm32f4xx_it.c **** /** 3:Core/Src/stm32f4xx_it.c **** ****************************************************************************** 4:Core/Src/stm32f4xx_it.c **** * @file stm32f4xx_it.c 5:Core/Src/stm32f4xx_it.c **** * @brief Interrupt Service Routines. 6:Core/Src/stm32f4xx_it.c **** ****************************************************************************** 7:Core/Src/stm32f4xx_it.c **** * @attention 8:Core/Src/stm32f4xx_it.c **** * 9:Core/Src/stm32f4xx_it.c **** * Copyright (c) 2025 STMicroelectronics. 10:Core/Src/stm32f4xx_it.c **** * All rights reserved. 11:Core/Src/stm32f4xx_it.c **** * 12:Core/Src/stm32f4xx_it.c **** * This software is licensed under terms that can be found in the LICENSE file 13:Core/Src/stm32f4xx_it.c **** * in the root directory of this software component. 14:Core/Src/stm32f4xx_it.c **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Core/Src/stm32f4xx_it.c **** * 16:Core/Src/stm32f4xx_it.c **** ****************************************************************************** 17:Core/Src/stm32f4xx_it.c **** */ 18:Core/Src/stm32f4xx_it.c **** /* USER CODE END Header */ 19:Core/Src/stm32f4xx_it.c **** 20:Core/Src/stm32f4xx_it.c **** /* Includes ------------------------------------------------------------------*/ 21:Core/Src/stm32f4xx_it.c **** #include "main.h" 22:Core/Src/stm32f4xx_it.c **** #include "stm32f4xx_it.h" 23:Core/Src/stm32f4xx_it.c **** /* Private includes ----------------------------------------------------------*/ 24:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN Includes */ 25:Core/Src/stm32f4xx_it.c **** /* USER CODE END Includes */ 26:Core/Src/stm32f4xx_it.c **** 27:Core/Src/stm32f4xx_it.c **** /* Private typedef -----------------------------------------------------------*/ 28:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN TD */ 29:Core/Src/stm32f4xx_it.c **** 30:Core/Src/stm32f4xx_it.c **** /* USER CODE END TD */ ARM GAS /tmp/ccdzv1TD.s page 2 31:Core/Src/stm32f4xx_it.c **** 32:Core/Src/stm32f4xx_it.c **** /* Private define ------------------------------------------------------------*/ 33:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PD */ 34:Core/Src/stm32f4xx_it.c **** 35:Core/Src/stm32f4xx_it.c **** /* USER CODE END PD */ 36:Core/Src/stm32f4xx_it.c **** 37:Core/Src/stm32f4xx_it.c **** /* Private macro -------------------------------------------------------------*/ 38:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PM */ 39:Core/Src/stm32f4xx_it.c **** 40:Core/Src/stm32f4xx_it.c **** /* USER CODE END PM */ 41:Core/Src/stm32f4xx_it.c **** 42:Core/Src/stm32f4xx_it.c **** /* Private variables ---------------------------------------------------------*/ 43:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PV */ 44:Core/Src/stm32f4xx_it.c **** 45:Core/Src/stm32f4xx_it.c **** /* USER CODE END PV */ 46:Core/Src/stm32f4xx_it.c **** 47:Core/Src/stm32f4xx_it.c **** /* Private function prototypes -----------------------------------------------*/ 48:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PFP */ 49:Core/Src/stm32f4xx_it.c **** 50:Core/Src/stm32f4xx_it.c **** /* USER CODE END PFP */ 51:Core/Src/stm32f4xx_it.c **** 52:Core/Src/stm32f4xx_it.c **** /* Private user code ---------------------------------------------------------*/ 53:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN 0 */ 54:Core/Src/stm32f4xx_it.c **** 55:Core/Src/stm32f4xx_it.c **** /* USER CODE END 0 */ 56:Core/Src/stm32f4xx_it.c **** 57:Core/Src/stm32f4xx_it.c **** /* External variables --------------------------------------------------------*/ 58:Core/Src/stm32f4xx_it.c **** extern PCD_HandleTypeDef hpcd_USB_OTG_FS; 59:Core/Src/stm32f4xx_it.c **** extern DMA_HandleTypeDef hdma_adc1; 60:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN EV */ 61:Core/Src/stm32f4xx_it.c **** /* Externs are provided via main.h; no extra declarations needed here */ 62:Core/Src/stm32f4xx_it.c **** /* USER CODE END EV */ 63:Core/Src/stm32f4xx_it.c **** 64:Core/Src/stm32f4xx_it.c **** /******************************************************************************/ 65:Core/Src/stm32f4xx_it.c **** /* Cortex-M4 Processor Interruption and Exception Handlers */ 66:Core/Src/stm32f4xx_it.c **** /******************************************************************************/ 67:Core/Src/stm32f4xx_it.c **** /** 68:Core/Src/stm32f4xx_it.c **** * @brief This function handles Non maskable interrupt. 69:Core/Src/stm32f4xx_it.c **** */ 70:Core/Src/stm32f4xx_it.c **** void NMI_Handler(void) 71:Core/Src/stm32f4xx_it.c **** { 29 .loc 1 71 1 view -0 30 .cfi_startproc 31 @ Volatile: function does not return. 32 @ args = 0, pretend = 0, frame = 0 33 @ frame_needed = 0, uses_anonymous_args = 0 34 @ link register save eliminated. 35 .L2: 72:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ 73:Core/Src/stm32f4xx_it.c **** 74:Core/Src/stm32f4xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 0 */ 75:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ 76:Core/Src/stm32f4xx_it.c **** while (1) 36 .loc 1 76 4 view .LVU1 77:Core/Src/stm32f4xx_it.c **** { 78:Core/Src/stm32f4xx_it.c **** } 37 .loc 1 78 3 view .LVU2 ARM GAS /tmp/ccdzv1TD.s page 3 76:Core/Src/stm32f4xx_it.c **** { 38 .loc 1 76 10 view .LVU3 39 0000 FEE7 b .L2 40 .cfi_endproc 41 .LFE239: 43 .section .text.HardFault_Handler,"ax",%progbits 44 .align 1 45 .global HardFault_Handler 46 .syntax unified 47 .thumb 48 .thumb_func 50 HardFault_Handler: 51 .LFB240: 79:Core/Src/stm32f4xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 1 */ 80:Core/Src/stm32f4xx_it.c **** } 81:Core/Src/stm32f4xx_it.c **** 82:Core/Src/stm32f4xx_it.c **** /** 83:Core/Src/stm32f4xx_it.c **** * @brief This function handles Hard fault interrupt. 84:Core/Src/stm32f4xx_it.c **** */ 85:Core/Src/stm32f4xx_it.c **** void HardFault_Handler(void) 86:Core/Src/stm32f4xx_it.c **** { 52 .loc 1 86 1 view -0 53 .cfi_startproc 54 @ Volatile: function does not return. 55 @ args = 0, pretend = 0, frame = 0 56 @ frame_needed = 0, uses_anonymous_args = 0 57 @ link register save eliminated. 58 .L4: 87:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN HardFault_IRQn 0 */ 88:Core/Src/stm32f4xx_it.c **** 89:Core/Src/stm32f4xx_it.c **** /* USER CODE END HardFault_IRQn 0 */ 90:Core/Src/stm32f4xx_it.c **** while (1) 59 .loc 1 90 3 view .LVU5 91:Core/Src/stm32f4xx_it.c **** { 92:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_HardFault_IRQn 0 */ 93:Core/Src/stm32f4xx_it.c **** /* USER CODE END W1_HardFault_IRQn 0 */ 94:Core/Src/stm32f4xx_it.c **** } 60 .loc 1 94 3 view .LVU6 90:Core/Src/stm32f4xx_it.c **** { 61 .loc 1 90 9 view .LVU7 62 0000 FEE7 b .L4 63 .cfi_endproc 64 .LFE240: 66 .section .text.MemManage_Handler,"ax",%progbits 67 .align 1 68 .global MemManage_Handler 69 .syntax unified 70 .thumb 71 .thumb_func 73 MemManage_Handler: 74 .LFB241: 95:Core/Src/stm32f4xx_it.c **** } 96:Core/Src/stm32f4xx_it.c **** 97:Core/Src/stm32f4xx_it.c **** /** 98:Core/Src/stm32f4xx_it.c **** * @brief This function handles Memory management fault. 99:Core/Src/stm32f4xx_it.c **** */ 100:Core/Src/stm32f4xx_it.c **** void MemManage_Handler(void) ARM GAS /tmp/ccdzv1TD.s page 4 101:Core/Src/stm32f4xx_it.c **** { 75 .loc 1 101 1 view -0 76 .cfi_startproc 77 @ Volatile: function does not return. 78 @ args = 0, pretend = 0, frame = 0 79 @ frame_needed = 0, uses_anonymous_args = 0 80 @ link register save eliminated. 81 .L6: 102:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN MemoryManagement_IRQn 0 */ 103:Core/Src/stm32f4xx_it.c **** 104:Core/Src/stm32f4xx_it.c **** /* USER CODE END MemoryManagement_IRQn 0 */ 105:Core/Src/stm32f4xx_it.c **** while (1) 82 .loc 1 105 3 view .LVU9 106:Core/Src/stm32f4xx_it.c **** { 107:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ 108:Core/Src/stm32f4xx_it.c **** /* USER CODE END W1_MemoryManagement_IRQn 0 */ 109:Core/Src/stm32f4xx_it.c **** } 83 .loc 1 109 3 view .LVU10 105:Core/Src/stm32f4xx_it.c **** { 84 .loc 1 105 9 view .LVU11 85 0000 FEE7 b .L6 86 .cfi_endproc 87 .LFE241: 89 .section .text.BusFault_Handler,"ax",%progbits 90 .align 1 91 .global BusFault_Handler 92 .syntax unified 93 .thumb 94 .thumb_func 96 BusFault_Handler: 97 .LFB242: 110:Core/Src/stm32f4xx_it.c **** } 111:Core/Src/stm32f4xx_it.c **** 112:Core/Src/stm32f4xx_it.c **** /** 113:Core/Src/stm32f4xx_it.c **** * @brief This function handles Pre-fetch fault, memory access fault. 114:Core/Src/stm32f4xx_it.c **** */ 115:Core/Src/stm32f4xx_it.c **** void BusFault_Handler(void) 116:Core/Src/stm32f4xx_it.c **** { 98 .loc 1 116 1 view -0 99 .cfi_startproc 100 @ Volatile: function does not return. 101 @ args = 0, pretend = 0, frame = 0 102 @ frame_needed = 0, uses_anonymous_args = 0 103 @ link register save eliminated. 104 .L8: 117:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN BusFault_IRQn 0 */ 118:Core/Src/stm32f4xx_it.c **** 119:Core/Src/stm32f4xx_it.c **** /* USER CODE END BusFault_IRQn 0 */ 120:Core/Src/stm32f4xx_it.c **** while (1) 105 .loc 1 120 3 view .LVU13 121:Core/Src/stm32f4xx_it.c **** { 122:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_BusFault_IRQn 0 */ 123:Core/Src/stm32f4xx_it.c **** /* USER CODE END W1_BusFault_IRQn 0 */ 124:Core/Src/stm32f4xx_it.c **** } 106 .loc 1 124 3 view .LVU14 120:Core/Src/stm32f4xx_it.c **** { 107 .loc 1 120 9 view .LVU15 ARM GAS /tmp/ccdzv1TD.s page 5 108 0000 FEE7 b .L8 109 .cfi_endproc 110 .LFE242: 112 .section .text.UsageFault_Handler,"ax",%progbits 113 .align 1 114 .global UsageFault_Handler 115 .syntax unified 116 .thumb 117 .thumb_func 119 UsageFault_Handler: 120 .LFB243: 125:Core/Src/stm32f4xx_it.c **** } 126:Core/Src/stm32f4xx_it.c **** 127:Core/Src/stm32f4xx_it.c **** /** 128:Core/Src/stm32f4xx_it.c **** * @brief This function handles Undefined instruction or illegal state. 129:Core/Src/stm32f4xx_it.c **** */ 130:Core/Src/stm32f4xx_it.c **** void UsageFault_Handler(void) 131:Core/Src/stm32f4xx_it.c **** { 121 .loc 1 131 1 view -0 122 .cfi_startproc 123 @ Volatile: function does not return. 124 @ args = 0, pretend = 0, frame = 0 125 @ frame_needed = 0, uses_anonymous_args = 0 126 @ link register save eliminated. 127 .L10: 132:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN UsageFault_IRQn 0 */ 133:Core/Src/stm32f4xx_it.c **** 134:Core/Src/stm32f4xx_it.c **** /* USER CODE END UsageFault_IRQn 0 */ 135:Core/Src/stm32f4xx_it.c **** while (1) 128 .loc 1 135 3 view .LVU17 136:Core/Src/stm32f4xx_it.c **** { 137:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ 138:Core/Src/stm32f4xx_it.c **** /* USER CODE END W1_UsageFault_IRQn 0 */ 139:Core/Src/stm32f4xx_it.c **** } 129 .loc 1 139 3 view .LVU18 135:Core/Src/stm32f4xx_it.c **** { 130 .loc 1 135 9 view .LVU19 131 0000 FEE7 b .L10 132 .cfi_endproc 133 .LFE243: 135 .section .text.SVC_Handler,"ax",%progbits 136 .align 1 137 .global SVC_Handler 138 .syntax unified 139 .thumb 140 .thumb_func 142 SVC_Handler: 143 .LFB244: 140:Core/Src/stm32f4xx_it.c **** } 141:Core/Src/stm32f4xx_it.c **** 142:Core/Src/stm32f4xx_it.c **** /** 143:Core/Src/stm32f4xx_it.c **** * @brief This function handles System service call via SWI instruction. 144:Core/Src/stm32f4xx_it.c **** */ 145:Core/Src/stm32f4xx_it.c **** void SVC_Handler(void) 146:Core/Src/stm32f4xx_it.c **** { 144 .loc 1 146 1 view -0 145 .cfi_startproc ARM GAS /tmp/ccdzv1TD.s page 6 146 @ args = 0, pretend = 0, frame = 0 147 @ frame_needed = 0, uses_anonymous_args = 0 148 @ link register save eliminated. 147:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 0 */ 148:Core/Src/stm32f4xx_it.c **** 149:Core/Src/stm32f4xx_it.c **** /* USER CODE END SVCall_IRQn 0 */ 150:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 1 */ 151:Core/Src/stm32f4xx_it.c **** 152:Core/Src/stm32f4xx_it.c **** /* USER CODE END SVCall_IRQn 1 */ 153:Core/Src/stm32f4xx_it.c **** } 149 .loc 1 153 1 view .LVU21 150 0000 7047 bx lr 151 .cfi_endproc 152 .LFE244: 154 .section .text.DebugMon_Handler,"ax",%progbits 155 .align 1 156 .global DebugMon_Handler 157 .syntax unified 158 .thumb 159 .thumb_func 161 DebugMon_Handler: 162 .LFB245: 154:Core/Src/stm32f4xx_it.c **** 155:Core/Src/stm32f4xx_it.c **** /** 156:Core/Src/stm32f4xx_it.c **** * @brief This function handles Debug monitor. 157:Core/Src/stm32f4xx_it.c **** */ 158:Core/Src/stm32f4xx_it.c **** void DebugMon_Handler(void) 159:Core/Src/stm32f4xx_it.c **** { 163 .loc 1 159 1 view -0 164 .cfi_startproc 165 @ args = 0, pretend = 0, frame = 0 166 @ frame_needed = 0, uses_anonymous_args = 0 167 @ link register save eliminated. 160:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 0 */ 161:Core/Src/stm32f4xx_it.c **** 162:Core/Src/stm32f4xx_it.c **** /* USER CODE END DebugMonitor_IRQn 0 */ 163:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 1 */ 164:Core/Src/stm32f4xx_it.c **** 165:Core/Src/stm32f4xx_it.c **** /* USER CODE END DebugMonitor_IRQn 1 */ 166:Core/Src/stm32f4xx_it.c **** } 168 .loc 1 166 1 view .LVU23 169 0000 7047 bx lr 170 .cfi_endproc 171 .LFE245: 173 .section .text.PendSV_Handler,"ax",%progbits 174 .align 1 175 .global PendSV_Handler 176 .syntax unified 177 .thumb 178 .thumb_func 180 PendSV_Handler: 181 .LFB246: 167:Core/Src/stm32f4xx_it.c **** 168:Core/Src/stm32f4xx_it.c **** /** 169:Core/Src/stm32f4xx_it.c **** * @brief This function handles Pendable request for system service. 170:Core/Src/stm32f4xx_it.c **** */ 171:Core/Src/stm32f4xx_it.c **** void PendSV_Handler(void) ARM GAS /tmp/ccdzv1TD.s page 7 172:Core/Src/stm32f4xx_it.c **** { 182 .loc 1 172 1 view -0 183 .cfi_startproc 184 @ args = 0, pretend = 0, frame = 0 185 @ frame_needed = 0, uses_anonymous_args = 0 186 @ link register save eliminated. 173:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 0 */ 174:Core/Src/stm32f4xx_it.c **** 175:Core/Src/stm32f4xx_it.c **** /* USER CODE END PendSV_IRQn 0 */ 176:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 1 */ 177:Core/Src/stm32f4xx_it.c **** 178:Core/Src/stm32f4xx_it.c **** /* USER CODE END PendSV_IRQn 1 */ 179:Core/Src/stm32f4xx_it.c **** } 187 .loc 1 179 1 view .LVU25 188 0000 7047 bx lr 189 .cfi_endproc 190 .LFE246: 192 .section .text.SysTick_Handler,"ax",%progbits 193 .align 1 194 .global SysTick_Handler 195 .syntax unified 196 .thumb 197 .thumb_func 199 SysTick_Handler: 200 .LFB247: 180:Core/Src/stm32f4xx_it.c **** 181:Core/Src/stm32f4xx_it.c **** /** 182:Core/Src/stm32f4xx_it.c **** * @brief This function handles System tick timer. 183:Core/Src/stm32f4xx_it.c **** */ 184:Core/Src/stm32f4xx_it.c **** void SysTick_Handler(void) 185:Core/Src/stm32f4xx_it.c **** { 201 .loc 1 185 1 view -0 202 .cfi_startproc 203 @ args = 0, pretend = 0, frame = 0 204 @ frame_needed = 0, uses_anonymous_args = 0 205 0000 08B5 push {r3, lr} 206 .LCFI0: 207 .cfi_def_cfa_offset 8 208 .cfi_offset 3, -8 209 .cfi_offset 14, -4 186:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 0 */ 187:Core/Src/stm32f4xx_it.c **** 188:Core/Src/stm32f4xx_it.c **** /* USER CODE END SysTick_IRQn 0 */ 189:Core/Src/stm32f4xx_it.c **** HAL_IncTick(); 210 .loc 1 189 3 view .LVU27 211 0002 FFF7FEFF bl HAL_IncTick 212 .LVL0: 190:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 1 */ 191:Core/Src/stm32f4xx_it.c **** 192:Core/Src/stm32f4xx_it.c **** /* USER CODE END SysTick_IRQn 1 */ 193:Core/Src/stm32f4xx_it.c **** } 213 .loc 1 193 1 is_stmt 0 view .LVU28 214 0006 08BD pop {r3, pc} 215 .cfi_endproc 216 .LFE247: 218 .section .text.EXTI0_IRQHandler,"ax",%progbits 219 .align 1 ARM GAS /tmp/ccdzv1TD.s page 8 220 .global EXTI0_IRQHandler 221 .syntax unified 222 .thumb 223 .thumb_func 225 EXTI0_IRQHandler: 226 .LFB248: 194:Core/Src/stm32f4xx_it.c **** 195:Core/Src/stm32f4xx_it.c **** /******************************************************************************/ 196:Core/Src/stm32f4xx_it.c **** /* STM32F4xx Peripheral Interrupt Handlers */ 197:Core/Src/stm32f4xx_it.c **** /* Add here the Interrupt Handlers for the used peripherals. */ 198:Core/Src/stm32f4xx_it.c **** /* For the available peripheral interrupt handler names, */ 199:Core/Src/stm32f4xx_it.c **** /* please refer to the startup file (startup_stm32f4xx.s). */ 200:Core/Src/stm32f4xx_it.c **** /******************************************************************************/ 201:Core/Src/stm32f4xx_it.c **** 202:Core/Src/stm32f4xx_it.c **** /** 203:Core/Src/stm32f4xx_it.c **** * @brief This function handles EXTI line0 interrupt. 204:Core/Src/stm32f4xx_it.c **** */ 205:Core/Src/stm32f4xx_it.c **** void EXTI0_IRQHandler(void) 206:Core/Src/stm32f4xx_it.c **** { 227 .loc 1 206 1 is_stmt 1 view -0 228 .cfi_startproc 229 @ args = 0, pretend = 0, frame = 0 230 @ frame_needed = 0, uses_anonymous_args = 0 231 0000 08B5 push {r3, lr} 232 .LCFI1: 233 .cfi_def_cfa_offset 8 234 .cfi_offset 3, -8 235 .cfi_offset 14, -4 207:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN EXTI0_IRQn 0 */ 208:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_start_DMA_N = ADC_BUFF_SIZE - hdma_adc1.Instance->NDTR; 236 .loc 1 208 3 view .LVU30 237 .loc 1 208 64 is_stmt 0 view .LVU31 238 0002 0A4B ldr r3, .L20 239 0004 1B68 ldr r3, [r3] 240 .loc 1 208 73 view .LVU32 241 0006 5B68 ldr r3, [r3, #4] 242 .loc 1 208 53 view .LVU33 243 0008 C3F16403 rsb r3, r3, #100 244 .loc 1 208 37 view .LVU34 245 000c 084A ldr r2, .L20+4 246 000e 9360 str r3, [r2, #8] 209:Core/Src/stm32f4xx_it.c **** if (Sweep_state.curr_step_start_DMA_N < ADC_BUFF_SIZE/2) { 247 .loc 1 209 3 is_stmt 1 view .LVU35 248 .loc 1 209 18 is_stmt 0 view .LVU36 249 0010 9368 ldr r3, [r2, #8] 250 .loc 1 209 6 view .LVU37 251 0012 312B cmp r3, #49 252 0014 06D8 bhi .L17 210:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag =1; // first half DMA buffer 253 .loc 1 210 5 is_stmt 1 view .LVU38 254 .loc 1 210 40 is_stmt 0 view .LVU39 255 0016 1346 mov r3, r2 256 0018 0122 movs r2, #1 257 001a 1A71 strb r2, [r3, #4] 258 .L18: 211:Core/Src/stm32f4xx_it.c **** } else{ 212:Core/Src/stm32f4xx_it.c **** Sweep_state.curr_step_started_flag =2; // second half DMA buffer ARM GAS /tmp/ccdzv1TD.s page 9 213:Core/Src/stm32f4xx_it.c **** } 214:Core/Src/stm32f4xx_it.c **** /* USER CODE END EXTI0_IRQn 0 */ 215:Core/Src/stm32f4xx_it.c **** HAL_GPIO_EXTI_IRQHandler(CURR_STEP_START_TRG_Pin); 259 .loc 1 215 3 is_stmt 1 view .LVU40 260 001c 0120 movs r0, #1 261 001e FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler 262 .LVL1: 216:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN EXTI0_IRQn 1 */ 217:Core/Src/stm32f4xx_it.c **** 218:Core/Src/stm32f4xx_it.c **** /* USER CODE END EXTI0_IRQn 1 */ 219:Core/Src/stm32f4xx_it.c **** } 263 .loc 1 219 1 is_stmt 0 view .LVU41 264 0022 08BD pop {r3, pc} 265 .L17: 212:Core/Src/stm32f4xx_it.c **** } 266 .loc 1 212 5 is_stmt 1 view .LVU42 212:Core/Src/stm32f4xx_it.c **** } 267 .loc 1 212 40 is_stmt 0 view .LVU43 268 0024 024B ldr r3, .L20+4 269 0026 0222 movs r2, #2 270 0028 1A71 strb r2, [r3, #4] 271 002a F7E7 b .L18 272 .L21: 273 .align 2 274 .L20: 275 002c 00000000 .word hdma_adc1 276 0030 00000000 .word Sweep_state 277 .cfi_endproc 278 .LFE248: 280 .section .text.EXTI3_IRQHandler,"ax",%progbits 281 .align 1 282 .global EXTI3_IRQHandler 283 .syntax unified 284 .thumb 285 .thumb_func 287 EXTI3_IRQHandler: 288 .LFB249: 220:Core/Src/stm32f4xx_it.c **** 221:Core/Src/stm32f4xx_it.c **** /** 222:Core/Src/stm32f4xx_it.c **** * @brief This function handles EXTI line3 interrupt. 223:Core/Src/stm32f4xx_it.c **** */ 224:Core/Src/stm32f4xx_it.c **** void EXTI3_IRQHandler(void) 225:Core/Src/stm32f4xx_it.c **** { 289 .loc 1 225 1 is_stmt 1 view -0 290 .cfi_startproc 291 @ args = 0, pretend = 0, frame = 0 292 @ frame_needed = 0, uses_anonymous_args = 0 293 0000 08B5 push {r3, lr} 294 .LCFI2: 295 .cfi_def_cfa_offset 8 296 .cfi_offset 3, -8 297 .cfi_offset 14, -4 226:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN EXTI3_IRQn 0 */ 227:Core/Src/stm32f4xx_it.c **** 228:Core/Src/stm32f4xx_it.c **** /* USER CODE END EXTI3_IRQn 0 */ 229:Core/Src/stm32f4xx_it.c **** HAL_GPIO_EXTI_IRQHandler(SWEEP_CYCLE_START_TRG_Pin); 298 .loc 1 229 3 view .LVU45 ARM GAS /tmp/ccdzv1TD.s page 10 299 0002 0220 movs r0, #2 300 0004 FFF7FEFF bl HAL_GPIO_EXTI_IRQHandler 301 .LVL2: 230:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN EXTI3_IRQn 1 */ 231:Core/Src/stm32f4xx_it.c **** 232:Core/Src/stm32f4xx_it.c **** /* USER CODE END EXTI3_IRQn 1 */ 233:Core/Src/stm32f4xx_it.c **** } 302 .loc 1 233 1 is_stmt 0 view .LVU46 303 0008 08BD pop {r3, pc} 304 .cfi_endproc 305 .LFE249: 307 .section .text.DMA2_Stream0_IRQHandler,"ax",%progbits 308 .align 1 309 .global DMA2_Stream0_IRQHandler 310 .syntax unified 311 .thumb 312 .thumb_func 314 DMA2_Stream0_IRQHandler: 315 .LFB250: 234:Core/Src/stm32f4xx_it.c **** 235:Core/Src/stm32f4xx_it.c **** /** 236:Core/Src/stm32f4xx_it.c **** * @brief This function handles DMA2 stream0 global interrupt. 237:Core/Src/stm32f4xx_it.c **** */ 238:Core/Src/stm32f4xx_it.c **** void DMA2_Stream0_IRQHandler(void) 239:Core/Src/stm32f4xx_it.c **** { 316 .loc 1 239 1 is_stmt 1 view -0 317 .cfi_startproc 318 @ args = 0, pretend = 0, frame = 0 319 @ frame_needed = 0, uses_anonymous_args = 0 320 0000 08B5 push {r3, lr} 321 .LCFI3: 322 .cfi_def_cfa_offset 8 323 .cfi_offset 3, -8 324 .cfi_offset 14, -4 240:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN DMA2_Stream0_IRQn 0 */ 241:Core/Src/stm32f4xx_it.c **** 242:Core/Src/stm32f4xx_it.c **** /* USER CODE END DMA2_Stream0_IRQn 0 */ 243:Core/Src/stm32f4xx_it.c **** HAL_DMA_IRQHandler(&hdma_adc1); 325 .loc 1 243 3 view .LVU48 326 0002 0248 ldr r0, .L26 327 0004 FFF7FEFF bl HAL_DMA_IRQHandler 328 .LVL3: 244:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN DMA2_Stream0_IRQn 1 */ 245:Core/Src/stm32f4xx_it.c **** 246:Core/Src/stm32f4xx_it.c **** /* USER CODE END DMA2_Stream0_IRQn 1 */ 247:Core/Src/stm32f4xx_it.c **** } 329 .loc 1 247 1 is_stmt 0 view .LVU49 330 0008 08BD pop {r3, pc} 331 .L27: 332 000a 00BF .align 2 333 .L26: 334 000c 00000000 .word hdma_adc1 335 .cfi_endproc 336 .LFE250: 338 .section .text.OTG_FS_IRQHandler,"ax",%progbits 339 .align 1 340 .global OTG_FS_IRQHandler ARM GAS /tmp/ccdzv1TD.s page 11 341 .syntax unified 342 .thumb 343 .thumb_func 345 OTG_FS_IRQHandler: 346 .LFB251: 248:Core/Src/stm32f4xx_it.c **** 249:Core/Src/stm32f4xx_it.c **** /** 250:Core/Src/stm32f4xx_it.c **** * @brief This function handles USB On The Go FS global interrupt. 251:Core/Src/stm32f4xx_it.c **** */ 252:Core/Src/stm32f4xx_it.c **** void OTG_FS_IRQHandler(void) 253:Core/Src/stm32f4xx_it.c **** { 347 .loc 1 253 1 is_stmt 1 view -0 348 .cfi_startproc 349 @ args = 0, pretend = 0, frame = 0 350 @ frame_needed = 0, uses_anonymous_args = 0 351 0000 08B5 push {r3, lr} 352 .LCFI4: 353 .cfi_def_cfa_offset 8 354 .cfi_offset 3, -8 355 .cfi_offset 14, -4 254:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN OTG_FS_IRQn 0 */ 255:Core/Src/stm32f4xx_it.c **** 256:Core/Src/stm32f4xx_it.c **** /* USER CODE END OTG_FS_IRQn 0 */ 257:Core/Src/stm32f4xx_it.c **** HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); 356 .loc 1 257 3 view .LVU51 357 0002 0248 ldr r0, .L30 358 0004 FFF7FEFF bl HAL_PCD_IRQHandler 359 .LVL4: 258:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN OTG_FS_IRQn 1 */ 259:Core/Src/stm32f4xx_it.c **** 260:Core/Src/stm32f4xx_it.c **** /* USER CODE END OTG_FS_IRQn 1 */ 261:Core/Src/stm32f4xx_it.c **** } 360 .loc 1 261 1 is_stmt 0 view .LVU52 361 0008 08BD pop {r3, pc} 362 .L31: 363 000a 00BF .align 2 364 .L30: 365 000c 00000000 .word hpcd_USB_OTG_FS 366 .cfi_endproc 367 .LFE251: 369 .section .text.HAL_ADC_ConvCpltCallback,"ax",%progbits 370 .align 1 371 .global HAL_ADC_ConvCpltCallback 372 .syntax unified 373 .thumb 374 .thumb_func 376 HAL_ADC_ConvCpltCallback: 377 .LVL5: 378 .LFB252: 262:Core/Src/stm32f4xx_it.c **** 263:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN 1 */ 264:Core/Src/stm32f4xx_it.c **** 265:Core/Src/stm32f4xx_it.c **** void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) 266:Core/Src/stm32f4xx_it.c **** { 379 .loc 1 266 1 is_stmt 1 view -0 380 .cfi_startproc 381 @ args = 0, pretend = 0, frame = 0 ARM GAS /tmp/ccdzv1TD.s page 12 382 @ frame_needed = 0, uses_anonymous_args = 0 383 .loc 1 266 1 is_stmt 0 view .LVU54 384 0000 08B5 push {r3, lr} 385 .LCFI5: 386 .cfi_def_cfa_offset 8 387 .cfi_offset 3, -8 388 .cfi_offset 14, -4 267:Core/Src/stm32f4xx_it.c **** HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_SET); 389 .loc 1 267 3 is_stmt 1 view .LVU55 390 0002 0122 movs r2, #1 391 0004 8021 movs r1, #128 392 0006 3348 ldr r0, .L43 393 .LVL6: 394 .loc 1 267 3 is_stmt 0 view .LVU56 395 0008 FFF7FEFF bl HAL_GPIO_WritePin 396 .LVL7: 268:Core/Src/stm32f4xx_it.c **** 269:Core/Src/stm32f4xx_it.c **** if (Sweep_state.curr_step_started_flag == 2) { 397 .loc 1 269 3 is_stmt 1 view .LVU57 398 .loc 1 269 18 is_stmt 0 view .LVU58 399 000c 324B ldr r3, .L43+4 400 000e 1B79 ldrb r3, [r3, #4] @ zero_extendqisi2 401 0010 DBB2 uxtb r3, r3 402 .loc 1 269 6 view .LVU59 403 0012 022B cmp r3, #2 404 0014 25D0 beq .L41 405 .LBB2: 270:Core/Src/stm32f4xx_it.c **** for (uint32_t i = ADC_BUFF_SIZE/2; i < Sweep_state.curr_step_start_DMA_N; i++) { 271:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 272:Core/Src/stm32f4xx_it.c **** } 273:Core/Src/stm32f4xx_it.c **** 274:Core/Src/stm32f4xx_it.c **** ADC_proc.N += Sweep_state.curr_step_start_DMA_N - ADC_BUFF_SIZE/2; 275:Core/Src/stm32f4xx_it.c **** 276:Core/Src/stm32f4xx_it.c **** 277:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum = ADC_proc.sum; 278:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg = ADC_proc.avg; 279:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N; 280:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled 281:Core/Src/stm32f4xx_it.c **** 282:Core/Src/stm32f4xx_it.c **** 283:Core/Src/stm32f4xx_it.c **** ADC_proc.sum = 0; 284:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0; 285:Core/Src/stm32f4xx_it.c **** ADC_proc.avg = 0; 286:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data 287:Core/Src/stm32f4xx_it.c **** 288:Core/Src/stm32f4xx_it.c **** for (uint32_t i = Sweep_state.curr_step_start_DMA_N; i < ADC_BUFF_SIZE; i++) { 289:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 290:Core/Src/stm32f4xx_it.c **** } 291:Core/Src/stm32f4xx_it.c **** ADC_proc.N = ADC_BUFF_SIZE - Sweep_state.curr_step_start_DMA_N; 292:Core/Src/stm32f4xx_it.c **** 293:Core/Src/stm32f4xx_it.c **** 294:Core/Src/stm32f4xx_it.c **** }else{ 295:Core/Src/stm32f4xx_it.c **** for (uint32_t i = ADC_BUFF_SIZE/2; i < ADC_BUFF_SIZE; i++) { 406 .loc 1 295 19 view .LVU60 407 0016 3223 movs r3, #50 408 0018 3EE0 b .L34 409 .LVL8: ARM GAS /tmp/ccdzv1TD.s page 13 410 .L35: 411 .loc 1 295 19 view .LVU61 412 .LBE2: 413 .LBB3: 271:Core/Src/stm32f4xx_it.c **** } 414 .loc 1 271 7 is_stmt 1 view .LVU62 271:Core/Src/stm32f4xx_it.c **** } 415 .loc 1 271 15 is_stmt 0 view .LVU63 416 001a 3049 ldr r1, .L43+8 417 001c 4A68 ldr r2, [r1, #4] 271:Core/Src/stm32f4xx_it.c **** } 418 .loc 1 271 41 view .LVU64 419 001e 3048 ldr r0, .L43+12 420 0020 30F81300 ldrh r0, [r0, r3, lsl #1] 271:Core/Src/stm32f4xx_it.c **** } 421 .loc 1 271 20 view .LVU65 422 0024 0244 add r2, r2, r0 423 0026 4A60 str r2, [r1, #4] 270:Core/Src/stm32f4xx_it.c **** for (uint32_t i = ADC_BUFF_SIZE/2; i < Sweep_state.curr_step_start_DMA_N; i++) { 424 .loc 1 270 80 is_stmt 1 discriminator 3 view .LVU66 425 0028 0133 adds r3, r3, #1 426 .LVL9: 427 .L33: 270:Core/Src/stm32f4xx_it.c **** for (uint32_t i = ADC_BUFF_SIZE/2; i < Sweep_state.curr_step_start_DMA_N; i++) { 428 .loc 1 270 42 discriminator 1 view .LVU67 270:Core/Src/stm32f4xx_it.c **** for (uint32_t i = ADC_BUFF_SIZE/2; i < Sweep_state.curr_step_start_DMA_N; i++) { 429 .loc 1 270 55 is_stmt 0 discriminator 1 view .LVU68 430 002a 2B4A ldr r2, .L43+4 431 002c 9268 ldr r2, [r2, #8] 270:Core/Src/stm32f4xx_it.c **** for (uint32_t i = ADC_BUFF_SIZE/2; i < Sweep_state.curr_step_start_DMA_N; i++) { 432 .loc 1 270 42 discriminator 1 view .LVU69 433 002e 9A42 cmp r2, r3 434 0030 F3D8 bhi .L35 435 .LBE3: 274:Core/Src/stm32f4xx_it.c **** 436 .loc 1 274 5 is_stmt 1 view .LVU70 274:Core/Src/stm32f4xx_it.c **** 437 .loc 1 274 30 is_stmt 0 view .LVU71 438 0032 2948 ldr r0, .L43+4 439 0034 8168 ldr r1, [r0, #8] 274:Core/Src/stm32f4xx_it.c **** 440 .loc 1 274 53 view .LVU72 441 0036 3239 subs r1, r1, #50 274:Core/Src/stm32f4xx_it.c **** 442 .loc 1 274 13 view .LVU73 443 0038 284B ldr r3, .L43+8 444 .LVL10: 274:Core/Src/stm32f4xx_it.c **** 445 .loc 1 274 13 view .LVU74 446 003a DA68 ldr r2, [r3, #12] 274:Core/Src/stm32f4xx_it.c **** 447 .loc 1 274 16 view .LVU75 448 003c 0A44 add r2, r2, r1 449 003e DA60 str r2, [r3, #12] 277:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg = ADC_proc.avg; 450 .loc 1 277 5 is_stmt 1 view .LVU76 277:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg = ADC_proc.avg; ARM GAS /tmp/ccdzv1TD.s page 14 451 .loc 1 277 35 is_stmt 0 view .LVU77 452 0040 5968 ldr r1, [r3, #4] 277:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg = ADC_proc.avg; 453 .loc 1 277 25 view .LVU78 454 0042 284A ldr r2, .L43+16 455 0044 5160 str r1, [r2, #4] 278:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N; 456 .loc 1 278 5 is_stmt 1 view .LVU79 278:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N; 457 .loc 1 278 35 is_stmt 0 view .LVU80 458 0046 9968 ldr r1, [r3, #8] 278:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N; 459 .loc 1 278 25 view .LVU81 460 0048 9160 str r1, [r2, #8] 279:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled 461 .loc 1 279 5 is_stmt 1 view .LVU82 279:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled 462 .loc 1 279 33 is_stmt 0 view .LVU83 463 004a D968 ldr r1, [r3, #12] 279:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled 464 .loc 1 279 23 view .LVU84 465 004c D160 str r1, [r2, #12] 280:Core/Src/stm32f4xx_it.c **** 466 .loc 1 280 5 is_stmt 1 view .LVU85 280:Core/Src/stm32f4xx_it.c **** 467 .loc 1 280 28 is_stmt 0 view .LVU86 468 004e 0221 movs r1, #2 469 0050 1170 strb r1, [r2] 283:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0; 470 .loc 1 283 5 is_stmt 1 view .LVU87 283:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0; 471 .loc 1 283 18 is_stmt 0 view .LVU88 472 0052 0022 movs r2, #0 473 0054 5A60 str r2, [r3, #4] 284:Core/Src/stm32f4xx_it.c **** ADC_proc.avg = 0; 474 .loc 1 284 5 is_stmt 1 view .LVU89 284:Core/Src/stm32f4xx_it.c **** ADC_proc.avg = 0; 475 .loc 1 284 16 is_stmt 0 view .LVU90 476 0056 DA60 str r2, [r3, #12] 285:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data 477 .loc 1 285 5 is_stmt 1 view .LVU91 285:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data 478 .loc 1 285 18 is_stmt 0 view .LVU92 479 0058 9A60 str r2, [r3, #8] 286:Core/Src/stm32f4xx_it.c **** 480 .loc 1 286 5 is_stmt 1 view .LVU93 286:Core/Src/stm32f4xx_it.c **** 481 .loc 1 286 21 is_stmt 0 view .LVU94 482 005a 0122 movs r2, #1 483 005c 1A70 strb r2, [r3] 288:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 484 .loc 1 288 5 is_stmt 1 view .LVU95 485 .LBB4: 288:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 486 .loc 1 288 10 view .LVU96 288:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 487 .loc 1 288 19 is_stmt 0 view .LVU97 ARM GAS /tmp/ccdzv1TD.s page 15 488 005e 8368 ldr r3, [r0, #8] 489 .LVL11: 288:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 490 .loc 1 288 5 view .LVU98 491 0060 09E0 b .L36 492 .LVL12: 493 .L41: 288:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 494 .loc 1 288 5 view .LVU99 495 .LBE4: 496 .LBB5: 270:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 497 .loc 1 270 19 view .LVU100 498 0062 3223 movs r3, #50 499 0064 E1E7 b .L33 500 .LVL13: 501 .L37: 270:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 502 .loc 1 270 19 view .LVU101 503 .LBE5: 504 .LBB6: 289:Core/Src/stm32f4xx_it.c **** } 505 .loc 1 289 7 is_stmt 1 view .LVU102 289:Core/Src/stm32f4xx_it.c **** } 506 .loc 1 289 15 is_stmt 0 view .LVU103 507 0066 1D49 ldr r1, .L43+8 508 0068 4A68 ldr r2, [r1, #4] 289:Core/Src/stm32f4xx_it.c **** } 509 .loc 1 289 41 view .LVU104 510 006a 1D48 ldr r0, .L43+12 511 006c 30F81300 ldrh r0, [r0, r3, lsl #1] 289:Core/Src/stm32f4xx_it.c **** } 512 .loc 1 289 20 view .LVU105 513 0070 0244 add r2, r2, r0 514 0072 4A60 str r2, [r1, #4] 288:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 515 .loc 1 288 78 is_stmt 1 discriminator 3 view .LVU106 516 0074 0133 adds r3, r3, #1 517 .LVL14: 518 .L36: 288:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 519 .loc 1 288 60 discriminator 1 view .LVU107 520 0076 632B cmp r3, #99 521 0078 F5D9 bls .L37 288:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 522 .loc 1 288 60 is_stmt 0 discriminator 1 view .LVU108 523 .LBE6: 291:Core/Src/stm32f4xx_it.c **** 524 .loc 1 291 5 is_stmt 1 view .LVU109 291:Core/Src/stm32f4xx_it.c **** 525 .loc 1 291 45 is_stmt 0 view .LVU110 526 007a 174B ldr r3, .L43+4 527 .LVL15: 291:Core/Src/stm32f4xx_it.c **** 528 .loc 1 291 45 view .LVU111 529 007c 9B68 ldr r3, [r3, #8] 291:Core/Src/stm32f4xx_it.c **** ARM GAS /tmp/ccdzv1TD.s page 16 530 .loc 1 291 32 view .LVU112 531 007e C3F16403 rsb r3, r3, #100 291:Core/Src/stm32f4xx_it.c **** 532 .loc 1 291 16 view .LVU113 533 0082 164A ldr r2, .L43+8 534 0084 D360 str r3, [r2, #12] 535 0086 0DE0 b .L38 536 .LVL16: 537 .L39: 538 .LBB7: 296:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 539 .loc 1 296 7 is_stmt 1 view .LVU114 540 .loc 1 296 15 is_stmt 0 view .LVU115 541 0088 1449 ldr r1, .L43+8 542 008a 4A68 ldr r2, [r1, #4] 543 .loc 1 296 41 view .LVU116 544 008c 1448 ldr r0, .L43+12 545 008e 30F81300 ldrh r0, [r0, r3, lsl #1] 546 .loc 1 296 20 view .LVU117 547 0092 0244 add r2, r2, r0 548 0094 4A60 str r2, [r1, #4] 295:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 549 .loc 1 295 60 is_stmt 1 discriminator 3 view .LVU118 550 0096 0133 adds r3, r3, #1 551 .LVL17: 552 .L34: 295:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 553 .loc 1 295 42 discriminator 1 view .LVU119 554 0098 632B cmp r3, #99 555 009a F5D9 bls .L39 556 .LBE7: 297:Core/Src/stm32f4xx_it.c **** } 298:Core/Src/stm32f4xx_it.c **** ADC_proc.N += ADC_BUFF_SIZE - ADC_BUFF_SIZE/2; 557 .loc 1 298 5 view .LVU120 558 .loc 1 298 13 is_stmt 0 view .LVU121 559 009c 0F4A ldr r2, .L43+8 560 009e D368 ldr r3, [r2, #12] 561 .LVL18: 562 .loc 1 298 16 view .LVU122 563 00a0 3233 adds r3, r3, #50 564 00a2 D360 str r3, [r2, #12] 565 .LVL19: 566 .L38: 299:Core/Src/stm32f4xx_it.c **** } 300:Core/Src/stm32f4xx_it.c **** if (ADC_proc.N >= ADC_BUFF_SIZE*100){ 567 .loc 1 300 3 is_stmt 1 view .LVU123 568 .loc 1 300 15 is_stmt 0 view .LVU124 569 00a4 0D4B ldr r3, .L43+8 570 00a6 DA68 ldr r2, [r3, #12] 571 .loc 1 300 6 view .LVU125 572 00a8 42F20F73 movw r3, #9999 573 00ac 9A42 cmp r2, r3 574 00ae 0FD9 bls .L32 301:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum = ADC_proc.sum; 575 .loc 1 301 5 is_stmt 1 view .LVU126 576 .loc 1 301 35 is_stmt 0 view .LVU127 577 00b0 0A4B ldr r3, .L43+8 ARM GAS /tmp/ccdzv1TD.s page 17 578 00b2 5968 ldr r1, [r3, #4] 579 .loc 1 301 25 view .LVU128 580 00b4 0B4A ldr r2, .L43+16 581 00b6 5160 str r1, [r2, #4] 302:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg = ADC_proc.avg; 582 .loc 1 302 5 is_stmt 1 view .LVU129 583 .loc 1 302 35 is_stmt 0 view .LVU130 584 00b8 9968 ldr r1, [r3, #8] 585 .loc 1 302 25 view .LVU131 586 00ba 9160 str r1, [r2, #8] 303:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N; 587 .loc 1 303 5 is_stmt 1 view .LVU132 588 .loc 1 303 33 is_stmt 0 view .LVU133 589 00bc D968 ldr r1, [r3, #12] 590 .loc 1 303 23 view .LVU134 591 00be D160 str r1, [r2, #12] 304:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled 592 .loc 1 304 5 is_stmt 1 view .LVU135 593 .loc 1 304 28 is_stmt 0 view .LVU136 594 00c0 0221 movs r1, #2 595 00c2 1170 strb r1, [r2] 305:Core/Src/stm32f4xx_it.c **** 306:Core/Src/stm32f4xx_it.c **** 307:Core/Src/stm32f4xx_it.c **** ADC_proc.sum = 0; 596 .loc 1 307 5 is_stmt 1 view .LVU137 597 .loc 1 307 18 is_stmt 0 view .LVU138 598 00c4 0022 movs r2, #0 599 00c6 5A60 str r2, [r3, #4] 308:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0; 600 .loc 1 308 5 is_stmt 1 view .LVU139 601 .loc 1 308 16 is_stmt 0 view .LVU140 602 00c8 DA60 str r2, [r3, #12] 309:Core/Src/stm32f4xx_it.c **** ADC_proc.avg = 0; 603 .loc 1 309 5 is_stmt 1 view .LVU141 604 .loc 1 309 18 is_stmt 0 view .LVU142 605 00ca 9A60 str r2, [r3, #8] 310:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data 606 .loc 1 310 5 is_stmt 1 view .LVU143 607 .loc 1 310 21 is_stmt 0 view .LVU144 608 00cc 0122 movs r2, #1 609 00ce 1A70 strb r2, [r3] 610 .L32: 311:Core/Src/stm32f4xx_it.c **** } 312:Core/Src/stm32f4xx_it.c **** // This function is called when the first half of the ADC buffer is filled 313:Core/Src/stm32f4xx_it.c **** // You can process the first half of ADC1_buff_circular here 314:Core/Src/stm32f4xx_it.c **** } 611 .loc 1 314 1 view .LVU145 612 00d0 08BD pop {r3, pc} 613 .L44: 614 00d2 00BF .align 2 615 .L43: 616 00d4 00040240 .word 1073873920 617 00d8 00000000 .word Sweep_state 618 00dc 00000000 .word ADC_proc 619 00e0 00000000 .word ADC1_buff_circular 620 00e4 00000000 .word ADC_proc_shadow 621 .cfi_endproc ARM GAS /tmp/ccdzv1TD.s page 18 622 .LFE252: 624 .section .text.HAL_ADC_ConvHalfCpltCallback,"ax",%progbits 625 .align 1 626 .global HAL_ADC_ConvHalfCpltCallback 627 .syntax unified 628 .thumb 629 .thumb_func 631 HAL_ADC_ConvHalfCpltCallback: 632 .LVL20: 633 .LFB253: 315:Core/Src/stm32f4xx_it.c **** 316:Core/Src/stm32f4xx_it.c **** void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) 317:Core/Src/stm32f4xx_it.c **** { 634 .loc 1 317 1 is_stmt 1 view -0 635 .cfi_startproc 636 @ args = 0, pretend = 0, frame = 0 637 @ frame_needed = 0, uses_anonymous_args = 0 638 .loc 1 317 1 is_stmt 0 view .LVU147 639 0000 08B5 push {r3, lr} 640 .LCFI6: 641 .cfi_def_cfa_offset 8 642 .cfi_offset 3, -8 643 .cfi_offset 14, -4 318:Core/Src/stm32f4xx_it.c **** //HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_RESET); 319:Core/Src/stm32f4xx_it.c **** 320:Core/Src/stm32f4xx_it.c **** HAL_GPIO_TogglePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin); 644 .loc 1 320 3 is_stmt 1 view .LVU148 645 0002 8021 movs r1, #128 646 0004 2648 ldr r0, .L55 647 .LVL21: 648 .loc 1 320 3 is_stmt 0 view .LVU149 649 0006 FFF7FEFF bl HAL_GPIO_TogglePin 650 .LVL22: 321:Core/Src/stm32f4xx_it.c **** if (Sweep_state.curr_step_started_flag == 1) { 651 .loc 1 321 3 is_stmt 1 view .LVU150 652 .loc 1 321 18 is_stmt 0 view .LVU151 653 000a 264B ldr r3, .L55+4 654 000c 1B79 ldrb r3, [r3, #4] @ zero_extendqisi2 655 000e DBB2 uxtb r3, r3 656 .loc 1 321 6 view .LVU152 657 0010 012B cmp r3, #1 658 0012 24D0 beq .L53 659 .LBB8: 322:Core/Src/stm32f4xx_it.c **** for (uint32_t i = 0; i < Sweep_state.curr_step_start_DMA_N; i++) { 323:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 324:Core/Src/stm32f4xx_it.c **** } 325:Core/Src/stm32f4xx_it.c **** 326:Core/Src/stm32f4xx_it.c **** ADC_proc.N += Sweep_state.curr_step_start_DMA_N; 327:Core/Src/stm32f4xx_it.c **** 328:Core/Src/stm32f4xx_it.c **** 329:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.sum = ADC_proc.sum; 330:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg = ADC_proc.avg; 331:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N; 332:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled 333:Core/Src/stm32f4xx_it.c **** 334:Core/Src/stm32f4xx_it.c **** 335:Core/Src/stm32f4xx_it.c **** ADC_proc.sum = 0; ARM GAS /tmp/ccdzv1TD.s page 19 336:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0; 337:Core/Src/stm32f4xx_it.c **** ADC_proc.avg = 0; 338:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data 339:Core/Src/stm32f4xx_it.c **** 340:Core/Src/stm32f4xx_it.c **** for (uint32_t i = Sweep_state.curr_step_start_DMA_N; i < ADC_BUFF_SIZE/2; i++) { 341:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 342:Core/Src/stm32f4xx_it.c **** } 343:Core/Src/stm32f4xx_it.c **** ADC_proc.N = Sweep_state.curr_step_start_DMA_N; 344:Core/Src/stm32f4xx_it.c **** 345:Core/Src/stm32f4xx_it.c **** }else{ 346:Core/Src/stm32f4xx_it.c **** for (uint32_t i = 0; i < ADC_BUFF_SIZE/2; i++) { 660 .loc 1 346 19 view .LVU153 661 0014 0023 movs r3, #0 662 0016 3BE0 b .L47 663 .LVL23: 664 .L48: 665 .loc 1 346 19 view .LVU154 666 .LBE8: 667 .LBB9: 323:Core/Src/stm32f4xx_it.c **** } 668 .loc 1 323 7 is_stmt 1 view .LVU155 323:Core/Src/stm32f4xx_it.c **** } 669 .loc 1 323 15 is_stmt 0 view .LVU156 670 0018 2349 ldr r1, .L55+8 671 001a 4A68 ldr r2, [r1, #4] 323:Core/Src/stm32f4xx_it.c **** } 672 .loc 1 323 41 view .LVU157 673 001c 2348 ldr r0, .L55+12 674 001e 30F81300 ldrh r0, [r0, r3, lsl #1] 323:Core/Src/stm32f4xx_it.c **** } 675 .loc 1 323 20 view .LVU158 676 0022 0244 add r2, r2, r0 677 0024 4A60 str r2, [r1, #4] 322:Core/Src/stm32f4xx_it.c **** for (uint32_t i = 0; i < Sweep_state.curr_step_start_DMA_N; i++) { 678 .loc 1 322 66 is_stmt 1 discriminator 3 view .LVU159 679 0026 0133 adds r3, r3, #1 680 .LVL24: 681 .L46: 322:Core/Src/stm32f4xx_it.c **** for (uint32_t i = 0; i < Sweep_state.curr_step_start_DMA_N; i++) { 682 .loc 1 322 28 discriminator 1 view .LVU160 322:Core/Src/stm32f4xx_it.c **** for (uint32_t i = 0; i < Sweep_state.curr_step_start_DMA_N; i++) { 683 .loc 1 322 41 is_stmt 0 discriminator 1 view .LVU161 684 0028 1E4A ldr r2, .L55+4 685 002a 9268 ldr r2, [r2, #8] 322:Core/Src/stm32f4xx_it.c **** for (uint32_t i = 0; i < Sweep_state.curr_step_start_DMA_N; i++) { 686 .loc 1 322 28 discriminator 1 view .LVU162 687 002c 9A42 cmp r2, r3 688 002e F3D8 bhi .L48 689 .LBE9: 326:Core/Src/stm32f4xx_it.c **** 690 .loc 1 326 5 is_stmt 1 view .LVU163 326:Core/Src/stm32f4xx_it.c **** 691 .loc 1 326 30 is_stmt 0 view .LVU164 692 0030 1C49 ldr r1, .L55+4 693 0032 8868 ldr r0, [r1, #8] 326:Core/Src/stm32f4xx_it.c **** 694 .loc 1 326 13 view .LVU165 ARM GAS /tmp/ccdzv1TD.s page 20 695 0034 1C4B ldr r3, .L55+8 696 .LVL25: 326:Core/Src/stm32f4xx_it.c **** 697 .loc 1 326 13 view .LVU166 698 0036 DA68 ldr r2, [r3, #12] 326:Core/Src/stm32f4xx_it.c **** 699 .loc 1 326 16 view .LVU167 700 0038 0244 add r2, r2, r0 701 003a DA60 str r2, [r3, #12] 329:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg = ADC_proc.avg; 702 .loc 1 329 5 is_stmt 1 view .LVU168 329:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg = ADC_proc.avg; 703 .loc 1 329 35 is_stmt 0 view .LVU169 704 003c 5868 ldr r0, [r3, #4] 329:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.avg = ADC_proc.avg; 705 .loc 1 329 25 view .LVU170 706 003e 1C4A ldr r2, .L55+16 707 0040 5060 str r0, [r2, #4] 330:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N; 708 .loc 1 330 5 is_stmt 1 view .LVU171 330:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N; 709 .loc 1 330 35 is_stmt 0 view .LVU172 710 0042 9868 ldr r0, [r3, #8] 330:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.N = ADC_proc.N; 711 .loc 1 330 25 view .LVU173 712 0044 9060 str r0, [r2, #8] 331:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled 713 .loc 1 331 5 is_stmt 1 view .LVU174 331:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled 714 .loc 1 331 33 is_stmt 0 view .LVU175 715 0046 D868 ldr r0, [r3, #12] 331:Core/Src/stm32f4xx_it.c **** ADC_proc_shadow.status = 2; // buffer filled 716 .loc 1 331 23 view .LVU176 717 0048 D060 str r0, [r2, #12] 332:Core/Src/stm32f4xx_it.c **** 718 .loc 1 332 5 is_stmt 1 view .LVU177 332:Core/Src/stm32f4xx_it.c **** 719 .loc 1 332 28 is_stmt 0 view .LVU178 720 004a 0220 movs r0, #2 721 004c 1070 strb r0, [r2] 335:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0; 722 .loc 1 335 5 is_stmt 1 view .LVU179 335:Core/Src/stm32f4xx_it.c **** ADC_proc.N = 0; 723 .loc 1 335 18 is_stmt 0 view .LVU180 724 004e 0022 movs r2, #0 725 0050 5A60 str r2, [r3, #4] 336:Core/Src/stm32f4xx_it.c **** ADC_proc.avg = 0; 726 .loc 1 336 5 is_stmt 1 view .LVU181 336:Core/Src/stm32f4xx_it.c **** ADC_proc.avg = 0; 727 .loc 1 336 16 is_stmt 0 view .LVU182 728 0052 DA60 str r2, [r3, #12] 337:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data 729 .loc 1 337 5 is_stmt 1 view .LVU183 337:Core/Src/stm32f4xx_it.c **** ADC_proc.status = 1; // collecting data 730 .loc 1 337 18 is_stmt 0 view .LVU184 731 0054 9A60 str r2, [r3, #8] 338:Core/Src/stm32f4xx_it.c **** ARM GAS /tmp/ccdzv1TD.s page 21 732 .loc 1 338 5 is_stmt 1 view .LVU185 338:Core/Src/stm32f4xx_it.c **** 733 .loc 1 338 21 is_stmt 0 view .LVU186 734 0056 0122 movs r2, #1 735 0058 1A70 strb r2, [r3] 340:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 736 .loc 1 340 5 is_stmt 1 view .LVU187 737 .LBB10: 340:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 738 .loc 1 340 10 view .LVU188 340:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 739 .loc 1 340 19 is_stmt 0 view .LVU189 740 005a 8B68 ldr r3, [r1, #8] 741 .LVL26: 340:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 742 .loc 1 340 5 view .LVU190 743 005c 09E0 b .L49 744 .LVL27: 745 .L53: 340:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 746 .loc 1 340 5 view .LVU191 747 .LBE10: 748 .LBB11: 322:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 749 .loc 1 322 19 view .LVU192 750 005e 0023 movs r3, #0 751 0060 E2E7 b .L46 752 .LVL28: 753 .L50: 322:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 754 .loc 1 322 19 view .LVU193 755 .LBE11: 756 .LBB12: 341:Core/Src/stm32f4xx_it.c **** } 757 .loc 1 341 7 is_stmt 1 view .LVU194 341:Core/Src/stm32f4xx_it.c **** } 758 .loc 1 341 15 is_stmt 0 view .LVU195 759 0062 1149 ldr r1, .L55+8 760 0064 4A68 ldr r2, [r1, #4] 341:Core/Src/stm32f4xx_it.c **** } 761 .loc 1 341 41 view .LVU196 762 0066 1148 ldr r0, .L55+12 763 0068 30F81300 ldrh r0, [r0, r3, lsl #1] 341:Core/Src/stm32f4xx_it.c **** } 764 .loc 1 341 20 view .LVU197 765 006c 0244 add r2, r2, r0 766 006e 4A60 str r2, [r1, #4] 340:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 767 .loc 1 340 80 is_stmt 1 discriminator 3 view .LVU198 768 0070 0133 adds r3, r3, #1 769 .LVL29: 770 .L49: 340:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 771 .loc 1 340 60 discriminator 1 view .LVU199 772 0072 312B cmp r3, #49 773 0074 F5D9 bls .L50 340:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; ARM GAS /tmp/ccdzv1TD.s page 22 774 .loc 1 340 60 is_stmt 0 discriminator 1 view .LVU200 775 .LBE12: 343:Core/Src/stm32f4xx_it.c **** 776 .loc 1 343 5 is_stmt 1 view .LVU201 343:Core/Src/stm32f4xx_it.c **** 777 .loc 1 343 29 is_stmt 0 view .LVU202 778 0076 0B4B ldr r3, .L55+4 779 .LVL30: 343:Core/Src/stm32f4xx_it.c **** 780 .loc 1 343 29 view .LVU203 781 0078 9A68 ldr r2, [r3, #8] 343:Core/Src/stm32f4xx_it.c **** 782 .loc 1 343 16 view .LVU204 783 007a 0B4B ldr r3, .L55+8 784 007c DA60 str r2, [r3, #12] 785 007e 0DE0 b .L45 786 .LVL31: 787 .L52: 788 .LBB13: 347:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 789 .loc 1 347 7 is_stmt 1 view .LVU205 790 .loc 1 347 15 is_stmt 0 view .LVU206 791 0080 0949 ldr r1, .L55+8 792 0082 4A68 ldr r2, [r1, #4] 793 .loc 1 347 41 view .LVU207 794 0084 0948 ldr r0, .L55+12 795 0086 30F81300 ldrh r0, [r0, r3, lsl #1] 796 .loc 1 347 20 view .LVU208 797 008a 0244 add r2, r2, r0 798 008c 4A60 str r2, [r1, #4] 346:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 799 .loc 1 346 48 is_stmt 1 discriminator 3 view .LVU209 800 008e 0133 adds r3, r3, #1 801 .LVL32: 802 .L47: 346:Core/Src/stm32f4xx_it.c **** ADC_proc.sum += ADC1_buff_circular[i]; 803 .loc 1 346 28 discriminator 1 view .LVU210 804 0090 312B cmp r3, #49 805 0092 F5D9 bls .L52 806 .LBE13: 348:Core/Src/stm32f4xx_it.c **** } 349:Core/Src/stm32f4xx_it.c **** ADC_proc.N += ADC_BUFF_SIZE/2; 807 .loc 1 349 5 view .LVU211 808 .loc 1 349 13 is_stmt 0 view .LVU212 809 0094 044A ldr r2, .L55+8 810 0096 D368 ldr r3, [r2, #12] 811 .LVL33: 812 .loc 1 349 16 view .LVU213 813 0098 3233 adds r3, r3, #50 814 009a D360 str r3, [r2, #12] 815 .LVL34: 816 .L45: 350:Core/Src/stm32f4xx_it.c **** } 351:Core/Src/stm32f4xx_it.c **** // This function is called when the first half of the ADC buffer is filled 352:Core/Src/stm32f4xx_it.c **** // You can process the first half of ADC1_buff_circular here 353:Core/Src/stm32f4xx_it.c **** } 817 .loc 1 353 1 view .LVU214 ARM GAS /tmp/ccdzv1TD.s page 23 818 009c 08BD pop {r3, pc} 819 .L56: 820 009e 00BF .align 2 821 .L55: 822 00a0 00040240 .word 1073873920 823 00a4 00000000 .word Sweep_state 824 00a8 00000000 .word ADC_proc 825 00ac 00000000 .word ADC1_buff_circular 826 00b0 00000000 .word ADC_proc_shadow 827 .cfi_endproc 828 .LFE253: 830 .text 831 .Letext0: 832 .file 2 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" 833 .file 3 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h" 834 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" 835 .file 5 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h" 836 .file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h" 837 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h" 838 .file 8 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h" 839 .file 9 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h" 840 .file 10 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h" 841 .file 11 "Core/Inc/main.h" 842 .file 12 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h" ARM GAS /tmp/ccdzv1TD.s page 24 DEFINED SYMBOLS *ABS*:00000000 stm32f4xx_it.c /tmp/ccdzv1TD.s:21 .text.NMI_Handler:00000000 $t /tmp/ccdzv1TD.s:27 .text.NMI_Handler:00000000 NMI_Handler /tmp/ccdzv1TD.s:44 .text.HardFault_Handler:00000000 $t /tmp/ccdzv1TD.s:50 .text.HardFault_Handler:00000000 HardFault_Handler /tmp/ccdzv1TD.s:67 .text.MemManage_Handler:00000000 $t /tmp/ccdzv1TD.s:73 .text.MemManage_Handler:00000000 MemManage_Handler /tmp/ccdzv1TD.s:90 .text.BusFault_Handler:00000000 $t /tmp/ccdzv1TD.s:96 .text.BusFault_Handler:00000000 BusFault_Handler /tmp/ccdzv1TD.s:113 .text.UsageFault_Handler:00000000 $t /tmp/ccdzv1TD.s:119 .text.UsageFault_Handler:00000000 UsageFault_Handler /tmp/ccdzv1TD.s:136 .text.SVC_Handler:00000000 $t /tmp/ccdzv1TD.s:142 .text.SVC_Handler:00000000 SVC_Handler /tmp/ccdzv1TD.s:155 .text.DebugMon_Handler:00000000 $t /tmp/ccdzv1TD.s:161 .text.DebugMon_Handler:00000000 DebugMon_Handler /tmp/ccdzv1TD.s:174 .text.PendSV_Handler:00000000 $t /tmp/ccdzv1TD.s:180 .text.PendSV_Handler:00000000 PendSV_Handler /tmp/ccdzv1TD.s:193 .text.SysTick_Handler:00000000 $t /tmp/ccdzv1TD.s:199 .text.SysTick_Handler:00000000 SysTick_Handler /tmp/ccdzv1TD.s:219 .text.EXTI0_IRQHandler:00000000 $t /tmp/ccdzv1TD.s:225 .text.EXTI0_IRQHandler:00000000 EXTI0_IRQHandler /tmp/ccdzv1TD.s:275 .text.EXTI0_IRQHandler:0000002c $d /tmp/ccdzv1TD.s:281 .text.EXTI3_IRQHandler:00000000 $t /tmp/ccdzv1TD.s:287 .text.EXTI3_IRQHandler:00000000 EXTI3_IRQHandler /tmp/ccdzv1TD.s:308 .text.DMA2_Stream0_IRQHandler:00000000 $t /tmp/ccdzv1TD.s:314 .text.DMA2_Stream0_IRQHandler:00000000 DMA2_Stream0_IRQHandler /tmp/ccdzv1TD.s:334 .text.DMA2_Stream0_IRQHandler:0000000c $d /tmp/ccdzv1TD.s:339 .text.OTG_FS_IRQHandler:00000000 $t /tmp/ccdzv1TD.s:345 .text.OTG_FS_IRQHandler:00000000 OTG_FS_IRQHandler /tmp/ccdzv1TD.s:365 .text.OTG_FS_IRQHandler:0000000c $d /tmp/ccdzv1TD.s:370 .text.HAL_ADC_ConvCpltCallback:00000000 $t /tmp/ccdzv1TD.s:376 .text.HAL_ADC_ConvCpltCallback:00000000 HAL_ADC_ConvCpltCallback /tmp/ccdzv1TD.s:616 .text.HAL_ADC_ConvCpltCallback:000000d4 $d /tmp/ccdzv1TD.s:625 .text.HAL_ADC_ConvHalfCpltCallback:00000000 $t /tmp/ccdzv1TD.s:631 .text.HAL_ADC_ConvHalfCpltCallback:00000000 HAL_ADC_ConvHalfCpltCallback /tmp/ccdzv1TD.s:822 .text.HAL_ADC_ConvHalfCpltCallback:000000a0 $d UNDEFINED SYMBOLS HAL_IncTick HAL_GPIO_EXTI_IRQHandler hdma_adc1 Sweep_state HAL_DMA_IRQHandler HAL_PCD_IRQHandler hpcd_USB_OTG_FS HAL_GPIO_WritePin ADC_proc ADC1_buff_circular ADC_proc_shadow HAL_GPIO_TogglePin