ARM GAS /tmp/ccdSoXH4.s page 1 1 .cpu cortex-m4 2 .arch armv7e-m 3 .fpu fpv4-sp-d16 4 .eabi_attribute 27, 1 5 .eabi_attribute 28, 1 6 .eabi_attribute 20, 1 7 .eabi_attribute 21, 1 8 .eabi_attribute 23, 3 9 .eabi_attribute 24, 1 10 .eabi_attribute 25, 1 11 .eabi_attribute 26, 1 12 .eabi_attribute 30, 1 13 .eabi_attribute 34, 1 14 .eabi_attribute 18, 4 15 .file "main.c" 16 .text 17 .Ltext0: 18 .cfi_sections .debug_frame 19 .file 1 "Core/Src/main.c" 20 .section .text.MX_GPIO_Init,"ax",%progbits 21 .align 1 22 .syntax unified 23 .thumb 24 .thumb_func 26 MX_GPIO_Init: 27 .LFB247: 1:Core/Src/main.c **** /* USER CODE BEGIN Header */ 2:Core/Src/main.c **** /** 3:Core/Src/main.c **** ****************************************************************************** 4:Core/Src/main.c **** * @file : main.c 5:Core/Src/main.c **** * @brief : Main program body 6:Core/Src/main.c **** ****************************************************************************** 7:Core/Src/main.c **** * @attention 8:Core/Src/main.c **** * 9:Core/Src/main.c **** * Copyright (c) 2025 STMicroelectronics. 10:Core/Src/main.c **** * All rights reserved. 11:Core/Src/main.c **** * 12:Core/Src/main.c **** * This software is licensed under terms that can be found in the LICENSE file 13:Core/Src/main.c **** * in the root directory of this software component. 14:Core/Src/main.c **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Core/Src/main.c **** * 16:Core/Src/main.c **** ****************************************************************************** 17:Core/Src/main.c **** */ 18:Core/Src/main.c **** /* USER CODE END Header */ 19:Core/Src/main.c **** /* Includes ------------------------------------------------------------------*/ 20:Core/Src/main.c **** #include "main.h" 21:Core/Src/main.c **** #include "usb_device.h" 22:Core/Src/main.c **** 23:Core/Src/main.c **** /* Private includes ----------------------------------------------------------*/ 24:Core/Src/main.c **** /* USER CODE BEGIN Includes */ 25:Core/Src/main.c **** 26:Core/Src/main.c **** /* USER CODE END Includes */ 27:Core/Src/main.c **** 28:Core/Src/main.c **** /* Private typedef -----------------------------------------------------------*/ 29:Core/Src/main.c **** /* USER CODE BEGIN PTD */ 30:Core/Src/main.c **** 31:Core/Src/main.c **** /* USER CODE END PTD */ ARM GAS /tmp/ccdSoXH4.s page 2 32:Core/Src/main.c **** 33:Core/Src/main.c **** /* Private define ------------------------------------------------------------*/ 34:Core/Src/main.c **** /* USER CODE BEGIN PD */ 35:Core/Src/main.c **** 36:Core/Src/main.c **** /* USER CODE END PD */ 37:Core/Src/main.c **** 38:Core/Src/main.c **** /* Private macro -------------------------------------------------------------*/ 39:Core/Src/main.c **** /* USER CODE BEGIN PM */ 40:Core/Src/main.c **** 41:Core/Src/main.c **** /* USER CODE END PM */ 42:Core/Src/main.c **** 43:Core/Src/main.c **** /* Private variables ---------------------------------------------------------*/ 44:Core/Src/main.c **** ADC_HandleTypeDef hadc1; 45:Core/Src/main.c **** DMA_HandleTypeDef hdma_adc1; 46:Core/Src/main.c **** 47:Core/Src/main.c **** /* USER CODE BEGIN PV */ 48:Core/Src/main.c **** 49:Core/Src/main.c **** /* USER CODE END PV */ 50:Core/Src/main.c **** 51:Core/Src/main.c **** /* Private function prototypes -----------------------------------------------*/ 52:Core/Src/main.c **** void SystemClock_Config(void); 53:Core/Src/main.c **** static void MX_GPIO_Init(void); 54:Core/Src/main.c **** static void MX_DMA_Init(void); 55:Core/Src/main.c **** static void MX_ADC1_Init(void); 56:Core/Src/main.c **** /* USER CODE BEGIN PFP */ 57:Core/Src/main.c **** 58:Core/Src/main.c **** /* USER CODE END PFP */ 59:Core/Src/main.c **** 60:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/ 61:Core/Src/main.c **** /* USER CODE BEGIN 0 */ 62:Core/Src/main.c **** /* ADC_proc/ADC_proc_shadow/Sweep_state definitions */ 63:Core/Src/main.c **** volatile struct ADC_proc_typedef ADC_proc, ADC_proc_shadow; 64:Core/Src/main.c **** volatile struct Sweep_state_typedef Sweep_state; 65:Core/Src/main.c **** volatile uint32_t curr_step_start_N = 0; 66:Core/Src/main.c **** 67:Core/Src/main.c **** /* ADC1 circular DMA buffer definition */ 68:Core/Src/main.c **** uint16_t ADC1_buff_circular[ADC_BUFF_SIZE]; 69:Core/Src/main.c **** 70:Core/Src/main.c **** 71:Core/Src/main.c **** char ADC_msg[] = "stp ?????? ??????????\r\nSweep_start\n\r"; 72:Core/Src/main.c **** #define ADC_msg_len 24 73:Core/Src/main.c **** #define ADC_msg_len_Sweep_start 37 74:Core/Src/main.c **** 75:Core/Src/main.c **** 76:Core/Src/main.c **** 77:Core/Src/main.c **** //char ADC_msg[] = "stp ?????? ?????????? ??????????\r\nSweep_start\n\r"; 78:Core/Src/main.c **** //#define ADC_msg_len 35 79:Core/Src/main.c **** //#define ADC_msg_len_Sweep_start 48 80:Core/Src/main.c **** #define ADC_msg_val_ON_pos 12 81:Core/Src/main.c **** #define ADC_msg_val_OFF_pos 23 82:Core/Src/main.c **** 83:Core/Src/main.c **** #define ADC_msg_step_pos 4 84:Core/Src/main.c **** /* USER CODE END 0 */ 85:Core/Src/main.c **** 86:Core/Src/main.c **** /** 87:Core/Src/main.c **** * @brief The application entry point. 88:Core/Src/main.c **** * @retval int ARM GAS /tmp/ccdSoXH4.s page 3 89:Core/Src/main.c **** */ 90:Core/Src/main.c **** int main(void) 91:Core/Src/main.c **** { 92:Core/Src/main.c **** 93:Core/Src/main.c **** /* USER CODE BEGIN 1 */ 94:Core/Src/main.c **** 95:Core/Src/main.c **** /* USER CODE END 1 */ 96:Core/Src/main.c **** 97:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ 98:Core/Src/main.c **** 99:Core/Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 100:Core/Src/main.c **** HAL_Init(); 101:Core/Src/main.c **** 102:Core/Src/main.c **** /* USER CODE BEGIN Init */ 103:Core/Src/main.c **** 104:Core/Src/main.c **** /* USER CODE END Init */ 105:Core/Src/main.c **** 106:Core/Src/main.c **** /* Configure the system clock */ 107:Core/Src/main.c **** SystemClock_Config(); 108:Core/Src/main.c **** 109:Core/Src/main.c **** /* USER CODE BEGIN SysInit */ 110:Core/Src/main.c **** 111:Core/Src/main.c **** /* USER CODE END SysInit */ 112:Core/Src/main.c **** 113:Core/Src/main.c **** /* Initialize all configured peripherals */ 114:Core/Src/main.c **** MX_GPIO_Init(); 115:Core/Src/main.c **** MX_DMA_Init(); 116:Core/Src/main.c **** MX_ADC1_Init(); 117:Core/Src/main.c **** MX_USB_DEVICE_Init(); 118:Core/Src/main.c **** /* USER CODE BEGIN 2 */ 119:Core/Src/main.c **** HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_SET); 120:Core/Src/main.c **** HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADC1_buff_circular, ADC_BUFF_SIZE); 121:Core/Src/main.c **** 122:Core/Src/main.c **** ADC_proc_shadow.status = 0; // ADC started 123:Core/Src/main.c **** ADC_proc_shadow.N = 0; 124:Core/Src/main.c **** ADC_proc_shadow.sum_ON = 0; 125:Core/Src/main.c **** ADC_proc_shadow.avg_ON = 0; 126:Core/Src/main.c **** ADC_proc_shadow.sum_OFF = 0; 127:Core/Src/main.c **** ADC_proc_shadow.avg_OFF = 0; 128:Core/Src/main.c **** 129:Core/Src/main.c **** ADC_proc.status = 0; // ADC started 130:Core/Src/main.c **** ADC_proc.N = 0; 131:Core/Src/main.c **** ADC_proc.sum_ON = 0; 132:Core/Src/main.c **** ADC_proc.avg_ON = 0; 133:Core/Src/main.c **** ADC_proc.sum_OFF = 0; 134:Core/Src/main.c **** ADC_proc.avg_OFF = 0; 135:Core/Src/main.c **** 136:Core/Src/main.c **** uint32_t curr_points_N_max = 100; 137:Core/Src/main.c **** uint32_t curr_points_N =0; 138:Core/Src/main.c **** 139:Core/Src/main.c **** /* USER CODE END 2 */ 140:Core/Src/main.c **** 141:Core/Src/main.c **** /* Infinite loop */ 142:Core/Src/main.c **** /* USER CODE BEGIN WHILE */ 143:Core/Src/main.c **** while (1) 144:Core/Src/main.c **** { 145:Core/Src/main.c **** //HAL_GPIO_TogglePin(LED_RED_GPIO_Port, LED_RED_Pin); ARM GAS /tmp/ccdSoXH4.s page 4 146:Core/Src/main.c **** //HAL_Delay(100); 147:Core/Src/main.c **** 148:Core/Src/main.c **** if (ADC_proc_shadow.status == 2) { 149:Core/Src/main.c **** // ADC_proc_shadow.avg_ON = ADC_proc_shadow.sum_ON / ADC_proc_shadow.N; 150:Core/Src/main.c **** ADC_proc_shadow.avg_OFF = ADC_proc_shadow.sum_OFF / ADC_proc_shadow.N; 151:Core/Src/main.c **** ADC_proc_shadow.avg_ON = ADC_proc_shadow.sum_ON / ADC_proc_shadow.N; 152:Core/Src/main.c **** ADC_proc_shadow.avg_ON = ADC_proc_shadow.avg_OFF; 153:Core/Src/main.c **** // ADC_proc_shadow.avg_ON = ADC_proc_shadow.avg_ON - ADC_proc_shadow.avg_OFF; 154:Core/Src/main.c **** ADC_proc_shadow.status = 1; // reset for next accumulation 155:Core/Src/main.c **** ADC_proc_shadow.sum = 0; 156:Core/Src/main.c **** ADC_proc_shadow.N = 0; 157:Core/Src/main.c **** 158:Core/Src/main.c **** 159:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 0] = (ADC_proc_shadow.avg_ON / 1000000000) % 10 + '0'; 160:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 1] = (ADC_proc_shadow.avg_ON / 100000000) % 10 + '0'; 161:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 2] = (ADC_proc_shadow.avg_ON / 10000000) % 10 + '0'; 162:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 3] = (ADC_proc_shadow.avg_ON / 1000000) % 10 + '0'; 163:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 4] = (ADC_proc_shadow.avg_ON / 100000) % 10 + '0'; 164:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 5] = (ADC_proc_shadow.avg_ON / 10000) % 10 + '0'; 165:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 6] = (ADC_proc_shadow.avg_ON / 1000) % 10 + '0'; 166:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 7] = (ADC_proc_shadow.avg_ON / 100) % 10 + '0'; 167:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 8] = (ADC_proc_shadow.avg_ON / 10) % 10 + '0'; 168:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 9] = (ADC_proc_shadow.avg_ON / 1) % 10 + '0'; 169:Core/Src/main.c **** 170:Core/Src/main.c **** /* 171:Core/Src/main.c **** ADC_msg[ADC_msg_val_OFF_pos + 0] = (ADC_proc_shadow.avg_OFF / 1000000000) % 10 + '0'; 172:Core/Src/main.c **** ADC_msg[ADC_msg_val_OFF_pos + 1] = (ADC_proc_shadow.avg_OFF / 100000000) % 10 + '0'; 173:Core/Src/main.c **** ADC_msg[ADC_msg_val_OFF_pos + 2] = (ADC_proc_shadow.avg_OFF / 10000000) % 10 + '0'; 174:Core/Src/main.c **** ADC_msg[ADC_msg_val_OFF_pos + 3] = (ADC_proc_shadow.avg_OFF / 1000000) % 10 + '0'; 175:Core/Src/main.c **** ADC_msg[ADC_msg_val_OFF_pos + 4] = (ADC_proc_shadow.avg_OFF / 100000) % 10 + '0'; 176:Core/Src/main.c **** ADC_msg[ADC_msg_val_OFF_pos + 5] = (ADC_proc_shadow.avg_OFF / 10000) % 10 + '0'; 177:Core/Src/main.c **** ADC_msg[ADC_msg_val_OFF_pos + 6] = (ADC_proc_shadow.avg_OFF / 1000) % 10 + '0'; 178:Core/Src/main.c **** ADC_msg[ADC_msg_val_OFF_pos + 7] = (ADC_proc_shadow.avg_OFF / 100) % 10 + '0'; 179:Core/Src/main.c **** ADC_msg[ADC_msg_val_OFF_pos + 8] = (ADC_proc_shadow.avg_OFF / 10) % 10 + '0'; 180:Core/Src/main.c **** ADC_msg[ADC_msg_val_OFF_pos + 9] = (ADC_proc_shadow.avg_OFF / 1) % 10 + '0'; 181:Core/Src/main.c **** */ 182:Core/Src/main.c **** 183:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 0] = (Sweep_state.curr_step_N / 100000) % 10 + '0'; 184:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 1] = (Sweep_state.curr_step_N / 10000) % 10 + '0'; 185:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 2] = (Sweep_state.curr_step_N / 1000) % 10 + '0'; 186:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 3] = (Sweep_state.curr_step_N / 100) % 10 + '0'; 187:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 4] = (Sweep_state.curr_step_N / 10) % 10 + '0'; 188:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 5] = (Sweep_state.curr_step_N / 1) % 10 + '0'; 189:Core/Src/main.c **** 190:Core/Src/main.c **** 191:Core/Src/main.c **** //HAL_GPIO_TogglePin(LED_RED_GPIO_Port, LED_RED_Pin); 192:Core/Src/main.c **** 193:Core/Src/main.c **** 194:Core/Src/main.c **** if (Sweep_state.curr_step_N > 10000){ 195:Core/Src/main.c **** Sweep_state.curr_step_N = 0; 196:Core/Src/main.c **** Sweep_state.sweep_cycle_started_flag = 1; 197:Core/Src/main.c **** } 198:Core/Src/main.c **** if (Sweep_state.sweep_cycle_started_flag == 1){ 199:Core/Src/main.c **** Sweep_state.sweep_cycle_started_flag = 0; // reset sweep cycle flag 200:Core/Src/main.c **** HAL_GPIO_TogglePin(LED_RED_GPIO_Port, LED_RED_Pin); 201:Core/Src/main.c **** //CDC_Transmit_FS((uint8_t *)ADC_msg, ADC_msg_len_Sweep_start); 202:Core/Src/main.c **** while (CDC_Transmit_FS((uint8_t *)ADC_msg, ADC_msg_len_Sweep_start) == USBD_BUSY){ ARM GAS /tmp/ccdSoXH4.s page 5 203:Core/Src/main.c **** //HAL_Delay(1); 204:Core/Src/main.c **** } 205:Core/Src/main.c **** 206:Core/Src/main.c **** }else{ 207:Core/Src/main.c **** CDC_Transmit_FS((uint8_t *)ADC_msg, ADC_msg_len); 208:Core/Src/main.c **** 209:Core/Src/main.c **** } 210:Core/Src/main.c **** 211:Core/Src/main.c **** } 212:Core/Src/main.c **** //CDC_Transmit_FS((uint8_t *)"Hello from STM32!\r\n", 19); 213:Core/Src/main.c **** 214:Core/Src/main.c **** /* USER CODE END WHILE */ 215:Core/Src/main.c **** 216:Core/Src/main.c **** /* USER CODE BEGIN 3 */ 217:Core/Src/main.c **** } 218:Core/Src/main.c **** /* USER CODE END 3 */ 219:Core/Src/main.c **** } 220:Core/Src/main.c **** 221:Core/Src/main.c **** /** 222:Core/Src/main.c **** * @brief System Clock Configuration 223:Core/Src/main.c **** * @retval None 224:Core/Src/main.c **** */ 225:Core/Src/main.c **** void SystemClock_Config(void) 226:Core/Src/main.c **** { 227:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 228:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 229:Core/Src/main.c **** 230:Core/Src/main.c **** /** Configure the main internal regulator output voltage 231:Core/Src/main.c **** */ 232:Core/Src/main.c **** __HAL_RCC_PWR_CLK_ENABLE(); 233:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 234:Core/Src/main.c **** 235:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters 236:Core/Src/main.c **** * in the RCC_OscInitTypeDef structure. 237:Core/Src/main.c **** */ 238:Core/Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 239:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 240:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 241:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 242:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 8; 243:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 336; 244:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 245:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 7; 246:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 247:Core/Src/main.c **** { 248:Core/Src/main.c **** Error_Handler(); 249:Core/Src/main.c **** } 250:Core/Src/main.c **** 251:Core/Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks 252:Core/Src/main.c **** */ 253:Core/Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 254:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 255:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 256:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 257:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 258:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 259:Core/Src/main.c **** ARM GAS /tmp/ccdSoXH4.s page 6 260:Core/Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) 261:Core/Src/main.c **** { 262:Core/Src/main.c **** Error_Handler(); 263:Core/Src/main.c **** } 264:Core/Src/main.c **** } 265:Core/Src/main.c **** 266:Core/Src/main.c **** /** 267:Core/Src/main.c **** * @brief ADC1 Initialization Function 268:Core/Src/main.c **** * @param None 269:Core/Src/main.c **** * @retval None 270:Core/Src/main.c **** */ 271:Core/Src/main.c **** static void MX_ADC1_Init(void) 272:Core/Src/main.c **** { 273:Core/Src/main.c **** 274:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 0 */ 275:Core/Src/main.c **** 276:Core/Src/main.c **** /* USER CODE END ADC1_Init 0 */ 277:Core/Src/main.c **** 278:Core/Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0}; 279:Core/Src/main.c **** 280:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 1 */ 281:Core/Src/main.c **** 282:Core/Src/main.c **** /* USER CODE END ADC1_Init 1 */ 283:Core/Src/main.c **** 284:Core/Src/main.c **** /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of con 285:Core/Src/main.c **** */ 286:Core/Src/main.c **** hadc1.Instance = ADC1; 287:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; 288:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; 289:Core/Src/main.c **** hadc1.Init.ScanConvMode = DISABLE; 290:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; 291:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; 292:Core/Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 293:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_Ext_IT11; 294:Core/Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 295:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1; 296:Core/Src/main.c **** hadc1.Init.DMAContinuousRequests = ENABLE; 297:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 298:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) 299:Core/Src/main.c **** { 300:Core/Src/main.c **** Error_Handler(); 301:Core/Src/main.c **** } 302:Core/Src/main.c **** 303:Core/Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 304:Core/Src/main.c **** */ 305:Core/Src/main.c **** sConfig.Channel = ADC_CHANNEL_3; 306:Core/Src/main.c **** sConfig.Rank = 1; 307:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; 308:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 309:Core/Src/main.c **** { 310:Core/Src/main.c **** Error_Handler(); 311:Core/Src/main.c **** } 312:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 2 */ 313:Core/Src/main.c **** 314:Core/Src/main.c **** /* USER CODE END ADC1_Init 2 */ 315:Core/Src/main.c **** 316:Core/Src/main.c **** } ARM GAS /tmp/ccdSoXH4.s page 7 317:Core/Src/main.c **** 318:Core/Src/main.c **** /** 319:Core/Src/main.c **** * Enable DMA controller clock 320:Core/Src/main.c **** */ 321:Core/Src/main.c **** static void MX_DMA_Init(void) 322:Core/Src/main.c **** { 323:Core/Src/main.c **** 324:Core/Src/main.c **** /* DMA controller clock enable */ 325:Core/Src/main.c **** __HAL_RCC_DMA2_CLK_ENABLE(); 326:Core/Src/main.c **** 327:Core/Src/main.c **** /* DMA interrupt init */ 328:Core/Src/main.c **** /* DMA2_Stream0_IRQn interrupt configuration */ 329:Core/Src/main.c **** HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 0, 0); 330:Core/Src/main.c **** HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); 331:Core/Src/main.c **** 332:Core/Src/main.c **** } 333:Core/Src/main.c **** 334:Core/Src/main.c **** /** 335:Core/Src/main.c **** * @brief GPIO Initialization Function 336:Core/Src/main.c **** * @param None 337:Core/Src/main.c **** * @retval None 338:Core/Src/main.c **** */ 339:Core/Src/main.c **** static void MX_GPIO_Init(void) 340:Core/Src/main.c **** { 28 .loc 1 340 1 view -0 29 .cfi_startproc 30 @ args = 0, pretend = 0, frame = 40 31 @ frame_needed = 0, uses_anonymous_args = 0 32 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 33 .LCFI0: 34 .cfi_def_cfa_offset 24 35 .cfi_offset 4, -24 36 .cfi_offset 5, -20 37 .cfi_offset 6, -16 38 .cfi_offset 7, -12 39 .cfi_offset 8, -8 40 .cfi_offset 14, -4 41 0004 8AB0 sub sp, sp, #40 42 .LCFI1: 43 .cfi_def_cfa_offset 64 341:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; 44 .loc 1 341 3 view .LVU1 45 .loc 1 341 20 is_stmt 0 view .LVU2 46 0006 0024 movs r4, #0 47 0008 0594 str r4, [sp, #20] 48 000a 0694 str r4, [sp, #24] 49 000c 0794 str r4, [sp, #28] 50 000e 0894 str r4, [sp, #32] 51 0010 0994 str r4, [sp, #36] 342:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */ 343:Core/Src/main.c **** 344:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_1 */ 345:Core/Src/main.c **** 346:Core/Src/main.c **** /* GPIO Ports Clock Enable */ 347:Core/Src/main.c **** __HAL_RCC_GPIOH_CLK_ENABLE(); 52 .loc 1 347 3 is_stmt 1 view .LVU3 53 .LBB4: ARM GAS /tmp/ccdSoXH4.s page 8 54 .loc 1 347 3 view .LVU4 55 0012 0094 str r4, [sp] 56 .loc 1 347 3 view .LVU5 57 0014 3D4B ldr r3, .L3 58 0016 1A6B ldr r2, [r3, #48] 59 0018 42F08002 orr r2, r2, #128 60 001c 1A63 str r2, [r3, #48] 61 .loc 1 347 3 view .LVU6 62 001e 1A6B ldr r2, [r3, #48] 63 0020 02F08002 and r2, r2, #128 64 0024 0092 str r2, [sp] 65 .loc 1 347 3 view .LVU7 66 0026 009A ldr r2, [sp] 67 .LBE4: 68 .loc 1 347 3 view .LVU8 348:Core/Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); 69 .loc 1 348 3 view .LVU9 70 .LBB5: 71 .loc 1 348 3 view .LVU10 72 0028 0194 str r4, [sp, #4] 73 .loc 1 348 3 view .LVU11 74 002a 1A6B ldr r2, [r3, #48] 75 002c 42F00402 orr r2, r2, #4 76 0030 1A63 str r2, [r3, #48] 77 .loc 1 348 3 view .LVU12 78 0032 1A6B ldr r2, [r3, #48] 79 0034 02F00402 and r2, r2, #4 80 0038 0192 str r2, [sp, #4] 81 .loc 1 348 3 view .LVU13 82 003a 019A ldr r2, [sp, #4] 83 .LBE5: 84 .loc 1 348 3 view .LVU14 349:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); 85 .loc 1 349 3 view .LVU15 86 .LBB6: 87 .loc 1 349 3 view .LVU16 88 003c 0294 str r4, [sp, #8] 89 .loc 1 349 3 view .LVU17 90 003e 1A6B ldr r2, [r3, #48] 91 0040 42F00102 orr r2, r2, #1 92 0044 1A63 str r2, [r3, #48] 93 .loc 1 349 3 view .LVU18 94 0046 1A6B ldr r2, [r3, #48] 95 0048 02F00102 and r2, r2, #1 96 004c 0292 str r2, [sp, #8] 97 .loc 1 349 3 view .LVU19 98 004e 029A ldr r2, [sp, #8] 99 .LBE6: 100 .loc 1 349 3 view .LVU20 350:Core/Src/main.c **** __HAL_RCC_GPIOF_CLK_ENABLE(); 101 .loc 1 350 3 view .LVU21 102 .LBB7: 103 .loc 1 350 3 view .LVU22 104 0050 0394 str r4, [sp, #12] 105 .loc 1 350 3 view .LVU23 106 0052 1A6B ldr r2, [r3, #48] 107 0054 42F02002 orr r2, r2, #32 ARM GAS /tmp/ccdSoXH4.s page 9 108 0058 1A63 str r2, [r3, #48] 109 .loc 1 350 3 view .LVU24 110 005a 1A6B ldr r2, [r3, #48] 111 005c 02F02002 and r2, r2, #32 112 0060 0392 str r2, [sp, #12] 113 .loc 1 350 3 view .LVU25 114 0062 039A ldr r2, [sp, #12] 115 .LBE7: 116 .loc 1 350 3 view .LVU26 351:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); 117 .loc 1 351 3 view .LVU27 118 .LBB8: 119 .loc 1 351 3 view .LVU28 120 0064 0494 str r4, [sp, #16] 121 .loc 1 351 3 view .LVU29 122 0066 1A6B ldr r2, [r3, #48] 123 0068 42F00202 orr r2, r2, #2 124 006c 1A63 str r2, [r3, #48] 125 .loc 1 351 3 view .LVU30 126 006e 1B6B ldr r3, [r3, #48] 127 0070 03F00203 and r3, r3, #2 128 0074 0493 str r3, [sp, #16] 129 .loc 1 351 3 view .LVU31 130 0076 049B ldr r3, [sp, #16] 131 .LBE8: 132 .loc 1 351 3 view .LVU32 352:Core/Src/main.c **** 353:Core/Src/main.c **** /*Configure GPIO pin Output Level */ 354:Core/Src/main.c **** HAL_GPIO_WritePin(LED_RED_GPIO_Port, LED_RED_Pin, GPIO_PIN_RESET); 133 .loc 1 354 3 view .LVU33 134 0078 254D ldr r5, .L3+4 135 007a 2246 mov r2, r4 136 007c 4FF48041 mov r1, #16384 137 0080 2846 mov r0, r5 138 0082 FFF7FEFF bl HAL_GPIO_WritePin 139 .LVL0: 355:Core/Src/main.c **** 356:Core/Src/main.c **** /*Configure GPIO pin Output Level */ 357:Core/Src/main.c **** HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_SET); 140 .loc 1 357 3 view .LVU34 141 0086 0122 movs r2, #1 142 0088 8021 movs r1, #128 143 008a 2846 mov r0, r5 144 008c FFF7FEFF bl HAL_GPIO_WritePin 145 .LVL1: 358:Core/Src/main.c **** 359:Core/Src/main.c **** /*Configure GPIO pin : CURR_STEP_START_TRG_Pin */ 360:Core/Src/main.c **** GPIO_InitStruct.Pin = CURR_STEP_START_TRG_Pin; 146 .loc 1 360 3 view .LVU35 147 .loc 1 360 23 is_stmt 0 view .LVU36 148 0090 0126 movs r6, #1 149 0092 0596 str r6, [sp, #20] 361:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; 150 .loc 1 361 3 is_stmt 1 view .LVU37 151 .loc 1 361 24 is_stmt 0 view .LVU38 152 0094 4FF44413 mov r3, #3211264 153 0098 0693 str r3, [sp, #24] ARM GAS /tmp/ccdSoXH4.s page 10 362:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_PULLDOWN; 154 .loc 1 362 3 is_stmt 1 view .LVU39 155 .loc 1 362 24 is_stmt 0 view .LVU40 156 009a 0223 movs r3, #2 157 009c 0793 str r3, [sp, #28] 363:Core/Src/main.c **** HAL_GPIO_Init(CURR_STEP_START_TRG_GPIO_Port, &GPIO_InitStruct); 158 .loc 1 363 3 is_stmt 1 view .LVU41 159 009e DFF87880 ldr r8, .L3+12 160 00a2 05A9 add r1, sp, #20 161 00a4 4046 mov r0, r8 162 00a6 FFF7FEFF bl HAL_GPIO_Init 163 .LVL2: 364:Core/Src/main.c **** 365:Core/Src/main.c **** /*Configure GPIO pin : SWEEP_CYCLE_START_TRG_Pin */ 366:Core/Src/main.c **** GPIO_InitStruct.Pin = SWEEP_CYCLE_START_TRG_Pin; 164 .loc 1 366 3 view .LVU42 165 .loc 1 366 23 is_stmt 0 view .LVU43 166 00aa 0823 movs r3, #8 167 00ac 0593 str r3, [sp, #20] 367:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 168 .loc 1 367 3 is_stmt 1 view .LVU44 169 .loc 1 367 24 is_stmt 0 view .LVU45 170 00ae 4FF48817 mov r7, #1114112 171 00b2 0697 str r7, [sp, #24] 368:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_PULLUP; 172 .loc 1 368 3 is_stmt 1 view .LVU46 173 .loc 1 368 24 is_stmt 0 view .LVU47 174 00b4 0796 str r6, [sp, #28] 369:Core/Src/main.c **** HAL_GPIO_Init(SWEEP_CYCLE_START_TRG_GPIO_Port, &GPIO_InitStruct); 175 .loc 1 369 3 is_stmt 1 view .LVU48 176 00b6 05A9 add r1, sp, #20 177 00b8 4046 mov r0, r8 178 00ba FFF7FEFF bl HAL_GPIO_Init 179 .LVL3: 370:Core/Src/main.c **** 371:Core/Src/main.c **** /*Configure GPIO pin : PF11 */ 372:Core/Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_11; 180 .loc 1 372 3 view .LVU49 181 .loc 1 372 23 is_stmt 0 view .LVU50 182 00be 4FF40063 mov r3, #2048 183 00c2 0593 str r3, [sp, #20] 373:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 184 .loc 1 373 3 is_stmt 1 view .LVU51 185 .loc 1 373 24 is_stmt 0 view .LVU52 186 00c4 0697 str r7, [sp, #24] 374:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 187 .loc 1 374 3 is_stmt 1 view .LVU53 188 .loc 1 374 24 is_stmt 0 view .LVU54 189 00c6 0794 str r4, [sp, #28] 375:Core/Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 190 .loc 1 375 3 is_stmt 1 view .LVU55 191 00c8 05A9 add r1, sp, #20 192 00ca 1248 ldr r0, .L3+8 193 00cc FFF7FEFF bl HAL_GPIO_Init 194 .LVL4: 376:Core/Src/main.c **** 377:Core/Src/main.c **** /*Configure GPIO pins : LED_RED_Pin LED_BLUE_Pin */ ARM GAS /tmp/ccdSoXH4.s page 11 378:Core/Src/main.c **** GPIO_InitStruct.Pin = LED_RED_Pin|LED_BLUE_Pin; 195 .loc 1 378 3 view .LVU56 196 .loc 1 378 23 is_stmt 0 view .LVU57 197 00d0 4FF48143 mov r3, #16512 198 00d4 0593 str r3, [sp, #20] 379:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 199 .loc 1 379 3 is_stmt 1 view .LVU58 200 .loc 1 379 24 is_stmt 0 view .LVU59 201 00d6 0696 str r6, [sp, #24] 380:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 202 .loc 1 380 3 is_stmt 1 view .LVU60 203 .loc 1 380 24 is_stmt 0 view .LVU61 204 00d8 0794 str r4, [sp, #28] 381:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 205 .loc 1 381 3 is_stmt 1 view .LVU62 206 .loc 1 381 25 is_stmt 0 view .LVU63 207 00da 0894 str r4, [sp, #32] 382:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 208 .loc 1 382 3 is_stmt 1 view .LVU64 209 00dc 05A9 add r1, sp, #20 210 00de 2846 mov r0, r5 211 00e0 FFF7FEFF bl HAL_GPIO_Init 212 .LVL5: 383:Core/Src/main.c **** 384:Core/Src/main.c **** /* EXTI interrupt init*/ 385:Core/Src/main.c **** HAL_NVIC_SetPriority(EXTI0_IRQn, 0, 0); 213 .loc 1 385 3 view .LVU65 214 00e4 2246 mov r2, r4 215 00e6 2146 mov r1, r4 216 00e8 0620 movs r0, #6 217 00ea FFF7FEFF bl HAL_NVIC_SetPriority 218 .LVL6: 386:Core/Src/main.c **** HAL_NVIC_EnableIRQ(EXTI0_IRQn); 219 .loc 1 386 3 view .LVU66 220 00ee 0620 movs r0, #6 221 00f0 FFF7FEFF bl HAL_NVIC_EnableIRQ 222 .LVL7: 387:Core/Src/main.c **** 388:Core/Src/main.c **** HAL_NVIC_SetPriority(EXTI3_IRQn, 0, 0); 223 .loc 1 388 3 view .LVU67 224 00f4 2246 mov r2, r4 225 00f6 2146 mov r1, r4 226 00f8 0920 movs r0, #9 227 00fa FFF7FEFF bl HAL_NVIC_SetPriority 228 .LVL8: 389:Core/Src/main.c **** HAL_NVIC_EnableIRQ(EXTI3_IRQn); 229 .loc 1 389 3 view .LVU68 230 00fe 0920 movs r0, #9 231 0100 FFF7FEFF bl HAL_NVIC_EnableIRQ 232 .LVL9: 390:Core/Src/main.c **** 391:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_2 */ 392:Core/Src/main.c **** 393:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_2 */ 394:Core/Src/main.c **** } 233 .loc 1 394 1 is_stmt 0 view .LVU69 234 0104 0AB0 add sp, sp, #40 ARM GAS /tmp/ccdSoXH4.s page 12 235 .LCFI2: 236 .cfi_def_cfa_offset 24 237 @ sp needed 238 0106 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 239 .L4: 240 010a 00BF .align 2 241 .L3: 242 010c 00380240 .word 1073887232 243 0110 00040240 .word 1073873920 244 0114 00140240 .word 1073878016 245 0118 00080240 .word 1073874944 246 .cfi_endproc 247 .LFE247: 249 .section .text.MX_DMA_Init,"ax",%progbits 250 .align 1 251 .syntax unified 252 .thumb 253 .thumb_func 255 MX_DMA_Init: 256 .LFB246: 322:Core/Src/main.c **** 257 .loc 1 322 1 is_stmt 1 view -0 258 .cfi_startproc 259 @ args = 0, pretend = 0, frame = 8 260 @ frame_needed = 0, uses_anonymous_args = 0 261 0000 00B5 push {lr} 262 .LCFI3: 263 .cfi_def_cfa_offset 4 264 .cfi_offset 14, -4 265 0002 83B0 sub sp, sp, #12 266 .LCFI4: 267 .cfi_def_cfa_offset 16 325:Core/Src/main.c **** 268 .loc 1 325 3 view .LVU71 269 .LBB9: 325:Core/Src/main.c **** 270 .loc 1 325 3 view .LVU72 271 0004 0021 movs r1, #0 272 0006 0191 str r1, [sp, #4] 325:Core/Src/main.c **** 273 .loc 1 325 3 view .LVU73 274 0008 094B ldr r3, .L7 275 000a 1A6B ldr r2, [r3, #48] 276 000c 42F48002 orr r2, r2, #4194304 277 0010 1A63 str r2, [r3, #48] 325:Core/Src/main.c **** 278 .loc 1 325 3 view .LVU74 279 0012 1B6B ldr r3, [r3, #48] 280 0014 03F48003 and r3, r3, #4194304 281 0018 0193 str r3, [sp, #4] 325:Core/Src/main.c **** 282 .loc 1 325 3 view .LVU75 283 001a 019B ldr r3, [sp, #4] 284 .LBE9: 325:Core/Src/main.c **** 285 .loc 1 325 3 view .LVU76 329:Core/Src/main.c **** HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); ARM GAS /tmp/ccdSoXH4.s page 13 286 .loc 1 329 3 view .LVU77 287 001c 0A46 mov r2, r1 288 001e 3820 movs r0, #56 289 0020 FFF7FEFF bl HAL_NVIC_SetPriority 290 .LVL10: 330:Core/Src/main.c **** 291 .loc 1 330 3 view .LVU78 292 0024 3820 movs r0, #56 293 0026 FFF7FEFF bl HAL_NVIC_EnableIRQ 294 .LVL11: 332:Core/Src/main.c **** 295 .loc 1 332 1 is_stmt 0 view .LVU79 296 002a 03B0 add sp, sp, #12 297 .LCFI5: 298 .cfi_def_cfa_offset 4 299 @ sp needed 300 002c 5DF804FB ldr pc, [sp], #4 301 .L8: 302 .align 2 303 .L7: 304 0030 00380240 .word 1073887232 305 .cfi_endproc 306 .LFE246: 308 .section .text.Error_Handler,"ax",%progbits 309 .align 1 310 .global Error_Handler 311 .syntax unified 312 .thumb 313 .thumb_func 315 Error_Handler: 316 .LFB248: 395:Core/Src/main.c **** 396:Core/Src/main.c **** /* USER CODE BEGIN 4 */ 397:Core/Src/main.c **** 398:Core/Src/main.c **** /* USER CODE END 4 */ 399:Core/Src/main.c **** 400:Core/Src/main.c **** /** 401:Core/Src/main.c **** * @brief This function is executed in case of error occurrence. 402:Core/Src/main.c **** * @retval None 403:Core/Src/main.c **** */ 404:Core/Src/main.c **** void Error_Handler(void) 405:Core/Src/main.c **** { 317 .loc 1 405 1 is_stmt 1 view -0 318 .cfi_startproc 319 @ Volatile: function does not return. 320 @ args = 0, pretend = 0, frame = 0 321 @ frame_needed = 0, uses_anonymous_args = 0 322 @ link register save eliminated. 406:Core/Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */ 407:Core/Src/main.c **** /* User can add his own implementation to report the HAL error return state */ 408:Core/Src/main.c **** __disable_irq(); 323 .loc 1 408 3 view .LVU81 324 .LBB10: 325 .LBI10: 326 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h ARM GAS /tmp/ccdSoXH4.s page 14 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.4.1 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 27. May 2021 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2021 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 24:Drivers/CMSIS/Include/cmsis_gcc.h **** 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H 27:Drivers/CMSIS/Include/cmsis_gcc.h **** 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" 33:Drivers/CMSIS/Include/cmsis_gcc.h **** 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 38:Drivers/CMSIS/Include/cmsis_gcc.h **** 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) ARM GAS /tmp/ccdSoXH4.s page 15 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __COMPILER_BARRIER ARM GAS /tmp/ccdSoXH4.s page 16 117:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __COMPILER_BARRIER() __ASM volatile("":::"memory") 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 119:Drivers/CMSIS/Include/cmsis_gcc.h **** 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ######################### Startup and Lowlevel Init ######################## */ 121:Drivers/CMSIS/Include/cmsis_gcc.h **** 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Initializes data and bss sections 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details This default implementations initialized all data and additional bss 127:Drivers/CMSIS/Include/cmsis_gcc.h **** sections relying on .copy.table and .zero.table specified properly 128:Drivers/CMSIS/Include/cmsis_gcc.h **** in the used linker script. 129:Drivers/CMSIS/Include/cmsis_gcc.h **** 130:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) 132:Drivers/CMSIS/Include/cmsis_gcc.h **** { 133:Drivers/CMSIS/Include/cmsis_gcc.h **** extern void _start(void) __NO_RETURN; 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 135:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct { 136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t const* src; 137:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest; 138:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen; 139:Drivers/CMSIS/Include/cmsis_gcc.h **** } __copy_table_t; 140:Drivers/CMSIS/Include/cmsis_gcc.h **** 141:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct { 142:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest; 143:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen; 144:Drivers/CMSIS/Include/cmsis_gcc.h **** } __zero_table_t; 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 146:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_start__; 147:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_end__; 148:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_start__; 149:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_end__; 150:Drivers/CMSIS/Include/cmsis_gcc.h **** 151:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable 152:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; iwlen; ++i) { 153:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = pTable->src[i]; 154:Drivers/CMSIS/Include/cmsis_gcc.h **** } 155:Drivers/CMSIS/Include/cmsis_gcc.h **** } 156:Drivers/CMSIS/Include/cmsis_gcc.h **** 157:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable 158:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; iwlen; ++i) { 159:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = 0u; 160:Drivers/CMSIS/Include/cmsis_gcc.h **** } 161:Drivers/CMSIS/Include/cmsis_gcc.h **** } 162:Drivers/CMSIS/Include/cmsis_gcc.h **** 163:Drivers/CMSIS/Include/cmsis_gcc.h **** _start(); 164:Drivers/CMSIS/Include/cmsis_gcc.h **** } 165:Drivers/CMSIS/Include/cmsis_gcc.h **** 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START __cmsis_start 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 168:Drivers/CMSIS/Include/cmsis_gcc.h **** 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP __StackTop 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 172:Drivers/CMSIS/Include/cmsis_gcc.h **** 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT ARM GAS /tmp/ccdSoXH4.s page 17 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT __StackLimit 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 176:Drivers/CMSIS/Include/cmsis_gcc.h **** 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE __Vectors 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 180:Drivers/CMSIS/Include/cmsis_gcc.h **** 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 184:Drivers/CMSIS/Include/cmsis_gcc.h **** 185:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 186:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_SEAL 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_SEAL __StackSeal 188:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 189:Drivers/CMSIS/Include/cmsis_gcc.h **** 190:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_SIZE 191:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __TZ_STACK_SEAL_SIZE 8U 192:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 193:Drivers/CMSIS/Include/cmsis_gcc.h **** 194:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_VALUE 195:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL 196:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 197:Drivers/CMSIS/Include/cmsis_gcc.h **** 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 199:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { 200:Drivers/CMSIS/Include/cmsis_gcc.h **** *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; 201:Drivers/CMSIS/Include/cmsis_gcc.h **** } 202:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 203:Drivers/CMSIS/Include/cmsis_gcc.h **** 204:Drivers/CMSIS/Include/cmsis_gcc.h **** 205:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ 206:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 207:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions 208:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 209:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 210:Drivers/CMSIS/Include/cmsis_gcc.h **** 211:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. 212:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" 213:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ 214:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) 215:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) 216:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) 217:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) 218:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 219:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) 220:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) 221:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) 222:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 223:Drivers/CMSIS/Include/cmsis_gcc.h **** 224:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 225:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation 226:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. 227:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 228:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") 229:Drivers/CMSIS/Include/cmsis_gcc.h **** 230:Drivers/CMSIS/Include/cmsis_gcc.h **** /** ARM GAS /tmp/ccdSoXH4.s page 18 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt 232:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o 233:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 234:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi":::"memory") 235:Drivers/CMSIS/Include/cmsis_gcc.h **** 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 237:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 238:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event 239:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter 240:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. 241:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 242:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe":::"memory") 243:Drivers/CMSIS/Include/cmsis_gcc.h **** 244:Drivers/CMSIS/Include/cmsis_gcc.h **** 245:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 246:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event 247:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. 248:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 249:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 251:Drivers/CMSIS/Include/cmsis_gcc.h **** 252:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 253:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier 254:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, 255:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, 256:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. 257:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 258:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) 259:Drivers/CMSIS/Include/cmsis_gcc.h **** { 260:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); 261:Drivers/CMSIS/Include/cmsis_gcc.h **** } 262:Drivers/CMSIS/Include/cmsis_gcc.h **** 263:Drivers/CMSIS/Include/cmsis_gcc.h **** 264:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 265:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier 266:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. 267:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. 268:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 269:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) 270:Drivers/CMSIS/Include/cmsis_gcc.h **** { 271:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); 272:Drivers/CMSIS/Include/cmsis_gcc.h **** } 273:Drivers/CMSIS/Include/cmsis_gcc.h **** 274:Drivers/CMSIS/Include/cmsis_gcc.h **** 275:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 276:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier 277:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before 278:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. 279:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 280:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) 281:Drivers/CMSIS/Include/cmsis_gcc.h **** { 282:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); 283:Drivers/CMSIS/Include/cmsis_gcc.h **** } 284:Drivers/CMSIS/Include/cmsis_gcc.h **** 285:Drivers/CMSIS/Include/cmsis_gcc.h **** 286:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) ARM GAS /tmp/ccdSoXH4.s page 19 288:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 289:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 290:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 291:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 292:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) 293:Drivers/CMSIS/Include/cmsis_gcc.h **** { 294:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) 295:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); 296:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 297:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 298:Drivers/CMSIS/Include/cmsis_gcc.h **** 299:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 300:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 301:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 302:Drivers/CMSIS/Include/cmsis_gcc.h **** } 303:Drivers/CMSIS/Include/cmsis_gcc.h **** 304:Drivers/CMSIS/Include/cmsis_gcc.h **** 305:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 306:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) 307:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 308:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 309:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 310:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 311:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) 312:Drivers/CMSIS/Include/cmsis_gcc.h **** { 313:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 314:Drivers/CMSIS/Include/cmsis_gcc.h **** 315:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 316:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 317:Drivers/CMSIS/Include/cmsis_gcc.h **** } 318:Drivers/CMSIS/Include/cmsis_gcc.h **** 319:Drivers/CMSIS/Include/cmsis_gcc.h **** 320:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 321:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) 322:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam 323:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 324:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 325:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 326:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) 327:Drivers/CMSIS/Include/cmsis_gcc.h **** { 328:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 329:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); 330:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 331:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; 332:Drivers/CMSIS/Include/cmsis_gcc.h **** 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 334:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 335:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 336:Drivers/CMSIS/Include/cmsis_gcc.h **** } 337:Drivers/CMSIS/Include/cmsis_gcc.h **** 338:Drivers/CMSIS/Include/cmsis_gcc.h **** 339:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v 342:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate 343:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate 344:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value ARM GAS /tmp/ccdSoXH4.s page 20 345:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 346:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) 347:Drivers/CMSIS/Include/cmsis_gcc.h **** { 348:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; 349:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) 350:Drivers/CMSIS/Include/cmsis_gcc.h **** { 351:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; 352:Drivers/CMSIS/Include/cmsis_gcc.h **** } 353:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); 354:Drivers/CMSIS/Include/cmsis_gcc.h **** } 355:Drivers/CMSIS/Include/cmsis_gcc.h **** 356:Drivers/CMSIS/Include/cmsis_gcc.h **** 357:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 358:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint 359:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. 360:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula 361:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. 362:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break 363:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 364:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) 365:Drivers/CMSIS/Include/cmsis_gcc.h **** 366:Drivers/CMSIS/Include/cmsis_gcc.h **** 367:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value 369:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. 370:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 371:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 372:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 373:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) 374:Drivers/CMSIS/Include/cmsis_gcc.h **** { 375:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 377:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 378:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 379:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 380:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); 381:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 382:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ 383:Drivers/CMSIS/Include/cmsis_gcc.h **** 384:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ 385:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) 386:Drivers/CMSIS/Include/cmsis_gcc.h **** { 387:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; 388:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; 389:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; 390:Drivers/CMSIS/Include/cmsis_gcc.h **** } 391:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ 392:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 393:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 394:Drivers/CMSIS/Include/cmsis_gcc.h **** } 395:Drivers/CMSIS/Include/cmsis_gcc.h **** 396:Drivers/CMSIS/Include/cmsis_gcc.h **** 397:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 398:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Count leading zeros 399:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Counts the number of leading zeros of a data value. 400:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to count the leading zeros 401:Drivers/CMSIS/Include/cmsis_gcc.h **** \return number of leading zeros in value ARM GAS /tmp/ccdSoXH4.s page 21 402:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 403:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) 404:Drivers/CMSIS/Include/cmsis_gcc.h **** { 405:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Even though __builtin_clz produces a CLZ instruction on ARM, formally 406:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_clz(0) is undefined behaviour, so handle this case specially. 407:Drivers/CMSIS/Include/cmsis_gcc.h **** This guarantees ARM-compatible results if happening to compile on a non-ARM 408:Drivers/CMSIS/Include/cmsis_gcc.h **** target, and ensures the compiler doesn't decide to activate any 409:Drivers/CMSIS/Include/cmsis_gcc.h **** optimisations using the logic "value was passed to __builtin_clz, so it 410:Drivers/CMSIS/Include/cmsis_gcc.h **** is non-zero". 411:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a 412:Drivers/CMSIS/Include/cmsis_gcc.h **** single CLZ instruction. 413:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 414:Drivers/CMSIS/Include/cmsis_gcc.h **** if (value == 0U) 415:Drivers/CMSIS/Include/cmsis_gcc.h **** { 416:Drivers/CMSIS/Include/cmsis_gcc.h **** return 32U; 417:Drivers/CMSIS/Include/cmsis_gcc.h **** } 418:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_clz(value); 419:Drivers/CMSIS/Include/cmsis_gcc.h **** } 420:Drivers/CMSIS/Include/cmsis_gcc.h **** 421:Drivers/CMSIS/Include/cmsis_gcc.h **** 422:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 423:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 425:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 426:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 427:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (8 bit) 428:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 8 bit value. 429:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 430:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) 431:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 432:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) 433:Drivers/CMSIS/Include/cmsis_gcc.h **** { 434:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 435:Drivers/CMSIS/Include/cmsis_gcc.h **** 436:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 437:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); 438:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 439:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 440:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 441:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 442:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); 443:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 444:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); /* Add explicit type cast here */ 445:Drivers/CMSIS/Include/cmsis_gcc.h **** } 446:Drivers/CMSIS/Include/cmsis_gcc.h **** 447:Drivers/CMSIS/Include/cmsis_gcc.h **** 448:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 449:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (16 bit) 450:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 16 bit values. 451:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 452:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) 453:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 454:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) 455:Drivers/CMSIS/Include/cmsis_gcc.h **** { 456:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 457:Drivers/CMSIS/Include/cmsis_gcc.h **** 458:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) ARM GAS /tmp/ccdSoXH4.s page 22 459:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); 460:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 461:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 462:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 463:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 464:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); 465:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); /* Add explicit type cast here */ 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 469:Drivers/CMSIS/Include/cmsis_gcc.h **** 470:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 471:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (32 bit) 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 32 bit values. 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 479:Drivers/CMSIS/Include/cmsis_gcc.h **** 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } 483:Drivers/CMSIS/Include/cmsis_gcc.h **** 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 485:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 486:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (8 bit) 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 8 bit values. 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 490:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 491:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 492:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) 494:Drivers/CMSIS/Include/cmsis_gcc.h **** { 495:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 497:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); 498:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 499:Drivers/CMSIS/Include/cmsis_gcc.h **** } 500:Drivers/CMSIS/Include/cmsis_gcc.h **** 501:Drivers/CMSIS/Include/cmsis_gcc.h **** 502:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 503:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (16 bit) 504:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 16 bit values. 505:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 506:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 507:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 508:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 509:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 510:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) 511:Drivers/CMSIS/Include/cmsis_gcc.h **** { 512:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 513:Drivers/CMSIS/Include/cmsis_gcc.h **** 514:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); 515:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); ARM GAS /tmp/ccdSoXH4.s page 23 516:Drivers/CMSIS/Include/cmsis_gcc.h **** } 517:Drivers/CMSIS/Include/cmsis_gcc.h **** 518:Drivers/CMSIS/Include/cmsis_gcc.h **** 519:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 520:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (32 bit) 521:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 32 bit values. 522:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 530:Drivers/CMSIS/Include/cmsis_gcc.h **** 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } 534:Drivers/CMSIS/Include/cmsis_gcc.h **** 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 536:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 537:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Remove the exclusive lock 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Removes the exclusive lock which is created by LDREX. 539:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 540:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __CLREX(void) 541:Drivers/CMSIS/Include/cmsis_gcc.h **** { 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("clrex" ::: "memory"); 543:Drivers/CMSIS/Include/cmsis_gcc.h **** } 544:Drivers/CMSIS/Include/cmsis_gcc.h **** 545:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 546:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 547:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 548:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 549:Drivers/CMSIS/Include/cmsis_gcc.h **** 550:Drivers/CMSIS/Include/cmsis_gcc.h **** 551:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 552:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 553:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 554:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Signed Saturate 556:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Saturates a signed value. 557:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ARG1 Value to be saturated 558:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ARG2 Bit position to saturate to (1..32) 559:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Saturated value 560:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 561:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SSAT(ARG1, ARG2) \ 562:Drivers/CMSIS/Include/cmsis_gcc.h **** __extension__ \ 563:Drivers/CMSIS/Include/cmsis_gcc.h **** ({ \ 564:Drivers/CMSIS/Include/cmsis_gcc.h **** int32_t __RES, __ARG1 = (ARG1); \ 565:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ 566:Drivers/CMSIS/Include/cmsis_gcc.h **** __RES; \ 567:Drivers/CMSIS/Include/cmsis_gcc.h **** }) 568:Drivers/CMSIS/Include/cmsis_gcc.h **** 569:Drivers/CMSIS/Include/cmsis_gcc.h **** 570:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 571:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Unsigned Saturate 572:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Saturates an unsigned value. ARM GAS /tmp/ccdSoXH4.s page 24 573:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ARG1 Value to be saturated 574:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ARG2 Bit position to saturate to (0..31) 575:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Saturated value 576:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 577:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USAT(ARG1, ARG2) \ 578:Drivers/CMSIS/Include/cmsis_gcc.h **** __extension__ \ 579:Drivers/CMSIS/Include/cmsis_gcc.h **** ({ \ 580:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t __RES, __ARG1 = (ARG1); \ 581:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ 582:Drivers/CMSIS/Include/cmsis_gcc.h **** __RES; \ 583:Drivers/CMSIS/Include/cmsis_gcc.h **** }) 584:Drivers/CMSIS/Include/cmsis_gcc.h **** 585:Drivers/CMSIS/Include/cmsis_gcc.h **** 586:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 587:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right with Extend (32 bit) 588:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Moves each bit of a bitstring right by one bit. 589:Drivers/CMSIS/Include/cmsis_gcc.h **** The carry input is shifted in at the left end of the bitstring. 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to rotate 591:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value 592:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 593:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) 594:Drivers/CMSIS/Include/cmsis_gcc.h **** { 595:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 596:Drivers/CMSIS/Include/cmsis_gcc.h **** 597:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 598:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 599:Drivers/CMSIS/Include/cmsis_gcc.h **** } 600:Drivers/CMSIS/Include/cmsis_gcc.h **** 601:Drivers/CMSIS/Include/cmsis_gcc.h **** 602:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 603:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDRT Unprivileged (8 bit) 604:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged LDRT instruction for 8 bit value. 605:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 606:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) 607:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 608:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) 609:Drivers/CMSIS/Include/cmsis_gcc.h **** { 610:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 611:Drivers/CMSIS/Include/cmsis_gcc.h **** 612:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 613:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); 614:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 615:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 616:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 617:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 618:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 620:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); /* Add explicit type cast here */ 621:Drivers/CMSIS/Include/cmsis_gcc.h **** } 622:Drivers/CMSIS/Include/cmsis_gcc.h **** 623:Drivers/CMSIS/Include/cmsis_gcc.h **** 624:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 625:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDRT Unprivileged (16 bit) 626:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged LDRT instruction for 16 bit values. 627:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 628:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) 629:Drivers/CMSIS/Include/cmsis_gcc.h **** */ ARM GAS /tmp/ccdSoXH4.s page 25 630:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) 631:Drivers/CMSIS/Include/cmsis_gcc.h **** { 632:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 633:Drivers/CMSIS/Include/cmsis_gcc.h **** 634:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 635:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); 636:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 637:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 638:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 639:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 640:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); 641:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 642:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); /* Add explicit type cast here */ 643:Drivers/CMSIS/Include/cmsis_gcc.h **** } 644:Drivers/CMSIS/Include/cmsis_gcc.h **** 645:Drivers/CMSIS/Include/cmsis_gcc.h **** 646:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 647:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDRT Unprivileged (32 bit) 648:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged LDRT instruction for 32 bit values. 649:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 650:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) 651:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 652:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) 653:Drivers/CMSIS/Include/cmsis_gcc.h **** { 654:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 655:Drivers/CMSIS/Include/cmsis_gcc.h **** 656:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); 657:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 658:Drivers/CMSIS/Include/cmsis_gcc.h **** } 659:Drivers/CMSIS/Include/cmsis_gcc.h **** 660:Drivers/CMSIS/Include/cmsis_gcc.h **** 661:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 662:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STRT Unprivileged (8 bit) 663:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged STRT instruction for 8 bit values. 664:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 665:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 666:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 667:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) 668:Drivers/CMSIS/Include/cmsis_gcc.h **** { 669:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); 670:Drivers/CMSIS/Include/cmsis_gcc.h **** } 671:Drivers/CMSIS/Include/cmsis_gcc.h **** 672:Drivers/CMSIS/Include/cmsis_gcc.h **** 673:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 674:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STRT Unprivileged (16 bit) 675:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged STRT instruction for 16 bit values. 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { 681:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); 682:Drivers/CMSIS/Include/cmsis_gcc.h **** } 683:Drivers/CMSIS/Include/cmsis_gcc.h **** 684:Drivers/CMSIS/Include/cmsis_gcc.h **** 685:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 686:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STRT Unprivileged (32 bit) ARM GAS /tmp/ccdSoXH4.s page 26 687:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged STRT instruction for 32 bit values. 688:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 689:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 690:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 691:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) 692:Drivers/CMSIS/Include/cmsis_gcc.h **** { 693:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); 694:Drivers/CMSIS/Include/cmsis_gcc.h **** } 695:Drivers/CMSIS/Include/cmsis_gcc.h **** 696:Drivers/CMSIS/Include/cmsis_gcc.h **** #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 697:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 698:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 699:Drivers/CMSIS/Include/cmsis_gcc.h **** 700:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 701:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Signed Saturate 702:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Saturates a signed value. 703:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to be saturated 704:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] sat Bit position to saturate to (1..32) 705:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Saturated value 706:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 707:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) 708:Drivers/CMSIS/Include/cmsis_gcc.h **** { 709:Drivers/CMSIS/Include/cmsis_gcc.h **** if ((sat >= 1U) && (sat <= 32U)) 710:Drivers/CMSIS/Include/cmsis_gcc.h **** { 711:Drivers/CMSIS/Include/cmsis_gcc.h **** const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); 712:Drivers/CMSIS/Include/cmsis_gcc.h **** const int32_t min = -1 - max ; 713:Drivers/CMSIS/Include/cmsis_gcc.h **** if (val > max) 714:Drivers/CMSIS/Include/cmsis_gcc.h **** { 715:Drivers/CMSIS/Include/cmsis_gcc.h **** return max; 716:Drivers/CMSIS/Include/cmsis_gcc.h **** } 717:Drivers/CMSIS/Include/cmsis_gcc.h **** else if (val < min) 718:Drivers/CMSIS/Include/cmsis_gcc.h **** { 719:Drivers/CMSIS/Include/cmsis_gcc.h **** return min; 720:Drivers/CMSIS/Include/cmsis_gcc.h **** } 721:Drivers/CMSIS/Include/cmsis_gcc.h **** } 722:Drivers/CMSIS/Include/cmsis_gcc.h **** return val; 723:Drivers/CMSIS/Include/cmsis_gcc.h **** } 724:Drivers/CMSIS/Include/cmsis_gcc.h **** 725:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 726:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Unsigned Saturate 727:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Saturates an unsigned value. 728:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to be saturated 729:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] sat Bit position to saturate to (0..31) 730:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Saturated value 731:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) 733:Drivers/CMSIS/Include/cmsis_gcc.h **** { 734:Drivers/CMSIS/Include/cmsis_gcc.h **** if (sat <= 31U) 735:Drivers/CMSIS/Include/cmsis_gcc.h **** { 736:Drivers/CMSIS/Include/cmsis_gcc.h **** const uint32_t max = ((1U << sat) - 1U); 737:Drivers/CMSIS/Include/cmsis_gcc.h **** if (val > (int32_t)max) 738:Drivers/CMSIS/Include/cmsis_gcc.h **** { 739:Drivers/CMSIS/Include/cmsis_gcc.h **** return max; 740:Drivers/CMSIS/Include/cmsis_gcc.h **** } 741:Drivers/CMSIS/Include/cmsis_gcc.h **** else if (val < 0) 742:Drivers/CMSIS/Include/cmsis_gcc.h **** { 743:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; ARM GAS /tmp/ccdSoXH4.s page 27 744:Drivers/CMSIS/Include/cmsis_gcc.h **** } 745:Drivers/CMSIS/Include/cmsis_gcc.h **** } 746:Drivers/CMSIS/Include/cmsis_gcc.h **** return (uint32_t)val; 747:Drivers/CMSIS/Include/cmsis_gcc.h **** } 748:Drivers/CMSIS/Include/cmsis_gcc.h **** 749:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 751:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 752:Drivers/CMSIS/Include/cmsis_gcc.h **** 753:Drivers/CMSIS/Include/cmsis_gcc.h **** 754:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 755:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 756:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 757:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire (8 bit) 758:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDAB instruction for 8 bit value. 759:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 760:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) 761:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 762:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) 763:Drivers/CMSIS/Include/cmsis_gcc.h **** { 764:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 765:Drivers/CMSIS/Include/cmsis_gcc.h **** 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 767:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); 768:Drivers/CMSIS/Include/cmsis_gcc.h **** } 769:Drivers/CMSIS/Include/cmsis_gcc.h **** 770:Drivers/CMSIS/Include/cmsis_gcc.h **** 771:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 772:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire (16 bit) 773:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDAH instruction for 16 bit values. 774:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 775:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) 776:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 777:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) 778:Drivers/CMSIS/Include/cmsis_gcc.h **** { 779:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 780:Drivers/CMSIS/Include/cmsis_gcc.h **** 781:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); 783:Drivers/CMSIS/Include/cmsis_gcc.h **** } 784:Drivers/CMSIS/Include/cmsis_gcc.h **** 785:Drivers/CMSIS/Include/cmsis_gcc.h **** 786:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 787:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire (32 bit) 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDA instruction for 32 bit values. 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { 794:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 795:Drivers/CMSIS/Include/cmsis_gcc.h **** 796:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 797:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 798:Drivers/CMSIS/Include/cmsis_gcc.h **** } 799:Drivers/CMSIS/Include/cmsis_gcc.h **** 800:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccdSoXH4.s page 28 801:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 802:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release (8 bit) 803:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STLB instruction for 8 bit values. 804:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 805:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 806:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 807:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) 808:Drivers/CMSIS/Include/cmsis_gcc.h **** { 809:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 810:Drivers/CMSIS/Include/cmsis_gcc.h **** } 811:Drivers/CMSIS/Include/cmsis_gcc.h **** 812:Drivers/CMSIS/Include/cmsis_gcc.h **** 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 814:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release (16 bit) 815:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STLH instruction for 16 bit values. 816:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 817:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 818:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 819:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) 820:Drivers/CMSIS/Include/cmsis_gcc.h **** { 821:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 822:Drivers/CMSIS/Include/cmsis_gcc.h **** } 823:Drivers/CMSIS/Include/cmsis_gcc.h **** 824:Drivers/CMSIS/Include/cmsis_gcc.h **** 825:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 826:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release (32 bit) 827:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STL instruction for 32 bit values. 828:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 829:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 830:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 831:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) 832:Drivers/CMSIS/Include/cmsis_gcc.h **** { 833:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 834:Drivers/CMSIS/Include/cmsis_gcc.h **** } 835:Drivers/CMSIS/Include/cmsis_gcc.h **** 836:Drivers/CMSIS/Include/cmsis_gcc.h **** 837:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 838:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire Exclusive (8 bit) 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDAB exclusive instruction for 8 bit value. 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 841:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) 842:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 843:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) 844:Drivers/CMSIS/Include/cmsis_gcc.h **** { 845:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 846:Drivers/CMSIS/Include/cmsis_gcc.h **** 847:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 848:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); 849:Drivers/CMSIS/Include/cmsis_gcc.h **** } 850:Drivers/CMSIS/Include/cmsis_gcc.h **** 851:Drivers/CMSIS/Include/cmsis_gcc.h **** 852:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 853:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire Exclusive (16 bit) 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDAH exclusive instruction for 16 bit values. 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 856:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) 857:Drivers/CMSIS/Include/cmsis_gcc.h **** */ ARM GAS /tmp/ccdSoXH4.s page 29 858:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) 859:Drivers/CMSIS/Include/cmsis_gcc.h **** { 860:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 861:Drivers/CMSIS/Include/cmsis_gcc.h **** 862:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 863:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); 864:Drivers/CMSIS/Include/cmsis_gcc.h **** } 865:Drivers/CMSIS/Include/cmsis_gcc.h **** 866:Drivers/CMSIS/Include/cmsis_gcc.h **** 867:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 868:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire Exclusive (32 bit) 869:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDA exclusive instruction for 32 bit values. 870:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 871:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) 872:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 873:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) 874:Drivers/CMSIS/Include/cmsis_gcc.h **** { 875:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 876:Drivers/CMSIS/Include/cmsis_gcc.h **** 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 878:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 879:Drivers/CMSIS/Include/cmsis_gcc.h **** } 880:Drivers/CMSIS/Include/cmsis_gcc.h **** 881:Drivers/CMSIS/Include/cmsis_gcc.h **** 882:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 883:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release Exclusive (8 bit) 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STLB exclusive instruction for 8 bit values. 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 886:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 887:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 888:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 889:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) 891:Drivers/CMSIS/Include/cmsis_gcc.h **** { 892:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 893:Drivers/CMSIS/Include/cmsis_gcc.h **** 894:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem 895:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 896:Drivers/CMSIS/Include/cmsis_gcc.h **** } 897:Drivers/CMSIS/Include/cmsis_gcc.h **** 898:Drivers/CMSIS/Include/cmsis_gcc.h **** 899:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 900:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release Exclusive (16 bit) 901:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STLH exclusive instruction for 16 bit values. 902:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 903:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 904:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 905:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 906:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) 908:Drivers/CMSIS/Include/cmsis_gcc.h **** { 909:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 910:Drivers/CMSIS/Include/cmsis_gcc.h **** 911:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem 912:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 913:Drivers/CMSIS/Include/cmsis_gcc.h **** } 914:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccdSoXH4.s page 30 915:Drivers/CMSIS/Include/cmsis_gcc.h **** 916:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release Exclusive (32 bit) 918:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STL exclusive instruction for 32 bit values. 919:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 920:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 921:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 922:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 923:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 924:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) 925:Drivers/CMSIS/Include/cmsis_gcc.h **** { 926:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 927:Drivers/CMSIS/Include/cmsis_gcc.h **** 928:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memo 929:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 930:Drivers/CMSIS/Include/cmsis_gcc.h **** } 931:Drivers/CMSIS/Include/cmsis_gcc.h **** 932:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 933:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 934:Drivers/CMSIS/Include/cmsis_gcc.h **** 935:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ 936:Drivers/CMSIS/Include/cmsis_gcc.h **** 937:Drivers/CMSIS/Include/cmsis_gcc.h **** 938:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ 939:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface 940:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 941:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 942:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 943:Drivers/CMSIS/Include/cmsis_gcc.h **** 944:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 945:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts 946:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. 947:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 948:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 949:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) 950:Drivers/CMSIS/Include/cmsis_gcc.h **** { 951:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); 952:Drivers/CMSIS/Include/cmsis_gcc.h **** } 953:Drivers/CMSIS/Include/cmsis_gcc.h **** 954:Drivers/CMSIS/Include/cmsis_gcc.h **** 955:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 956:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts 957:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting special-purpose register PRIMASK. 958:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 959:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 960:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) 327 .loc 2 960 27 view .LVU82 328 .LBB11: 961:Drivers/CMSIS/Include/cmsis_gcc.h **** { 962:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); 329 .loc 2 962 3 view .LVU83 330 .syntax unified 331 @ 962 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 332 0000 72B6 cpsid i 333 @ 0 "" 2 334 .thumb 335 .syntax unified ARM GAS /tmp/ccdSoXH4.s page 31 336 .L10: 337 .LBE11: 338 .LBE10: 409:Core/Src/main.c **** while (1) 339 .loc 1 409 3 view .LVU84 410:Core/Src/main.c **** { 411:Core/Src/main.c **** } 340 .loc 1 411 3 view .LVU85 409:Core/Src/main.c **** while (1) 341 .loc 1 409 9 view .LVU86 342 0002 FEE7 b .L10 343 .cfi_endproc 344 .LFE248: 346 .section .text.MX_ADC1_Init,"ax",%progbits 347 .align 1 348 .syntax unified 349 .thumb 350 .thumb_func 352 MX_ADC1_Init: 353 .LFB245: 272:Core/Src/main.c **** 354 .loc 1 272 1 view -0 355 .cfi_startproc 356 @ args = 0, pretend = 0, frame = 16 357 @ frame_needed = 0, uses_anonymous_args = 0 358 0000 00B5 push {lr} 359 .LCFI6: 360 .cfi_def_cfa_offset 4 361 .cfi_offset 14, -4 362 0002 85B0 sub sp, sp, #20 363 .LCFI7: 364 .cfi_def_cfa_offset 24 278:Core/Src/main.c **** 365 .loc 1 278 3 view .LVU88 278:Core/Src/main.c **** 366 .loc 1 278 26 is_stmt 0 view .LVU89 367 0004 0023 movs r3, #0 368 0006 0093 str r3, [sp] 369 0008 0193 str r3, [sp, #4] 370 000a 0293 str r3, [sp, #8] 371 000c 0393 str r3, [sp, #12] 286:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; 372 .loc 1 286 3 is_stmt 1 view .LVU90 286:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; 373 .loc 1 286 18 is_stmt 0 view .LVU91 374 000e 1648 ldr r0, .L17 375 0010 164A ldr r2, .L17+4 376 0012 0260 str r2, [r0] 287:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; 377 .loc 1 287 3 is_stmt 1 view .LVU92 287:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; 378 .loc 1 287 29 is_stmt 0 view .LVU93 379 0014 4FF48032 mov r2, #65536 380 0018 4260 str r2, [r0, #4] 288:Core/Src/main.c **** hadc1.Init.ScanConvMode = DISABLE; 381 .loc 1 288 3 is_stmt 1 view .LVU94 288:Core/Src/main.c **** hadc1.Init.ScanConvMode = DISABLE; ARM GAS /tmp/ccdSoXH4.s page 32 382 .loc 1 288 25 is_stmt 0 view .LVU95 383 001a 8360 str r3, [r0, #8] 289:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; 384 .loc 1 289 3 is_stmt 1 view .LVU96 289:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; 385 .loc 1 289 27 is_stmt 0 view .LVU97 386 001c 0361 str r3, [r0, #16] 290:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; 387 .loc 1 290 3 is_stmt 1 view .LVU98 290:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; 388 .loc 1 290 33 is_stmt 0 view .LVU99 389 001e 0376 strb r3, [r0, #24] 291:Core/Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 390 .loc 1 291 3 is_stmt 1 view .LVU100 291:Core/Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 391 .loc 1 291 36 is_stmt 0 view .LVU101 392 0020 80F82030 strb r3, [r0, #32] 292:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_Ext_IT11; 393 .loc 1 292 3 is_stmt 1 view .LVU102 292:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_Ext_IT11; 394 .loc 1 292 35 is_stmt 0 view .LVU103 395 0024 4FF08052 mov r2, #268435456 396 0028 C262 str r2, [r0, #44] 293:Core/Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 397 .loc 1 293 3 is_stmt 1 view .LVU104 293:Core/Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 398 .loc 1 293 31 is_stmt 0 view .LVU105 399 002a 4FF07062 mov r2, #251658240 400 002e 8262 str r2, [r0, #40] 294:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1; 401 .loc 1 294 3 is_stmt 1 view .LVU106 294:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1; 402 .loc 1 294 24 is_stmt 0 view .LVU107 403 0030 C360 str r3, [r0, #12] 295:Core/Src/main.c **** hadc1.Init.DMAContinuousRequests = ENABLE; 404 .loc 1 295 3 is_stmt 1 view .LVU108 295:Core/Src/main.c **** hadc1.Init.DMAContinuousRequests = ENABLE; 405 .loc 1 295 30 is_stmt 0 view .LVU109 406 0032 0123 movs r3, #1 407 0034 C361 str r3, [r0, #28] 296:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 408 .loc 1 296 3 is_stmt 1 view .LVU110 296:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 409 .loc 1 296 36 is_stmt 0 view .LVU111 410 0036 80F83030 strb r3, [r0, #48] 297:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) 411 .loc 1 297 3 is_stmt 1 view .LVU112 297:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) 412 .loc 1 297 27 is_stmt 0 view .LVU113 413 003a 4361 str r3, [r0, #20] 298:Core/Src/main.c **** { 414 .loc 1 298 3 is_stmt 1 view .LVU114 298:Core/Src/main.c **** { 415 .loc 1 298 7 is_stmt 0 view .LVU115 416 003c FFF7FEFF bl HAL_ADC_Init 417 .LVL12: 298:Core/Src/main.c **** { ARM GAS /tmp/ccdSoXH4.s page 33 418 .loc 1 298 6 discriminator 1 view .LVU116 419 0040 68B9 cbnz r0, .L15 305:Core/Src/main.c **** sConfig.Rank = 1; 420 .loc 1 305 3 is_stmt 1 view .LVU117 305:Core/Src/main.c **** sConfig.Rank = 1; 421 .loc 1 305 19 is_stmt 0 view .LVU118 422 0042 0323 movs r3, #3 423 0044 0093 str r3, [sp] 306:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; 424 .loc 1 306 3 is_stmt 1 view .LVU119 306:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; 425 .loc 1 306 16 is_stmt 0 view .LVU120 426 0046 0123 movs r3, #1 427 0048 0193 str r3, [sp, #4] 307:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 428 .loc 1 307 3 is_stmt 1 view .LVU121 307:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 429 .loc 1 307 24 is_stmt 0 view .LVU122 430 004a 0023 movs r3, #0 431 004c 0293 str r3, [sp, #8] 308:Core/Src/main.c **** { 432 .loc 1 308 3 is_stmt 1 view .LVU123 308:Core/Src/main.c **** { 433 .loc 1 308 7 is_stmt 0 view .LVU124 434 004e 6946 mov r1, sp 435 0050 0548 ldr r0, .L17 436 0052 FFF7FEFF bl HAL_ADC_ConfigChannel 437 .LVL13: 308:Core/Src/main.c **** { 438 .loc 1 308 6 discriminator 1 view .LVU125 439 0056 20B9 cbnz r0, .L16 316:Core/Src/main.c **** 440 .loc 1 316 1 view .LVU126 441 0058 05B0 add sp, sp, #20 442 .LCFI8: 443 .cfi_remember_state 444 .cfi_def_cfa_offset 4 445 @ sp needed 446 005a 5DF804FB ldr pc, [sp], #4 447 .L15: 448 .LCFI9: 449 .cfi_restore_state 300:Core/Src/main.c **** } 450 .loc 1 300 5 is_stmt 1 view .LVU127 451 005e FFF7FEFF bl Error_Handler 452 .LVL14: 453 .L16: 310:Core/Src/main.c **** } 454 .loc 1 310 5 view .LVU128 455 0062 FFF7FEFF bl Error_Handler 456 .LVL15: 457 .L18: 458 0066 00BF .align 2 459 .L17: 460 0068 00000000 .word hadc1 461 006c 00200140 .word 1073815552 462 .cfi_endproc ARM GAS /tmp/ccdSoXH4.s page 34 463 .LFE245: 465 .section .text.SystemClock_Config,"ax",%progbits 466 .align 1 467 .global SystemClock_Config 468 .syntax unified 469 .thumb 470 .thumb_func 472 SystemClock_Config: 473 .LFB244: 226:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 474 .loc 1 226 1 view -0 475 .cfi_startproc 476 @ args = 0, pretend = 0, frame = 80 477 @ frame_needed = 0, uses_anonymous_args = 0 478 0000 00B5 push {lr} 479 .LCFI10: 480 .cfi_def_cfa_offset 4 481 .cfi_offset 14, -4 482 0002 95B0 sub sp, sp, #84 483 .LCFI11: 484 .cfi_def_cfa_offset 88 227:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 485 .loc 1 227 3 view .LVU130 227:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 486 .loc 1 227 22 is_stmt 0 view .LVU131 487 0004 3022 movs r2, #48 488 0006 0021 movs r1, #0 489 0008 08A8 add r0, sp, #32 490 000a FFF7FEFF bl memset 491 .LVL16: 228:Core/Src/main.c **** 492 .loc 1 228 3 is_stmt 1 view .LVU132 228:Core/Src/main.c **** 493 .loc 1 228 22 is_stmt 0 view .LVU133 494 000e 0023 movs r3, #0 495 0010 0393 str r3, [sp, #12] 496 0012 0493 str r3, [sp, #16] 497 0014 0593 str r3, [sp, #20] 498 0016 0693 str r3, [sp, #24] 499 0018 0793 str r3, [sp, #28] 232:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 500 .loc 1 232 3 is_stmt 1 view .LVU134 501 .LBB12: 232:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 502 .loc 1 232 3 view .LVU135 503 001a 0193 str r3, [sp, #4] 232:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 504 .loc 1 232 3 view .LVU136 505 001c 214A ldr r2, .L25 506 001e 116C ldr r1, [r2, #64] 507 0020 41F08051 orr r1, r1, #268435456 508 0024 1164 str r1, [r2, #64] 232:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 509 .loc 1 232 3 view .LVU137 510 0026 126C ldr r2, [r2, #64] 511 0028 02F08052 and r2, r2, #268435456 512 002c 0192 str r2, [sp, #4] ARM GAS /tmp/ccdSoXH4.s page 35 232:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 513 .loc 1 232 3 view .LVU138 514 002e 019A ldr r2, [sp, #4] 515 .LBE12: 232:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 516 .loc 1 232 3 view .LVU139 233:Core/Src/main.c **** 517 .loc 1 233 3 view .LVU140 518 .LBB13: 233:Core/Src/main.c **** 519 .loc 1 233 3 view .LVU141 520 0030 0293 str r3, [sp, #8] 233:Core/Src/main.c **** 521 .loc 1 233 3 view .LVU142 522 0032 1D4B ldr r3, .L25+4 523 0034 1A68 ldr r2, [r3] 524 0036 42F44042 orr r2, r2, #49152 525 003a 1A60 str r2, [r3] 233:Core/Src/main.c **** 526 .loc 1 233 3 view .LVU143 527 003c 1B68 ldr r3, [r3] 528 003e 03F44043 and r3, r3, #49152 529 0042 0293 str r3, [sp, #8] 233:Core/Src/main.c **** 530 .loc 1 233 3 view .LVU144 531 0044 029B ldr r3, [sp, #8] 532 .LBE13: 233:Core/Src/main.c **** 533 .loc 1 233 3 view .LVU145 238:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 534 .loc 1 238 3 view .LVU146 238:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 535 .loc 1 238 36 is_stmt 0 view .LVU147 536 0046 0123 movs r3, #1 537 0048 0893 str r3, [sp, #32] 239:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 538 .loc 1 239 3 is_stmt 1 view .LVU148 239:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 539 .loc 1 239 30 is_stmt 0 view .LVU149 540 004a 4FF48033 mov r3, #65536 541 004e 0993 str r3, [sp, #36] 240:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 542 .loc 1 240 3 is_stmt 1 view .LVU150 240:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 543 .loc 1 240 34 is_stmt 0 view .LVU151 544 0050 0223 movs r3, #2 545 0052 0E93 str r3, [sp, #56] 241:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 8; 546 .loc 1 241 3 is_stmt 1 view .LVU152 241:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 8; 547 .loc 1 241 35 is_stmt 0 view .LVU153 548 0054 4FF48002 mov r2, #4194304 549 0058 0F92 str r2, [sp, #60] 242:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 336; 550 .loc 1 242 3 is_stmt 1 view .LVU154 242:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 336; 551 .loc 1 242 30 is_stmt 0 view .LVU155 ARM GAS /tmp/ccdSoXH4.s page 36 552 005a 0822 movs r2, #8 553 005c 1092 str r2, [sp, #64] 243:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 554 .loc 1 243 3 is_stmt 1 view .LVU156 243:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 555 .loc 1 243 30 is_stmt 0 view .LVU157 556 005e 4FF4A872 mov r2, #336 557 0062 1192 str r2, [sp, #68] 244:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 7; 558 .loc 1 244 3 is_stmt 1 view .LVU158 244:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 7; 559 .loc 1 244 30 is_stmt 0 view .LVU159 560 0064 1293 str r3, [sp, #72] 245:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 561 .loc 1 245 3 is_stmt 1 view .LVU160 245:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 562 .loc 1 245 30 is_stmt 0 view .LVU161 563 0066 0723 movs r3, #7 564 0068 1393 str r3, [sp, #76] 246:Core/Src/main.c **** { 565 .loc 1 246 3 is_stmt 1 view .LVU162 246:Core/Src/main.c **** { 566 .loc 1 246 7 is_stmt 0 view .LVU163 567 006a 08A8 add r0, sp, #32 568 006c FFF7FEFF bl HAL_RCC_OscConfig 569 .LVL17: 246:Core/Src/main.c **** { 570 .loc 1 246 6 discriminator 1 view .LVU164 571 0070 98B9 cbnz r0, .L23 253:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 572 .loc 1 253 3 is_stmt 1 view .LVU165 253:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 573 .loc 1 253 31 is_stmt 0 view .LVU166 574 0072 0F23 movs r3, #15 575 0074 0393 str r3, [sp, #12] 255:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 576 .loc 1 255 3 is_stmt 1 view .LVU167 255:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 577 .loc 1 255 34 is_stmt 0 view .LVU168 578 0076 0223 movs r3, #2 579 0078 0493 str r3, [sp, #16] 256:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 580 .loc 1 256 3 is_stmt 1 view .LVU169 256:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 581 .loc 1 256 35 is_stmt 0 view .LVU170 582 007a 0023 movs r3, #0 583 007c 0593 str r3, [sp, #20] 257:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 584 .loc 1 257 3 is_stmt 1 view .LVU171 257:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 585 .loc 1 257 36 is_stmt 0 view .LVU172 586 007e 4FF4A053 mov r3, #5120 587 0082 0693 str r3, [sp, #24] 258:Core/Src/main.c **** 588 .loc 1 258 3 is_stmt 1 view .LVU173 258:Core/Src/main.c **** 589 .loc 1 258 36 is_stmt 0 view .LVU174 ARM GAS /tmp/ccdSoXH4.s page 37 590 0084 4FF48053 mov r3, #4096 591 0088 0793 str r3, [sp, #28] 260:Core/Src/main.c **** { 592 .loc 1 260 3 is_stmt 1 view .LVU175 260:Core/Src/main.c **** { 593 .loc 1 260 7 is_stmt 0 view .LVU176 594 008a 0521 movs r1, #5 595 008c 03A8 add r0, sp, #12 596 008e FFF7FEFF bl HAL_RCC_ClockConfig 597 .LVL18: 260:Core/Src/main.c **** { 598 .loc 1 260 6 discriminator 1 view .LVU177 599 0092 20B9 cbnz r0, .L24 264:Core/Src/main.c **** 600 .loc 1 264 1 view .LVU178 601 0094 15B0 add sp, sp, #84 602 .LCFI12: 603 .cfi_remember_state 604 .cfi_def_cfa_offset 4 605 @ sp needed 606 0096 5DF804FB ldr pc, [sp], #4 607 .L23: 608 .LCFI13: 609 .cfi_restore_state 248:Core/Src/main.c **** } 610 .loc 1 248 5 is_stmt 1 view .LVU179 611 009a FFF7FEFF bl Error_Handler 612 .LVL19: 613 .L24: 262:Core/Src/main.c **** } 614 .loc 1 262 5 view .LVU180 615 009e FFF7FEFF bl Error_Handler 616 .LVL20: 617 .L26: 618 00a2 00BF .align 2 619 .L25: 620 00a4 00380240 .word 1073887232 621 00a8 00700040 .word 1073770496 622 .cfi_endproc 623 .LFE244: 625 .section .text.main,"ax",%progbits 626 .align 1 627 .global main 628 .syntax unified 629 .thumb 630 .thumb_func 632 main: 633 .LFB243: 91:Core/Src/main.c **** 634 .loc 1 91 1 view -0 635 .cfi_startproc 636 @ args = 0, pretend = 0, frame = 0 637 @ frame_needed = 0, uses_anonymous_args = 0 638 0000 F8B5 push {r3, r4, r5, r6, r7, lr} 639 .LCFI14: 640 .cfi_def_cfa_offset 24 641 .cfi_offset 3, -24 ARM GAS /tmp/ccdSoXH4.s page 38 642 .cfi_offset 4, -20 643 .cfi_offset 5, -16 644 .cfi_offset 6, -12 645 .cfi_offset 7, -8 646 .cfi_offset 14, -4 100:Core/Src/main.c **** 647 .loc 1 100 3 view .LVU182 648 0002 FFF7FEFF bl HAL_Init 649 .LVL21: 107:Core/Src/main.c **** 650 .loc 1 107 3 view .LVU183 651 0006 FFF7FEFF bl SystemClock_Config 652 .LVL22: 114:Core/Src/main.c **** MX_DMA_Init(); 653 .loc 1 114 3 view .LVU184 654 000a FFF7FEFF bl MX_GPIO_Init 655 .LVL23: 115:Core/Src/main.c **** MX_ADC1_Init(); 656 .loc 1 115 3 view .LVU185 657 000e FFF7FEFF bl MX_DMA_Init 658 .LVL24: 116:Core/Src/main.c **** MX_USB_DEVICE_Init(); 659 .loc 1 116 3 view .LVU186 660 0012 FFF7FEFF bl MX_ADC1_Init 661 .LVL25: 117:Core/Src/main.c **** /* USER CODE BEGIN 2 */ 662 .loc 1 117 3 view .LVU187 663 0016 FFF7FEFF bl MX_USB_DEVICE_Init 664 .LVL26: 119:Core/Src/main.c **** HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADC1_buff_circular, ADC_BUFF_SIZE); 665 .loc 1 119 3 view .LVU188 666 001a 0122 movs r2, #1 667 001c 8021 movs r1, #128 668 001e 9348 ldr r0, .L35 669 0020 FFF7FEFF bl HAL_GPIO_WritePin 670 .LVL27: 120:Core/Src/main.c **** 671 .loc 1 120 3 view .LVU189 672 0024 3222 movs r2, #50 673 0026 9249 ldr r1, .L35+4 674 0028 9248 ldr r0, .L35+8 675 002a FFF7FEFF bl HAL_ADC_Start_DMA 676 .LVL28: 122:Core/Src/main.c **** ADC_proc_shadow.N = 0; 677 .loc 1 122 3 view .LVU190 122:Core/Src/main.c **** ADC_proc_shadow.N = 0; 678 .loc 1 122 26 is_stmt 0 view .LVU191 679 002e 924A ldr r2, .L35+12 680 0030 0023 movs r3, #0 681 0032 1370 strb r3, [r2] 123:Core/Src/main.c **** ADC_proc_shadow.sum_ON = 0; 682 .loc 1 123 3 is_stmt 1 view .LVU192 123:Core/Src/main.c **** ADC_proc_shadow.sum_ON = 0; 683 .loc 1 123 21 is_stmt 0 view .LVU193 684 0034 9361 str r3, [r2, #24] 124:Core/Src/main.c **** ADC_proc_shadow.avg_ON = 0; 685 .loc 1 124 3 is_stmt 1 view .LVU194 ARM GAS /tmp/ccdSoXH4.s page 39 124:Core/Src/main.c **** ADC_proc_shadow.avg_ON = 0; 686 .loc 1 124 26 is_stmt 0 view .LVU195 687 0036 9360 str r3, [r2, #8] 125:Core/Src/main.c **** ADC_proc_shadow.sum_OFF = 0; 688 .loc 1 125 3 is_stmt 1 view .LVU196 125:Core/Src/main.c **** ADC_proc_shadow.sum_OFF = 0; 689 .loc 1 125 26 is_stmt 0 view .LVU197 690 0038 1361 str r3, [r2, #16] 126:Core/Src/main.c **** ADC_proc_shadow.avg_OFF = 0; 691 .loc 1 126 3 is_stmt 1 view .LVU198 126:Core/Src/main.c **** ADC_proc_shadow.avg_OFF = 0; 692 .loc 1 126 27 is_stmt 0 view .LVU199 693 003a D360 str r3, [r2, #12] 127:Core/Src/main.c **** 694 .loc 1 127 3 is_stmt 1 view .LVU200 127:Core/Src/main.c **** 695 .loc 1 127 27 is_stmt 0 view .LVU201 696 003c 5361 str r3, [r2, #20] 129:Core/Src/main.c **** ADC_proc.N = 0; 697 .loc 1 129 3 is_stmt 1 view .LVU202 129:Core/Src/main.c **** ADC_proc.N = 0; 698 .loc 1 129 19 is_stmt 0 view .LVU203 699 003e 8F4A ldr r2, .L35+16 700 0040 1370 strb r3, [r2] 130:Core/Src/main.c **** ADC_proc.sum_ON = 0; 701 .loc 1 130 3 is_stmt 1 view .LVU204 130:Core/Src/main.c **** ADC_proc.sum_ON = 0; 702 .loc 1 130 14 is_stmt 0 view .LVU205 703 0042 9361 str r3, [r2, #24] 131:Core/Src/main.c **** ADC_proc.avg_ON = 0; 704 .loc 1 131 3 is_stmt 1 view .LVU206 131:Core/Src/main.c **** ADC_proc.avg_ON = 0; 705 .loc 1 131 19 is_stmt 0 view .LVU207 706 0044 9360 str r3, [r2, #8] 132:Core/Src/main.c **** ADC_proc.sum_OFF = 0; 707 .loc 1 132 3 is_stmt 1 view .LVU208 132:Core/Src/main.c **** ADC_proc.sum_OFF = 0; 708 .loc 1 132 19 is_stmt 0 view .LVU209 709 0046 1361 str r3, [r2, #16] 133:Core/Src/main.c **** ADC_proc.avg_OFF = 0; 710 .loc 1 133 3 is_stmt 1 view .LVU210 133:Core/Src/main.c **** ADC_proc.avg_OFF = 0; 711 .loc 1 133 20 is_stmt 0 view .LVU211 712 0048 D360 str r3, [r2, #12] 134:Core/Src/main.c **** 713 .loc 1 134 3 is_stmt 1 view .LVU212 134:Core/Src/main.c **** 714 .loc 1 134 20 is_stmt 0 view .LVU213 715 004a 5361 str r3, [r2, #20] 136:Core/Src/main.c **** uint32_t curr_points_N =0; 716 .loc 1 136 3 is_stmt 1 view .LVU214 717 .LVL29: 137:Core/Src/main.c **** 718 .loc 1 137 3 view .LVU215 137:Core/Src/main.c **** 719 .loc 1 137 3 is_stmt 0 view .LVU216 720 004c 13E0 b .L29 ARM GAS /tmp/ccdSoXH4.s page 40 721 .L30: 198:Core/Src/main.c **** Sweep_state.sweep_cycle_started_flag = 0; // reset sweep cycle flag 722 .loc 1 198 7 is_stmt 1 view .LVU217 198:Core/Src/main.c **** Sweep_state.sweep_cycle_started_flag = 0; // reset sweep cycle flag 723 .loc 1 198 22 is_stmt 0 view .LVU218 724 004e 8C4B ldr r3, .L35+20 725 0050 1B7B ldrb r3, [r3, #12] @ zero_extendqisi2 726 0052 DBB2 uxtb r3, r3 198:Core/Src/main.c **** Sweep_state.sweep_cycle_started_flag = 0; // reset sweep cycle flag 727 .loc 1 198 10 view .LVU219 728 0054 012B cmp r3, #1 729 0056 40F00381 bne .L31 199:Core/Src/main.c **** HAL_GPIO_TogglePin(LED_RED_GPIO_Port, LED_RED_Pin); 730 .loc 1 199 9 is_stmt 1 view .LVU220 199:Core/Src/main.c **** HAL_GPIO_TogglePin(LED_RED_GPIO_Port, LED_RED_Pin); 731 .loc 1 199 46 is_stmt 0 view .LVU221 732 005a 894B ldr r3, .L35+20 733 005c 0022 movs r2, #0 734 005e 1A73 strb r2, [r3, #12] 200:Core/Src/main.c **** //CDC_Transmit_FS((uint8_t *)ADC_msg, ADC_msg_len_Sweep_start); 735 .loc 1 200 9 is_stmt 1 view .LVU222 736 0060 4FF48041 mov r1, #16384 737 0064 8148 ldr r0, .L35 738 0066 FFF7FEFF bl HAL_GPIO_TogglePin 739 .LVL30: 202:Core/Src/main.c **** //HAL_Delay(1); 740 .loc 1 202 9 view .LVU223 741 .L32: 742 .LBB14: 204:Core/Src/main.c **** 743 .loc 1 204 9 view .LVU224 202:Core/Src/main.c **** //HAL_Delay(1); 744 .loc 1 202 77 discriminator 1 view .LVU225 202:Core/Src/main.c **** //HAL_Delay(1); 745 .loc 1 202 16 is_stmt 0 discriminator 1 view .LVU226 746 006a 2521 movs r1, #37 747 006c 8548 ldr r0, .L35+24 748 006e FFF7FEFF bl CDC_Transmit_FS 749 .LVL31: 202:Core/Src/main.c **** //HAL_Delay(1); 750 .loc 1 202 77 discriminator 1 view .LVU227 751 0072 0128 cmp r0, #1 752 0074 F9D0 beq .L32 753 .L29: 754 .LBE14: 143:Core/Src/main.c **** { 755 .loc 1 143 3 is_stmt 1 view .LVU228 148:Core/Src/main.c **** // ADC_proc_shadow.avg_ON = ADC_proc_shadow.sum_ON / ADC_proc_shadow.N; 756 .loc 1 148 5 view .LVU229 148:Core/Src/main.c **** // ADC_proc_shadow.avg_ON = ADC_proc_shadow.sum_ON / ADC_proc_shadow.N; 757 .loc 1 148 24 is_stmt 0 view .LVU230 758 0076 804B ldr r3, .L35+12 759 0078 1B78 ldrb r3, [r3] @ zero_extendqisi2 760 007a DBB2 uxtb r3, r3 148:Core/Src/main.c **** // ADC_proc_shadow.avg_ON = ADC_proc_shadow.sum_ON / ADC_proc_shadow.N; 761 .loc 1 148 8 view .LVU231 762 007c 022B cmp r3, #2 ARM GAS /tmp/ccdSoXH4.s page 41 763 007e FAD1 bne .L29 150:Core/Src/main.c **** ADC_proc_shadow.avg_ON = ADC_proc_shadow.sum_ON / ADC_proc_shadow.N; 764 .loc 1 150 7 is_stmt 1 view .LVU232 150:Core/Src/main.c **** ADC_proc_shadow.avg_ON = ADC_proc_shadow.sum_ON / ADC_proc_shadow.N; 765 .loc 1 150 48 is_stmt 0 view .LVU233 766 0080 7D4A ldr r2, .L35+12 767 0082 D368 ldr r3, [r2, #12] 150:Core/Src/main.c **** ADC_proc_shadow.avg_ON = ADC_proc_shadow.sum_ON / ADC_proc_shadow.N; 768 .loc 1 150 74 view .LVU234 769 0084 9169 ldr r1, [r2, #24] 150:Core/Src/main.c **** ADC_proc_shadow.avg_ON = ADC_proc_shadow.sum_ON / ADC_proc_shadow.N; 770 .loc 1 150 57 view .LVU235 771 0086 B3FBF1F3 udiv r3, r3, r1 150:Core/Src/main.c **** ADC_proc_shadow.avg_ON = ADC_proc_shadow.sum_ON / ADC_proc_shadow.N; 772 .loc 1 150 31 view .LVU236 773 008a 5361 str r3, [r2, #20] 151:Core/Src/main.c **** ADC_proc_shadow.avg_ON = ADC_proc_shadow.avg_OFF; 774 .loc 1 151 7 is_stmt 1 view .LVU237 151:Core/Src/main.c **** ADC_proc_shadow.avg_ON = ADC_proc_shadow.avg_OFF; 775 .loc 1 151 47 is_stmt 0 view .LVU238 776 008c 9368 ldr r3, [r2, #8] 151:Core/Src/main.c **** ADC_proc_shadow.avg_ON = ADC_proc_shadow.avg_OFF; 777 .loc 1 151 72 view .LVU239 778 008e 9169 ldr r1, [r2, #24] 151:Core/Src/main.c **** ADC_proc_shadow.avg_ON = ADC_proc_shadow.avg_OFF; 779 .loc 1 151 55 view .LVU240 780 0090 B3FBF1F3 udiv r3, r3, r1 151:Core/Src/main.c **** ADC_proc_shadow.avg_ON = ADC_proc_shadow.avg_OFF; 781 .loc 1 151 30 view .LVU241 782 0094 1361 str r3, [r2, #16] 152:Core/Src/main.c **** // ADC_proc_shadow.avg_ON = ADC_proc_shadow.avg_ON - ADC_proc_shadow.avg_OFF; 783 .loc 1 152 7 is_stmt 1 view .LVU242 152:Core/Src/main.c **** // ADC_proc_shadow.avg_ON = ADC_proc_shadow.avg_ON - ADC_proc_shadow.avg_OFF; 784 .loc 1 152 47 is_stmt 0 view .LVU243 785 0096 5369 ldr r3, [r2, #20] 152:Core/Src/main.c **** // ADC_proc_shadow.avg_ON = ADC_proc_shadow.avg_ON - ADC_proc_shadow.avg_OFF; 786 .loc 1 152 30 view .LVU244 787 0098 1361 str r3, [r2, #16] 154:Core/Src/main.c **** ADC_proc_shadow.sum = 0; 788 .loc 1 154 7 is_stmt 1 view .LVU245 154:Core/Src/main.c **** ADC_proc_shadow.sum = 0; 789 .loc 1 154 30 is_stmt 0 view .LVU246 790 009a 0123 movs r3, #1 791 009c 1370 strb r3, [r2] 155:Core/Src/main.c **** ADC_proc_shadow.N = 0; 792 .loc 1 155 7 is_stmt 1 view .LVU247 155:Core/Src/main.c **** ADC_proc_shadow.N = 0; 793 .loc 1 155 27 is_stmt 0 view .LVU248 794 009e 0023 movs r3, #0 795 00a0 5360 str r3, [r2, #4] 156:Core/Src/main.c **** 796 .loc 1 156 7 is_stmt 1 view .LVU249 156:Core/Src/main.c **** 797 .loc 1 156 25 is_stmt 0 view .LVU250 798 00a2 9361 str r3, [r2, #24] 159:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 1] = (ADC_proc_shadow.avg_ON / 100000000) % 10 + '0'; 799 .loc 1 159 7 is_stmt 1 view .LVU251 ARM GAS /tmp/ccdSoXH4.s page 42 159:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 1] = (ADC_proc_shadow.avg_ON / 100000000) % 10 + '0'; 800 .loc 1 159 57 is_stmt 0 view .LVU252 801 00a4 1069 ldr r0, [r2, #16] 159:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 1] = (ADC_proc_shadow.avg_ON / 100000000) % 10 + '0'; 802 .loc 1 159 65 view .LVU253 803 00a6 400A lsrs r0, r0, #9 804 00a8 774B ldr r3, .L35+28 805 00aa A3FB0030 umull r3, r0, r3, r0 159:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 1] = (ADC_proc_shadow.avg_ON / 100000000) % 10 + '0'; 806 .loc 1 159 79 view .LVU254 807 00ae 774B ldr r3, .L35+32 808 00b0 C009 lsrs r0, r0, #7 159:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 1] = (ADC_proc_shadow.avg_ON / 100000000) % 10 + '0'; 809 .loc 1 159 84 view .LVU255 810 00b2 3030 adds r0, r0, #48 159:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 1] = (ADC_proc_shadow.avg_ON / 100000000) % 10 + '0'; 811 .loc 1 159 39 view .LVU256 812 00b4 7349 ldr r1, .L35+24 813 00b6 0873 strb r0, [r1, #12] 160:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 2] = (ADC_proc_shadow.avg_ON / 10000000) % 10 + '0'; 814 .loc 1 160 7 is_stmt 1 view .LVU257 160:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 2] = (ADC_proc_shadow.avg_ON / 10000000) % 10 + '0'; 815 .loc 1 160 57 is_stmt 0 view .LVU258 816 00b8 1469 ldr r4, [r2, #16] 160:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 2] = (ADC_proc_shadow.avg_ON / 10000000) % 10 + '0'; 817 .loc 1 160 65 view .LVU259 818 00ba 7548 ldr r0, .L35+36 819 00bc A0FB0404 umull r0, r4, r0, r4 820 00c0 640E lsrs r4, r4, #25 160:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 2] = (ADC_proc_shadow.avg_ON / 10000000) % 10 + '0'; 821 .loc 1 160 78 view .LVU260 822 00c2 A3FB0450 umull r5, r0, r3, r4 823 00c6 C008 lsrs r0, r0, #3 824 00c8 00EB8000 add r0, r0, r0, lsl #2 825 00cc A4EB4000 sub r0, r4, r0, lsl #1 160:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 2] = (ADC_proc_shadow.avg_ON / 10000000) % 10 + '0'; 826 .loc 1 160 83 view .LVU261 827 00d0 3030 adds r0, r0, #48 160:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 2] = (ADC_proc_shadow.avg_ON / 10000000) % 10 + '0'; 828 .loc 1 160 39 view .LVU262 829 00d2 4873 strb r0, [r1, #13] 161:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 3] = (ADC_proc_shadow.avg_ON / 1000000) % 10 + '0'; 830 .loc 1 161 7 is_stmt 1 view .LVU263 161:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 3] = (ADC_proc_shadow.avg_ON / 1000000) % 10 + '0'; 831 .loc 1 161 57 is_stmt 0 view .LVU264 832 00d4 1469 ldr r4, [r2, #16] 161:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 3] = (ADC_proc_shadow.avg_ON / 1000000) % 10 + '0'; 833 .loc 1 161 65 view .LVU265 834 00d6 6F48 ldr r0, .L35+40 835 00d8 A0FB0404 umull r0, r4, r0, r4 836 00dc A40D lsrs r4, r4, #22 161:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 3] = (ADC_proc_shadow.avg_ON / 1000000) % 10 + '0'; 837 .loc 1 161 77 view .LVU266 838 00de A3FB0450 umull r5, r0, r3, r4 839 00e2 C008 lsrs r0, r0, #3 840 00e4 00EB8000 add r0, r0, r0, lsl #2 841 00e8 A4EB4000 sub r0, r4, r0, lsl #1 ARM GAS /tmp/ccdSoXH4.s page 43 161:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 3] = (ADC_proc_shadow.avg_ON / 1000000) % 10 + '0'; 842 .loc 1 161 82 view .LVU267 843 00ec 3030 adds r0, r0, #48 161:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 3] = (ADC_proc_shadow.avg_ON / 1000000) % 10 + '0'; 844 .loc 1 161 39 view .LVU268 845 00ee 8873 strb r0, [r1, #14] 162:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 4] = (ADC_proc_shadow.avg_ON / 100000) % 10 + '0'; 846 .loc 1 162 7 is_stmt 1 view .LVU269 162:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 4] = (ADC_proc_shadow.avg_ON / 100000) % 10 + '0'; 847 .loc 1 162 57 is_stmt 0 view .LVU270 848 00f0 1469 ldr r4, [r2, #16] 162:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 4] = (ADC_proc_shadow.avg_ON / 100000) % 10 + '0'; 849 .loc 1 162 65 view .LVU271 850 00f2 6948 ldr r0, .L35+44 851 00f4 A0FB0404 umull r0, r4, r0, r4 852 00f8 A40C lsrs r4, r4, #18 162:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 4] = (ADC_proc_shadow.avg_ON / 100000) % 10 + '0'; 853 .loc 1 162 76 view .LVU272 854 00fa A3FB0450 umull r5, r0, r3, r4 855 00fe C008 lsrs r0, r0, #3 856 0100 00EB8000 add r0, r0, r0, lsl #2 857 0104 A4EB4000 sub r0, r4, r0, lsl #1 162:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 4] = (ADC_proc_shadow.avg_ON / 100000) % 10 + '0'; 858 .loc 1 162 81 view .LVU273 859 0108 3030 adds r0, r0, #48 162:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 4] = (ADC_proc_shadow.avg_ON / 100000) % 10 + '0'; 860 .loc 1 162 39 view .LVU274 861 010a C873 strb r0, [r1, #15] 163:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 5] = (ADC_proc_shadow.avg_ON / 10000) % 10 + '0'; 862 .loc 1 163 7 is_stmt 1 view .LVU275 163:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 5] = (ADC_proc_shadow.avg_ON / 10000) % 10 + '0'; 863 .loc 1 163 57 is_stmt 0 view .LVU276 864 010c 1469 ldr r4, [r2, #16] 163:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 5] = (ADC_proc_shadow.avg_ON / 10000) % 10 + '0'; 865 .loc 1 163 65 view .LVU277 866 010e 6409 lsrs r4, r4, #5 867 0110 624F ldr r7, .L35+48 868 0112 A7FB0404 umull r0, r4, r7, r4 869 0116 E409 lsrs r4, r4, #7 163:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 5] = (ADC_proc_shadow.avg_ON / 10000) % 10 + '0'; 870 .loc 1 163 75 view .LVU278 871 0118 A3FB0450 umull r5, r0, r3, r4 872 011c C008 lsrs r0, r0, #3 873 011e 00EB8000 add r0, r0, r0, lsl #2 874 0122 A4EB4000 sub r0, r4, r0, lsl #1 163:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 5] = (ADC_proc_shadow.avg_ON / 10000) % 10 + '0'; 875 .loc 1 163 80 view .LVU279 876 0126 3030 adds r0, r0, #48 163:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 5] = (ADC_proc_shadow.avg_ON / 10000) % 10 + '0'; 877 .loc 1 163 39 view .LVU280 878 0128 0874 strb r0, [r1, #16] 164:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 6] = (ADC_proc_shadow.avg_ON / 1000) % 10 + '0'; 879 .loc 1 164 7 is_stmt 1 view .LVU281 164:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 6] = (ADC_proc_shadow.avg_ON / 1000) % 10 + '0'; 880 .loc 1 164 57 is_stmt 0 view .LVU282 881 012a 1469 ldr r4, [r2, #16] 164:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 6] = (ADC_proc_shadow.avg_ON / 1000) % 10 + '0'; ARM GAS /tmp/ccdSoXH4.s page 44 882 .loc 1 164 65 view .LVU283 883 012c 5C4E ldr r6, .L35+52 884 012e A6FB0404 umull r0, r4, r6, r4 885 0132 640B lsrs r4, r4, #13 164:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 6] = (ADC_proc_shadow.avg_ON / 1000) % 10 + '0'; 886 .loc 1 164 74 view .LVU284 887 0134 A3FB0450 umull r5, r0, r3, r4 888 0138 C008 lsrs r0, r0, #3 889 013a 00EB8000 add r0, r0, r0, lsl #2 890 013e A4EB4000 sub r0, r4, r0, lsl #1 164:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 6] = (ADC_proc_shadow.avg_ON / 1000) % 10 + '0'; 891 .loc 1 164 79 view .LVU285 892 0142 3030 adds r0, r0, #48 164:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 6] = (ADC_proc_shadow.avg_ON / 1000) % 10 + '0'; 893 .loc 1 164 39 view .LVU286 894 0144 4874 strb r0, [r1, #17] 165:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 7] = (ADC_proc_shadow.avg_ON / 100) % 10 + '0'; 895 .loc 1 165 7 is_stmt 1 view .LVU287 165:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 7] = (ADC_proc_shadow.avg_ON / 100) % 10 + '0'; 896 .loc 1 165 57 is_stmt 0 view .LVU288 897 0146 1469 ldr r4, [r2, #16] 165:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 7] = (ADC_proc_shadow.avg_ON / 100) % 10 + '0'; 898 .loc 1 165 65 view .LVU289 899 0148 564D ldr r5, .L35+56 900 014a A5FB0404 umull r0, r4, r5, r4 901 014e A409 lsrs r4, r4, #6 165:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 7] = (ADC_proc_shadow.avg_ON / 100) % 10 + '0'; 902 .loc 1 165 73 view .LVU290 903 0150 A3FB04C0 umull ip, r0, r3, r4 904 0154 C008 lsrs r0, r0, #3 905 0156 00EB8000 add r0, r0, r0, lsl #2 906 015a A4EB4000 sub r0, r4, r0, lsl #1 165:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 7] = (ADC_proc_shadow.avg_ON / 100) % 10 + '0'; 907 .loc 1 165 78 view .LVU291 908 015e 3030 adds r0, r0, #48 165:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 7] = (ADC_proc_shadow.avg_ON / 100) % 10 + '0'; 909 .loc 1 165 39 view .LVU292 910 0160 8874 strb r0, [r1, #18] 166:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 8] = (ADC_proc_shadow.avg_ON / 10) % 10 + '0'; 911 .loc 1 166 7 is_stmt 1 view .LVU293 166:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 8] = (ADC_proc_shadow.avg_ON / 10) % 10 + '0'; 912 .loc 1 166 57 is_stmt 0 view .LVU294 913 0162 1069 ldr r0, [r2, #16] 166:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 8] = (ADC_proc_shadow.avg_ON / 10) % 10 + '0'; 914 .loc 1 166 65 view .LVU295 915 0164 504C ldr r4, .L35+60 916 0166 A4FB000C umull r0, ip, r4, r0 917 016a 4FEA5C1C lsr ip, ip, #5 166:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 8] = (ADC_proc_shadow.avg_ON / 10) % 10 + '0'; 918 .loc 1 166 72 view .LVU296 919 016e A3FB0CE0 umull lr, r0, r3, ip 920 0172 C008 lsrs r0, r0, #3 921 0174 00EB8000 add r0, r0, r0, lsl #2 922 0178 ACEB4000 sub r0, ip, r0, lsl #1 166:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 8] = (ADC_proc_shadow.avg_ON / 10) % 10 + '0'; 923 .loc 1 166 77 view .LVU297 924 017c 3030 adds r0, r0, #48 ARM GAS /tmp/ccdSoXH4.s page 45 166:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 8] = (ADC_proc_shadow.avg_ON / 10) % 10 + '0'; 925 .loc 1 166 39 view .LVU298 926 017e C874 strb r0, [r1, #19] 167:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 9] = (ADC_proc_shadow.avg_ON / 1) % 10 + '0'; 927 .loc 1 167 7 is_stmt 1 view .LVU299 167:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 9] = (ADC_proc_shadow.avg_ON / 1) % 10 + '0'; 928 .loc 1 167 57 is_stmt 0 view .LVU300 929 0180 1069 ldr r0, [r2, #16] 167:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 9] = (ADC_proc_shadow.avg_ON / 1) % 10 + '0'; 930 .loc 1 167 65 view .LVU301 931 0182 A3FB000C umull r0, ip, r3, r0 932 0186 4FEADC0C lsr ip, ip, #3 167:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 9] = (ADC_proc_shadow.avg_ON / 1) % 10 + '0'; 933 .loc 1 167 71 view .LVU302 934 018a A3FB0CE0 umull lr, r0, r3, ip 935 018e C008 lsrs r0, r0, #3 936 0190 00EB8000 add r0, r0, r0, lsl #2 937 0194 ACEB4000 sub r0, ip, r0, lsl #1 167:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 9] = (ADC_proc_shadow.avg_ON / 1) % 10 + '0'; 938 .loc 1 167 76 view .LVU303 939 0198 3030 adds r0, r0, #48 167:Core/Src/main.c **** ADC_msg[ADC_msg_val_ON_pos + 9] = (ADC_proc_shadow.avg_ON / 1) % 10 + '0'; 940 .loc 1 167 39 view .LVU304 941 019a 0875 strb r0, [r1, #20] 168:Core/Src/main.c **** 942 .loc 1 168 7 is_stmt 1 view .LVU305 168:Core/Src/main.c **** 943 .loc 1 168 57 is_stmt 0 view .LVU306 944 019c 1069 ldr r0, [r2, #16] 168:Core/Src/main.c **** 945 .loc 1 168 70 view .LVU307 946 019e A3FB00C2 umull ip, r2, r3, r0 947 01a2 D208 lsrs r2, r2, #3 948 01a4 02EB8202 add r2, r2, r2, lsl #2 949 01a8 A0EB4202 sub r2, r0, r2, lsl #1 168:Core/Src/main.c **** 950 .loc 1 168 75 view .LVU308 951 01ac 3032 adds r2, r2, #48 168:Core/Src/main.c **** 952 .loc 1 168 39 view .LVU309 953 01ae 4A75 strb r2, [r1, #21] 183:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 1] = (Sweep_state.curr_step_N / 10000) % 10 + '0'; 954 .loc 1 183 7 is_stmt 1 view .LVU310 183:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 1] = (Sweep_state.curr_step_N / 10000) % 10 + '0'; 955 .loc 1 183 51 is_stmt 0 view .LVU311 956 01b0 3348 ldr r0, .L35+20 957 01b2 0268 ldr r2, [r0] 183:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 1] = (Sweep_state.curr_step_N / 10000) % 10 + '0'; 958 .loc 1 183 64 view .LVU312 959 01b4 5209 lsrs r2, r2, #5 960 01b6 A7FB0272 umull r7, r2, r7, r2 961 01ba D709 lsrs r7, r2, #7 183:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 1] = (Sweep_state.curr_step_N / 10000) % 10 + '0'; 962 .loc 1 183 74 view .LVU313 963 01bc A3FB07C2 umull ip, r2, r3, r7 964 01c0 D208 lsrs r2, r2, #3 965 01c2 02EB8202 add r2, r2, r2, lsl #2 ARM GAS /tmp/ccdSoXH4.s page 46 966 01c6 A7EB4202 sub r2, r7, r2, lsl #1 183:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 1] = (Sweep_state.curr_step_N / 10000) % 10 + '0'; 967 .loc 1 183 79 view .LVU314 968 01ca 3032 adds r2, r2, #48 183:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 1] = (Sweep_state.curr_step_N / 10000) % 10 + '0'; 969 .loc 1 183 37 view .LVU315 970 01cc 0A71 strb r2, [r1, #4] 184:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 2] = (Sweep_state.curr_step_N / 1000) % 10 + '0'; 971 .loc 1 184 7 is_stmt 1 view .LVU316 184:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 2] = (Sweep_state.curr_step_N / 1000) % 10 + '0'; 972 .loc 1 184 51 is_stmt 0 view .LVU317 973 01ce 0268 ldr r2, [r0] 184:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 2] = (Sweep_state.curr_step_N / 1000) % 10 + '0'; 974 .loc 1 184 64 view .LVU318 975 01d0 A6FB0262 umull r6, r2, r6, r2 976 01d4 560B lsrs r6, r2, #13 184:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 2] = (Sweep_state.curr_step_N / 1000) % 10 + '0'; 977 .loc 1 184 73 view .LVU319 978 01d6 A3FB0672 umull r7, r2, r3, r6 979 01da D208 lsrs r2, r2, #3 980 01dc 02EB8202 add r2, r2, r2, lsl #2 981 01e0 A6EB4202 sub r2, r6, r2, lsl #1 184:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 2] = (Sweep_state.curr_step_N / 1000) % 10 + '0'; 982 .loc 1 184 78 view .LVU320 983 01e4 3032 adds r2, r2, #48 184:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 2] = (Sweep_state.curr_step_N / 1000) % 10 + '0'; 984 .loc 1 184 37 view .LVU321 985 01e6 4A71 strb r2, [r1, #5] 185:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 3] = (Sweep_state.curr_step_N / 100) % 10 + '0'; 986 .loc 1 185 7 is_stmt 1 view .LVU322 185:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 3] = (Sweep_state.curr_step_N / 100) % 10 + '0'; 987 .loc 1 185 51 is_stmt 0 view .LVU323 988 01e8 0268 ldr r2, [r0] 185:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 3] = (Sweep_state.curr_step_N / 100) % 10 + '0'; 989 .loc 1 185 64 view .LVU324 990 01ea A5FB0252 umull r5, r2, r5, r2 991 01ee 9509 lsrs r5, r2, #6 185:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 3] = (Sweep_state.curr_step_N / 100) % 10 + '0'; 992 .loc 1 185 72 view .LVU325 993 01f0 A3FB0562 umull r6, r2, r3, r5 994 01f4 D208 lsrs r2, r2, #3 995 01f6 02EB8202 add r2, r2, r2, lsl #2 996 01fa A5EB4202 sub r2, r5, r2, lsl #1 185:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 3] = (Sweep_state.curr_step_N / 100) % 10 + '0'; 997 .loc 1 185 77 view .LVU326 998 01fe 3032 adds r2, r2, #48 185:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 3] = (Sweep_state.curr_step_N / 100) % 10 + '0'; 999 .loc 1 185 37 view .LVU327 1000 0200 8A71 strb r2, [r1, #6] 186:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 4] = (Sweep_state.curr_step_N / 10) % 10 + '0'; 1001 .loc 1 186 7 is_stmt 1 view .LVU328 186:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 4] = (Sweep_state.curr_step_N / 10) % 10 + '0'; 1002 .loc 1 186 51 is_stmt 0 view .LVU329 1003 0202 0268 ldr r2, [r0] 186:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 4] = (Sweep_state.curr_step_N / 10) % 10 + '0'; 1004 .loc 1 186 64 view .LVU330 1005 0204 A4FB0242 umull r4, r2, r4, r2 ARM GAS /tmp/ccdSoXH4.s page 47 1006 0208 5409 lsrs r4, r2, #5 186:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 4] = (Sweep_state.curr_step_N / 10) % 10 + '0'; 1007 .loc 1 186 71 view .LVU331 1008 020a A3FB0452 umull r5, r2, r3, r4 1009 020e D208 lsrs r2, r2, #3 1010 0210 02EB8202 add r2, r2, r2, lsl #2 1011 0214 A4EB4202 sub r2, r4, r2, lsl #1 186:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 4] = (Sweep_state.curr_step_N / 10) % 10 + '0'; 1012 .loc 1 186 76 view .LVU332 1013 0218 3032 adds r2, r2, #48 186:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 4] = (Sweep_state.curr_step_N / 10) % 10 + '0'; 1014 .loc 1 186 37 view .LVU333 1015 021a CA71 strb r2, [r1, #7] 187:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 5] = (Sweep_state.curr_step_N / 1) % 10 + '0'; 1016 .loc 1 187 7 is_stmt 1 view .LVU334 187:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 5] = (Sweep_state.curr_step_N / 1) % 10 + '0'; 1017 .loc 1 187 51 is_stmt 0 view .LVU335 1018 021c 0468 ldr r4, [r0] 187:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 5] = (Sweep_state.curr_step_N / 1) % 10 + '0'; 1019 .loc 1 187 64 view .LVU336 1020 021e A3FB0424 umull r2, r4, r3, r4 1021 0222 E408 lsrs r4, r4, #3 187:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 5] = (Sweep_state.curr_step_N / 1) % 10 + '0'; 1022 .loc 1 187 70 view .LVU337 1023 0224 A3FB0452 umull r5, r2, r3, r4 1024 0228 D208 lsrs r2, r2, #3 1025 022a 02EB8202 add r2, r2, r2, lsl #2 1026 022e A4EB4202 sub r2, r4, r2, lsl #1 187:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 5] = (Sweep_state.curr_step_N / 1) % 10 + '0'; 1027 .loc 1 187 75 view .LVU338 1028 0232 3032 adds r2, r2, #48 187:Core/Src/main.c **** ADC_msg[ADC_msg_step_pos + 5] = (Sweep_state.curr_step_N / 1) % 10 + '0'; 1029 .loc 1 187 37 view .LVU339 1030 0234 0A72 strb r2, [r1, #8] 188:Core/Src/main.c **** 1031 .loc 1 188 7 is_stmt 1 view .LVU340 188:Core/Src/main.c **** 1032 .loc 1 188 51 is_stmt 0 view .LVU341 1033 0236 0268 ldr r2, [r0] 188:Core/Src/main.c **** 1034 .loc 1 188 69 view .LVU342 1035 0238 A3FB0243 umull r4, r3, r3, r2 1036 023c DB08 lsrs r3, r3, #3 1037 023e 03EB8303 add r3, r3, r3, lsl #2 1038 0242 A2EB4303 sub r3, r2, r3, lsl #1 188:Core/Src/main.c **** 1039 .loc 1 188 74 view .LVU343 1040 0246 3033 adds r3, r3, #48 188:Core/Src/main.c **** 1041 .loc 1 188 37 view .LVU344 1042 0248 4B72 strb r3, [r1, #9] 194:Core/Src/main.c **** Sweep_state.curr_step_N = 0; 1043 .loc 1 194 7 is_stmt 1 view .LVU345 194:Core/Src/main.c **** Sweep_state.curr_step_N = 0; 1044 .loc 1 194 22 is_stmt 0 view .LVU346 1045 024a 0268 ldr r2, [r0] 194:Core/Src/main.c **** Sweep_state.curr_step_N = 0; ARM GAS /tmp/ccdSoXH4.s page 48 1046 .loc 1 194 10 view .LVU347 1047 024c 42F21073 movw r3, #10000 1048 0250 9A42 cmp r2, r3 1049 0252 7FF6FCAE bls .L30 195:Core/Src/main.c **** Sweep_state.sweep_cycle_started_flag = 1; 1050 .loc 1 195 9 is_stmt 1 view .LVU348 195:Core/Src/main.c **** Sweep_state.sweep_cycle_started_flag = 1; 1051 .loc 1 195 33 is_stmt 0 view .LVU349 1052 0256 0022 movs r2, #0 1053 0258 0260 str r2, [r0] 196:Core/Src/main.c **** } 1054 .loc 1 196 9 is_stmt 1 view .LVU350 196:Core/Src/main.c **** } 1055 .loc 1 196 46 is_stmt 0 view .LVU351 1056 025a 0122 movs r2, #1 1057 025c 0273 strb r2, [r0, #12] 1058 025e F6E6 b .L30 1059 .L31: 1060 .LBB15: 207:Core/Src/main.c **** 1061 .loc 1 207 15 is_stmt 1 view .LVU352 1062 0260 1821 movs r1, #24 1063 0262 0848 ldr r0, .L35+24 1064 0264 FFF7FEFF bl CDC_Transmit_FS 1065 .LVL32: 1066 0268 05E7 b .L29 1067 .L36: 1068 026a 00BF .align 2 1069 .L35: 1070 026c 00040240 .word 1073873920 1071 0270 00000000 .word ADC1_buff_circular 1072 0274 00000000 .word hadc1 1073 0278 00000000 .word ADC_proc_shadow 1074 027c 00000000 .word ADC_proc 1075 0280 00000000 .word Sweep_state 1076 0284 00000000 .word ADC_msg 1077 0288 834B0400 .word 281475 1078 028c CDCCCCCC .word -858993459 1079 0290 893BE655 .word 1441151881 1080 0294 6BCA5F6B .word 1801439851 1081 0298 83DE1B43 .word 1125899907 1082 029c C55A7C0A .word 175921861 1083 02a0 5917B7D1 .word -776530087 1084 02a4 D34D6210 .word 274877907 1085 02a8 1F85EB51 .word 1374389535 1086 .LBE15: 1087 .cfi_endproc 1088 .LFE243: 1090 .global ADC_msg 1091 .section .data.ADC_msg,"aw" 1092 .align 2 1095 ADC_msg: 1096 0000 73747020 .ascii "stp ?????? ??????????\015\012Sweep_start\012\015\000" 1096 3F3F3F3F 1096 3F3F2020 1096 3F3F3F3F 1096 3F3F3F3F ARM GAS /tmp/ccdSoXH4.s page 49 1097 .global ADC1_buff_circular 1098 .section .bss.ADC1_buff_circular,"aw",%nobits 1099 .align 2 1102 ADC1_buff_circular: 1103 0000 00000000 .space 100 1103 00000000 1103 00000000 1103 00000000 1103 00000000 1104 .global curr_step_start_N 1105 .section .bss.curr_step_start_N,"aw",%nobits 1106 .align 2 1109 curr_step_start_N: 1110 0000 00000000 .space 4 1111 .global Sweep_state 1112 .section .bss.Sweep_state,"aw",%nobits 1113 .align 2 1116 Sweep_state: 1117 0000 00000000 .space 16 1117 00000000 1117 00000000 1117 00000000 1118 .global ADC_proc_shadow 1119 .section .bss.ADC_proc_shadow,"aw",%nobits 1120 .align 2 1123 ADC_proc_shadow: 1124 0000 00000000 .space 28 1124 00000000 1124 00000000 1124 00000000 1124 00000000 1125 .global ADC_proc 1126 .section .bss.ADC_proc,"aw",%nobits 1127 .align 2 1130 ADC_proc: 1131 0000 00000000 .space 28 1131 00000000 1131 00000000 1131 00000000 1131 00000000 1132 .global hdma_adc1 1133 .section .bss.hdma_adc1,"aw",%nobits 1134 .align 2 1137 hdma_adc1: 1138 0000 00000000 .space 96 1138 00000000 1138 00000000 1138 00000000 1138 00000000 1139 .global hadc1 1140 .section .bss.hadc1,"aw",%nobits 1141 .align 2 1144 hadc1: 1145 0000 00000000 .space 72 1145 00000000 1145 00000000 1145 00000000 ARM GAS /tmp/ccdSoXH4.s page 50 1145 00000000 1146 .text 1147 .Letext0: 1148 .file 3 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h" 1149 .file 4 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" 1150 .file 5 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" 1151 .file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h" 1152 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h" 1153 .file 8 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h" 1154 .file 9 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h" 1155 .file 10 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h" 1156 .file 11 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h" 1157 .file 12 "Core/Inc/main.h" 1158 .file 13 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h" 1159 .file 14 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h" 1160 .file 15 "USB_DEVICE/App/usb_device.h" 1161 .file 16 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h" 1162 .file 17 "" ARM GAS /tmp/ccdSoXH4.s page 51 DEFINED SYMBOLS *ABS*:00000000 main.c /tmp/ccdSoXH4.s:21 .text.MX_GPIO_Init:00000000 $t /tmp/ccdSoXH4.s:26 .text.MX_GPIO_Init:00000000 MX_GPIO_Init /tmp/ccdSoXH4.s:242 .text.MX_GPIO_Init:0000010c $d /tmp/ccdSoXH4.s:250 .text.MX_DMA_Init:00000000 $t /tmp/ccdSoXH4.s:255 .text.MX_DMA_Init:00000000 MX_DMA_Init /tmp/ccdSoXH4.s:304 .text.MX_DMA_Init:00000030 $d /tmp/ccdSoXH4.s:309 .text.Error_Handler:00000000 $t /tmp/ccdSoXH4.s:315 .text.Error_Handler:00000000 Error_Handler /tmp/ccdSoXH4.s:347 .text.MX_ADC1_Init:00000000 $t /tmp/ccdSoXH4.s:352 .text.MX_ADC1_Init:00000000 MX_ADC1_Init /tmp/ccdSoXH4.s:460 .text.MX_ADC1_Init:00000068 $d /tmp/ccdSoXH4.s:1144 .bss.hadc1:00000000 hadc1 /tmp/ccdSoXH4.s:466 .text.SystemClock_Config:00000000 $t /tmp/ccdSoXH4.s:472 .text.SystemClock_Config:00000000 SystemClock_Config /tmp/ccdSoXH4.s:620 .text.SystemClock_Config:000000a4 $d /tmp/ccdSoXH4.s:626 .text.main:00000000 $t /tmp/ccdSoXH4.s:632 .text.main:00000000 main /tmp/ccdSoXH4.s:1070 .text.main:0000026c $d /tmp/ccdSoXH4.s:1102 .bss.ADC1_buff_circular:00000000 ADC1_buff_circular /tmp/ccdSoXH4.s:1123 .bss.ADC_proc_shadow:00000000 ADC_proc_shadow /tmp/ccdSoXH4.s:1130 .bss.ADC_proc:00000000 ADC_proc /tmp/ccdSoXH4.s:1116 .bss.Sweep_state:00000000 Sweep_state /tmp/ccdSoXH4.s:1095 .data.ADC_msg:00000000 ADC_msg /tmp/ccdSoXH4.s:1092 .data.ADC_msg:00000000 $d /tmp/ccdSoXH4.s:1099 .bss.ADC1_buff_circular:00000000 $d /tmp/ccdSoXH4.s:1109 .bss.curr_step_start_N:00000000 curr_step_start_N /tmp/ccdSoXH4.s:1106 .bss.curr_step_start_N:00000000 $d /tmp/ccdSoXH4.s:1113 .bss.Sweep_state:00000000 $d /tmp/ccdSoXH4.s:1120 .bss.ADC_proc_shadow:00000000 $d /tmp/ccdSoXH4.s:1127 .bss.ADC_proc:00000000 $d /tmp/ccdSoXH4.s:1137 .bss.hdma_adc1:00000000 hdma_adc1 /tmp/ccdSoXH4.s:1134 .bss.hdma_adc1:00000000 $d /tmp/ccdSoXH4.s:1141 .bss.hadc1:00000000 $d UNDEFINED SYMBOLS HAL_GPIO_WritePin HAL_GPIO_Init HAL_NVIC_SetPriority HAL_NVIC_EnableIRQ HAL_ADC_Init HAL_ADC_ConfigChannel memset HAL_RCC_OscConfig HAL_RCC_ClockConfig HAL_Init MX_USB_DEVICE_Init HAL_ADC_Start_DMA HAL_GPIO_TogglePin CDC_Transmit_FS