ARM GAS /tmp/ccWJ27fo.s page 1 1 .cpu cortex-m4 2 .arch armv7e-m 3 .fpu fpv4-sp-d16 4 .eabi_attribute 27, 1 5 .eabi_attribute 28, 1 6 .eabi_attribute 20, 1 7 .eabi_attribute 21, 1 8 .eabi_attribute 23, 3 9 .eabi_attribute 24, 1 10 .eabi_attribute 25, 1 11 .eabi_attribute 26, 1 12 .eabi_attribute 30, 1 13 .eabi_attribute 34, 1 14 .eabi_attribute 18, 4 15 .file "main.c" 16 .text 17 .Ltext0: 18 .cfi_sections .debug_frame 19 .file 1 "Core/Src/main.c" 20 .section .text.MX_GPIO_Init,"ax",%progbits 21 .align 1 22 .syntax unified 23 .thumb 24 .thumb_func 26 MX_GPIO_Init: 27 .LFB247: 1:Core/Src/main.c **** /* USER CODE BEGIN Header */ 2:Core/Src/main.c **** /** 3:Core/Src/main.c **** ****************************************************************************** 4:Core/Src/main.c **** * @file : main.c 5:Core/Src/main.c **** * @brief : Main program body 6:Core/Src/main.c **** ****************************************************************************** 7:Core/Src/main.c **** * @attention 8:Core/Src/main.c **** * 9:Core/Src/main.c **** * Copyright (c) 2025 STMicroelectronics. 10:Core/Src/main.c **** * All rights reserved. 11:Core/Src/main.c **** * 12:Core/Src/main.c **** * This software is licensed under terms that can be found in the LICENSE file 13:Core/Src/main.c **** * in the root directory of this software component. 14:Core/Src/main.c **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Core/Src/main.c **** * 16:Core/Src/main.c **** ****************************************************************************** 17:Core/Src/main.c **** */ 18:Core/Src/main.c **** /* USER CODE END Header */ 19:Core/Src/main.c **** /* Includes ------------------------------------------------------------------*/ 20:Core/Src/main.c **** #include "main.h" 21:Core/Src/main.c **** #include "usb_device.h" 22:Core/Src/main.c **** 23:Core/Src/main.c **** /* Private includes ----------------------------------------------------------*/ 24:Core/Src/main.c **** /* USER CODE BEGIN Includes */ 25:Core/Src/main.c **** 26:Core/Src/main.c **** /* USER CODE END Includes */ 27:Core/Src/main.c **** 28:Core/Src/main.c **** /* Private typedef -----------------------------------------------------------*/ 29:Core/Src/main.c **** /* USER CODE BEGIN PTD */ 30:Core/Src/main.c **** 31:Core/Src/main.c **** /* USER CODE END PTD */ ARM GAS /tmp/ccWJ27fo.s page 2 32:Core/Src/main.c **** 33:Core/Src/main.c **** /* Private define ------------------------------------------------------------*/ 34:Core/Src/main.c **** /* USER CODE BEGIN PD */ 35:Core/Src/main.c **** 36:Core/Src/main.c **** /* USER CODE END PD */ 37:Core/Src/main.c **** 38:Core/Src/main.c **** /* Private macro -------------------------------------------------------------*/ 39:Core/Src/main.c **** /* USER CODE BEGIN PM */ 40:Core/Src/main.c **** 41:Core/Src/main.c **** /* USER CODE END PM */ 42:Core/Src/main.c **** 43:Core/Src/main.c **** /* Private variables ---------------------------------------------------------*/ 44:Core/Src/main.c **** ADC_HandleTypeDef hadc1; 45:Core/Src/main.c **** DMA_HandleTypeDef hdma_adc1; 46:Core/Src/main.c **** 47:Core/Src/main.c **** /* USER CODE BEGIN PV */ 48:Core/Src/main.c **** 49:Core/Src/main.c **** /* USER CODE END PV */ 50:Core/Src/main.c **** 51:Core/Src/main.c **** /* Private function prototypes -----------------------------------------------*/ 52:Core/Src/main.c **** void SystemClock_Config(void); 53:Core/Src/main.c **** static void MX_GPIO_Init(void); 54:Core/Src/main.c **** static void MX_DMA_Init(void); 55:Core/Src/main.c **** static void MX_ADC1_Init(void); 56:Core/Src/main.c **** /* USER CODE BEGIN PFP */ 57:Core/Src/main.c **** 58:Core/Src/main.c **** /* USER CODE END PFP */ 59:Core/Src/main.c **** 60:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/ 61:Core/Src/main.c **** /* USER CODE BEGIN 0 */ 62:Core/Src/main.c **** /* ADC_proc_shadow definition is provided here; structure is declared in main.h */ 63:Core/Src/main.c **** struct ADC_proc_typedef ADC_proc, ADC_proc_shadow; 64:Core/Src/main.c **** struct Sweep_state_typedef Sweep_state; 65:Core/Src/main.c **** 66:Core/Src/main.c **** /* ADC1 circular DMA buffer definition */ 67:Core/Src/main.c **** uint16_t ADC1_buff_circular[ADC_BUFF_SIZE]; 68:Core/Src/main.c **** char ADC_msg[] = "Received ADC value: ??????????\r\n"; 69:Core/Src/main.c **** #define ADC_msg_len 32 70:Core/Src/main.c **** #define ADC_msg_val_pos 20 71:Core/Src/main.c **** /* USER CODE END 0 */ 72:Core/Src/main.c **** 73:Core/Src/main.c **** /** 74:Core/Src/main.c **** * @brief The application entry point. 75:Core/Src/main.c **** * @retval int 76:Core/Src/main.c **** */ 77:Core/Src/main.c **** int main(void) 78:Core/Src/main.c **** { 79:Core/Src/main.c **** 80:Core/Src/main.c **** /* USER CODE BEGIN 1 */ 81:Core/Src/main.c **** 82:Core/Src/main.c **** /* USER CODE END 1 */ 83:Core/Src/main.c **** 84:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ 85:Core/Src/main.c **** 86:Core/Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 87:Core/Src/main.c **** HAL_Init(); 88:Core/Src/main.c **** ARM GAS /tmp/ccWJ27fo.s page 3 89:Core/Src/main.c **** /* USER CODE BEGIN Init */ 90:Core/Src/main.c **** 91:Core/Src/main.c **** /* USER CODE END Init */ 92:Core/Src/main.c **** 93:Core/Src/main.c **** /* Configure the system clock */ 94:Core/Src/main.c **** SystemClock_Config(); 95:Core/Src/main.c **** 96:Core/Src/main.c **** /* USER CODE BEGIN SysInit */ 97:Core/Src/main.c **** 98:Core/Src/main.c **** /* USER CODE END SysInit */ 99:Core/Src/main.c **** 100:Core/Src/main.c **** /* Initialize all configured peripherals */ 101:Core/Src/main.c **** MX_GPIO_Init(); 102:Core/Src/main.c **** MX_DMA_Init(); 103:Core/Src/main.c **** MX_ADC1_Init(); 104:Core/Src/main.c **** MX_USB_DEVICE_Init(); 105:Core/Src/main.c **** /* USER CODE BEGIN 2 */ 106:Core/Src/main.c **** HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_SET); 107:Core/Src/main.c **** HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADC1_buff_circular, ADC_BUFF_SIZE); 108:Core/Src/main.c **** 109:Core/Src/main.c **** ADC_proc_shadow.status = 0; // ADC started 110:Core/Src/main.c **** ADC_proc_shadow.N = 0; 111:Core/Src/main.c **** ADC_proc_shadow.sum = 0; 112:Core/Src/main.c **** ADC_proc_shadow.avg = 0; 113:Core/Src/main.c **** 114:Core/Src/main.c **** ADC_proc.status = 0; // ADC started 115:Core/Src/main.c **** ADC_proc.N = 0; 116:Core/Src/main.c **** ADC_proc.sum = 0; 117:Core/Src/main.c **** ADC_proc.avg = 0; 118:Core/Src/main.c **** 119:Core/Src/main.c **** /* USER CODE END 2 */ 120:Core/Src/main.c **** 121:Core/Src/main.c **** /* Infinite loop */ 122:Core/Src/main.c **** /* USER CODE BEGIN WHILE */ 123:Core/Src/main.c **** while (1) 124:Core/Src/main.c **** { 125:Core/Src/main.c **** HAL_GPIO_TogglePin(LED_RED_GPIO_Port, LED_RED_Pin); 126:Core/Src/main.c **** //HAL_Delay(100); 127:Core/Src/main.c **** 128:Core/Src/main.c **** if (ADC_proc_shadow.status == 2) { 129:Core/Src/main.c **** ADC_proc_shadow.avg = ADC_proc_shadow.sum / ADC_proc_shadow.N; 130:Core/Src/main.c **** ADC_proc_shadow.status = 1; // reset for next accumulation 131:Core/Src/main.c **** ADC_proc_shadow.sum = 0; 132:Core/Src/main.c **** ADC_proc_shadow.N = 0; 133:Core/Src/main.c **** 134:Core/Src/main.c **** 135:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 0] = (ADC_proc_shadow.avg / 10000000000) % 10 + '0'; 136:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 1] = (ADC_proc_shadow.avg / 1000000000) % 10 + '0'; 137:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 2] = (ADC_proc_shadow.avg / 10000000) % 10 + '0'; 138:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 3] = (ADC_proc_shadow.avg / 1000000) % 10 + '0'; 139:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 4] = (ADC_proc_shadow.avg / 100000) % 10 + '0'; 140:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 5] = (ADC_proc_shadow.avg / 10000) % 10 + '0'; 141:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 6] = (ADC_proc_shadow.avg / 1000) % 10 + '0'; 142:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 7] = (ADC_proc_shadow.avg / 100) % 10 + '0'; 143:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 8] = (ADC_proc_shadow.avg / 10) % 10 + '0'; 144:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 9] = (ADC_proc_shadow.avg / 1) % 10 + '0'; 145:Core/Src/main.c **** CDC_Transmit_FS((uint8_t *)ADC_msg, ADC_msg_len); ARM GAS /tmp/ccWJ27fo.s page 4 146:Core/Src/main.c **** 147:Core/Src/main.c **** } 148:Core/Src/main.c **** //CDC_Transmit_FS((uint8_t *)"Hello from STM32!\r\n", 19); 149:Core/Src/main.c **** 150:Core/Src/main.c **** /* USER CODE END WHILE */ 151:Core/Src/main.c **** 152:Core/Src/main.c **** /* USER CODE BEGIN 3 */ 153:Core/Src/main.c **** } 154:Core/Src/main.c **** /* USER CODE END 3 */ 155:Core/Src/main.c **** } 156:Core/Src/main.c **** 157:Core/Src/main.c **** /** 158:Core/Src/main.c **** * @brief System Clock Configuration 159:Core/Src/main.c **** * @retval None 160:Core/Src/main.c **** */ 161:Core/Src/main.c **** void SystemClock_Config(void) 162:Core/Src/main.c **** { 163:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 164:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 165:Core/Src/main.c **** 166:Core/Src/main.c **** /** Configure the main internal regulator output voltage 167:Core/Src/main.c **** */ 168:Core/Src/main.c **** __HAL_RCC_PWR_CLK_ENABLE(); 169:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 170:Core/Src/main.c **** 171:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters 172:Core/Src/main.c **** * in the RCC_OscInitTypeDef structure. 173:Core/Src/main.c **** */ 174:Core/Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 175:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 176:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 177:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 178:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 8; 179:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 336; 180:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 181:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 7; 182:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 183:Core/Src/main.c **** { 184:Core/Src/main.c **** Error_Handler(); 185:Core/Src/main.c **** } 186:Core/Src/main.c **** 187:Core/Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks 188:Core/Src/main.c **** */ 189:Core/Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 190:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 191:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 192:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 193:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 194:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 195:Core/Src/main.c **** 196:Core/Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) 197:Core/Src/main.c **** { 198:Core/Src/main.c **** Error_Handler(); 199:Core/Src/main.c **** } 200:Core/Src/main.c **** } 201:Core/Src/main.c **** 202:Core/Src/main.c **** /** ARM GAS /tmp/ccWJ27fo.s page 5 203:Core/Src/main.c **** * @brief ADC1 Initialization Function 204:Core/Src/main.c **** * @param None 205:Core/Src/main.c **** * @retval None 206:Core/Src/main.c **** */ 207:Core/Src/main.c **** static void MX_ADC1_Init(void) 208:Core/Src/main.c **** { 209:Core/Src/main.c **** 210:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 0 */ 211:Core/Src/main.c **** 212:Core/Src/main.c **** /* USER CODE END ADC1_Init 0 */ 213:Core/Src/main.c **** 214:Core/Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0}; 215:Core/Src/main.c **** 216:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 1 */ 217:Core/Src/main.c **** 218:Core/Src/main.c **** /* USER CODE END ADC1_Init 1 */ 219:Core/Src/main.c **** 220:Core/Src/main.c **** /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of con 221:Core/Src/main.c **** */ 222:Core/Src/main.c **** hadc1.Instance = ADC1; 223:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; 224:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; 225:Core/Src/main.c **** hadc1.Init.ScanConvMode = DISABLE; 226:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; 227:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; 228:Core/Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 229:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_Ext_IT11; 230:Core/Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 231:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1; 232:Core/Src/main.c **** hadc1.Init.DMAContinuousRequests = ENABLE; 233:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 234:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) 235:Core/Src/main.c **** { 236:Core/Src/main.c **** Error_Handler(); 237:Core/Src/main.c **** } 238:Core/Src/main.c **** 239:Core/Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 240:Core/Src/main.c **** */ 241:Core/Src/main.c **** sConfig.Channel = ADC_CHANNEL_3; 242:Core/Src/main.c **** sConfig.Rank = 1; 243:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; 244:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 245:Core/Src/main.c **** { 246:Core/Src/main.c **** Error_Handler(); 247:Core/Src/main.c **** } 248:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 2 */ 249:Core/Src/main.c **** 250:Core/Src/main.c **** /* USER CODE END ADC1_Init 2 */ 251:Core/Src/main.c **** 252:Core/Src/main.c **** } 253:Core/Src/main.c **** 254:Core/Src/main.c **** /** 255:Core/Src/main.c **** * Enable DMA controller clock 256:Core/Src/main.c **** */ 257:Core/Src/main.c **** static void MX_DMA_Init(void) 258:Core/Src/main.c **** { 259:Core/Src/main.c **** ARM GAS /tmp/ccWJ27fo.s page 6 260:Core/Src/main.c **** /* DMA controller clock enable */ 261:Core/Src/main.c **** __HAL_RCC_DMA2_CLK_ENABLE(); 262:Core/Src/main.c **** 263:Core/Src/main.c **** /* DMA interrupt init */ 264:Core/Src/main.c **** /* DMA2_Stream0_IRQn interrupt configuration */ 265:Core/Src/main.c **** HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 0, 0); 266:Core/Src/main.c **** HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); 267:Core/Src/main.c **** 268:Core/Src/main.c **** } 269:Core/Src/main.c **** 270:Core/Src/main.c **** /** 271:Core/Src/main.c **** * @brief GPIO Initialization Function 272:Core/Src/main.c **** * @param None 273:Core/Src/main.c **** * @retval None 274:Core/Src/main.c **** */ 275:Core/Src/main.c **** static void MX_GPIO_Init(void) 276:Core/Src/main.c **** { 28 .loc 1 276 1 view -0 29 .cfi_startproc 30 @ args = 0, pretend = 0, frame = 40 31 @ frame_needed = 0, uses_anonymous_args = 0 32 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} 33 .LCFI0: 34 .cfi_def_cfa_offset 28 35 .cfi_offset 4, -28 36 .cfi_offset 5, -24 37 .cfi_offset 6, -20 38 .cfi_offset 7, -16 39 .cfi_offset 8, -12 40 .cfi_offset 9, -8 41 .cfi_offset 14, -4 42 0004 8BB0 sub sp, sp, #44 43 .LCFI1: 44 .cfi_def_cfa_offset 72 277:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; 45 .loc 1 277 3 view .LVU1 46 .loc 1 277 20 is_stmt 0 view .LVU2 47 0006 0024 movs r4, #0 48 0008 0594 str r4, [sp, #20] 49 000a 0694 str r4, [sp, #24] 50 000c 0794 str r4, [sp, #28] 51 000e 0894 str r4, [sp, #32] 52 0010 0994 str r4, [sp, #36] 278:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */ 279:Core/Src/main.c **** 280:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_1 */ 281:Core/Src/main.c **** 282:Core/Src/main.c **** /* GPIO Ports Clock Enable */ 283:Core/Src/main.c **** __HAL_RCC_GPIOH_CLK_ENABLE(); 53 .loc 1 283 3 is_stmt 1 view .LVU3 54 .LBB4: 55 .loc 1 283 3 view .LVU4 56 0012 0094 str r4, [sp] 57 .loc 1 283 3 view .LVU5 58 0014 3D4B ldr r3, .L3 59 0016 1A6B ldr r2, [r3, #48] 60 0018 42F08002 orr r2, r2, #128 ARM GAS /tmp/ccWJ27fo.s page 7 61 001c 1A63 str r2, [r3, #48] 62 .loc 1 283 3 view .LVU6 63 001e 1A6B ldr r2, [r3, #48] 64 0020 02F08002 and r2, r2, #128 65 0024 0092 str r2, [sp] 66 .loc 1 283 3 view .LVU7 67 0026 009A ldr r2, [sp] 68 .LBE4: 69 .loc 1 283 3 view .LVU8 284:Core/Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); 70 .loc 1 284 3 view .LVU9 71 .LBB5: 72 .loc 1 284 3 view .LVU10 73 0028 0194 str r4, [sp, #4] 74 .loc 1 284 3 view .LVU11 75 002a 1A6B ldr r2, [r3, #48] 76 002c 42F00402 orr r2, r2, #4 77 0030 1A63 str r2, [r3, #48] 78 .loc 1 284 3 view .LVU12 79 0032 1A6B ldr r2, [r3, #48] 80 0034 02F00402 and r2, r2, #4 81 0038 0192 str r2, [sp, #4] 82 .loc 1 284 3 view .LVU13 83 003a 019A ldr r2, [sp, #4] 84 .LBE5: 85 .loc 1 284 3 view .LVU14 285:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); 86 .loc 1 285 3 view .LVU15 87 .LBB6: 88 .loc 1 285 3 view .LVU16 89 003c 0294 str r4, [sp, #8] 90 .loc 1 285 3 view .LVU17 91 003e 1A6B ldr r2, [r3, #48] 92 0040 42F00102 orr r2, r2, #1 93 0044 1A63 str r2, [r3, #48] 94 .loc 1 285 3 view .LVU18 95 0046 1A6B ldr r2, [r3, #48] 96 0048 02F00102 and r2, r2, #1 97 004c 0292 str r2, [sp, #8] 98 .loc 1 285 3 view .LVU19 99 004e 029A ldr r2, [sp, #8] 100 .LBE6: 101 .loc 1 285 3 view .LVU20 286:Core/Src/main.c **** __HAL_RCC_GPIOF_CLK_ENABLE(); 102 .loc 1 286 3 view .LVU21 103 .LBB7: 104 .loc 1 286 3 view .LVU22 105 0050 0394 str r4, [sp, #12] 106 .loc 1 286 3 view .LVU23 107 0052 1A6B ldr r2, [r3, #48] 108 0054 42F02002 orr r2, r2, #32 109 0058 1A63 str r2, [r3, #48] 110 .loc 1 286 3 view .LVU24 111 005a 1A6B ldr r2, [r3, #48] 112 005c 02F02002 and r2, r2, #32 113 0060 0392 str r2, [sp, #12] 114 .loc 1 286 3 view .LVU25 ARM GAS /tmp/ccWJ27fo.s page 8 115 0062 039A ldr r2, [sp, #12] 116 .LBE7: 117 .loc 1 286 3 view .LVU26 287:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); 118 .loc 1 287 3 view .LVU27 119 .LBB8: 120 .loc 1 287 3 view .LVU28 121 0064 0494 str r4, [sp, #16] 122 .loc 1 287 3 view .LVU29 123 0066 1A6B ldr r2, [r3, #48] 124 0068 42F00202 orr r2, r2, #2 125 006c 1A63 str r2, [r3, #48] 126 .loc 1 287 3 view .LVU30 127 006e 1B6B ldr r3, [r3, #48] 128 0070 03F00203 and r3, r3, #2 129 0074 0493 str r3, [sp, #16] 130 .loc 1 287 3 view .LVU31 131 0076 049B ldr r3, [sp, #16] 132 .LBE8: 133 .loc 1 287 3 view .LVU32 288:Core/Src/main.c **** 289:Core/Src/main.c **** /*Configure GPIO pin Output Level */ 290:Core/Src/main.c **** HAL_GPIO_WritePin(LED_RED_GPIO_Port, LED_RED_Pin, GPIO_PIN_RESET); 134 .loc 1 290 3 view .LVU33 135 0078 254D ldr r5, .L3+4 136 007a 2246 mov r2, r4 137 007c 4FF48041 mov r1, #16384 138 0080 2846 mov r0, r5 139 0082 FFF7FEFF bl HAL_GPIO_WritePin 140 .LVL0: 291:Core/Src/main.c **** 292:Core/Src/main.c **** /*Configure GPIO pin Output Level */ 293:Core/Src/main.c **** HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_SET); 141 .loc 1 293 3 view .LVU34 142 0086 0122 movs r2, #1 143 0088 8021 movs r1, #128 144 008a 2846 mov r0, r5 145 008c FFF7FEFF bl HAL_GPIO_WritePin 146 .LVL1: 294:Core/Src/main.c **** 295:Core/Src/main.c **** /*Configure GPIO pin : CURR_STEP_START_TRG_Pin */ 296:Core/Src/main.c **** GPIO_InitStruct.Pin = CURR_STEP_START_TRG_Pin; 147 .loc 1 296 3 view .LVU35 148 .loc 1 296 23 is_stmt 0 view .LVU36 149 0090 0127 movs r7, #1 150 0092 0597 str r7, [sp, #20] 297:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; 151 .loc 1 297 3 is_stmt 1 view .LVU37 152 .loc 1 297 24 is_stmt 0 view .LVU38 153 0094 4FF44413 mov r3, #3211264 154 0098 0693 str r3, [sp, #24] 298:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_PULLDOWN; 155 .loc 1 298 3 is_stmt 1 view .LVU39 156 .loc 1 298 24 is_stmt 0 view .LVU40 157 009a 0226 movs r6, #2 158 009c 0796 str r6, [sp, #28] 299:Core/Src/main.c **** HAL_GPIO_Init(CURR_STEP_START_TRG_GPIO_Port, &GPIO_InitStruct); ARM GAS /tmp/ccWJ27fo.s page 9 159 .loc 1 299 3 is_stmt 1 view .LVU41 160 009e DFF87890 ldr r9, .L3+12 161 00a2 05A9 add r1, sp, #20 162 00a4 4846 mov r0, r9 163 00a6 FFF7FEFF bl HAL_GPIO_Init 164 .LVL2: 300:Core/Src/main.c **** 301:Core/Src/main.c **** /*Configure GPIO pin : SWEEP_CYCLE_START_TRG_Pin */ 302:Core/Src/main.c **** GPIO_InitStruct.Pin = SWEEP_CYCLE_START_TRG_Pin; 165 .loc 1 302 3 view .LVU42 166 .loc 1 302 23 is_stmt 0 view .LVU43 167 00aa 0596 str r6, [sp, #20] 303:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 168 .loc 1 303 3 is_stmt 1 view .LVU44 169 .loc 1 303 24 is_stmt 0 view .LVU45 170 00ac 4FF48818 mov r8, #1114112 171 00b0 CDF81880 str r8, [sp, #24] 304:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_PULLDOWN; 172 .loc 1 304 3 is_stmt 1 view .LVU46 173 .loc 1 304 24 is_stmt 0 view .LVU47 174 00b4 0796 str r6, [sp, #28] 305:Core/Src/main.c **** HAL_GPIO_Init(SWEEP_CYCLE_START_TRG_GPIO_Port, &GPIO_InitStruct); 175 .loc 1 305 3 is_stmt 1 view .LVU48 176 00b6 05A9 add r1, sp, #20 177 00b8 4846 mov r0, r9 178 00ba FFF7FEFF bl HAL_GPIO_Init 179 .LVL3: 306:Core/Src/main.c **** 307:Core/Src/main.c **** /*Configure GPIO pin : PF11 */ 308:Core/Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_11; 180 .loc 1 308 3 view .LVU49 181 .loc 1 308 23 is_stmt 0 view .LVU50 182 00be 4FF40063 mov r3, #2048 183 00c2 0593 str r3, [sp, #20] 309:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 184 .loc 1 309 3 is_stmt 1 view .LVU51 185 .loc 1 309 24 is_stmt 0 view .LVU52 186 00c4 CDF81880 str r8, [sp, #24] 310:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 187 .loc 1 310 3 is_stmt 1 view .LVU53 188 .loc 1 310 24 is_stmt 0 view .LVU54 189 00c8 0794 str r4, [sp, #28] 311:Core/Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 190 .loc 1 311 3 is_stmt 1 view .LVU55 191 00ca 05A9 add r1, sp, #20 192 00cc 1148 ldr r0, .L3+8 193 00ce FFF7FEFF bl HAL_GPIO_Init 194 .LVL4: 312:Core/Src/main.c **** 313:Core/Src/main.c **** /*Configure GPIO pins : LED_RED_Pin LED_BLUE_Pin */ 314:Core/Src/main.c **** GPIO_InitStruct.Pin = LED_RED_Pin|LED_BLUE_Pin; 195 .loc 1 314 3 view .LVU56 196 .loc 1 314 23 is_stmt 0 view .LVU57 197 00d2 4FF48143 mov r3, #16512 198 00d6 0593 str r3, [sp, #20] 315:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 199 .loc 1 315 3 is_stmt 1 view .LVU58 ARM GAS /tmp/ccWJ27fo.s page 10 200 .loc 1 315 24 is_stmt 0 view .LVU59 201 00d8 0697 str r7, [sp, #24] 316:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 202 .loc 1 316 3 is_stmt 1 view .LVU60 203 .loc 1 316 24 is_stmt 0 view .LVU61 204 00da 0794 str r4, [sp, #28] 317:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 205 .loc 1 317 3 is_stmt 1 view .LVU62 206 .loc 1 317 25 is_stmt 0 view .LVU63 207 00dc 0894 str r4, [sp, #32] 318:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 208 .loc 1 318 3 is_stmt 1 view .LVU64 209 00de 05A9 add r1, sp, #20 210 00e0 2846 mov r0, r5 211 00e2 FFF7FEFF bl HAL_GPIO_Init 212 .LVL5: 319:Core/Src/main.c **** 320:Core/Src/main.c **** /* EXTI interrupt init*/ 321:Core/Src/main.c **** HAL_NVIC_SetPriority(EXTI0_IRQn, 0, 0); 213 .loc 1 321 3 view .LVU65 214 00e6 2246 mov r2, r4 215 00e8 2146 mov r1, r4 216 00ea 0620 movs r0, #6 217 00ec FFF7FEFF bl HAL_NVIC_SetPriority 218 .LVL6: 322:Core/Src/main.c **** HAL_NVIC_EnableIRQ(EXTI0_IRQn); 219 .loc 1 322 3 view .LVU66 220 00f0 0620 movs r0, #6 221 00f2 FFF7FEFF bl HAL_NVIC_EnableIRQ 222 .LVL7: 323:Core/Src/main.c **** 324:Core/Src/main.c **** HAL_NVIC_SetPriority(EXTI3_IRQn, 0, 0); 223 .loc 1 324 3 view .LVU67 224 00f6 2246 mov r2, r4 225 00f8 2146 mov r1, r4 226 00fa 0920 movs r0, #9 227 00fc FFF7FEFF bl HAL_NVIC_SetPriority 228 .LVL8: 325:Core/Src/main.c **** HAL_NVIC_EnableIRQ(EXTI3_IRQn); 229 .loc 1 325 3 view .LVU68 230 0100 0920 movs r0, #9 231 0102 FFF7FEFF bl HAL_NVIC_EnableIRQ 232 .LVL9: 326:Core/Src/main.c **** 327:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_2 */ 328:Core/Src/main.c **** 329:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_2 */ 330:Core/Src/main.c **** } 233 .loc 1 330 1 is_stmt 0 view .LVU69 234 0106 0BB0 add sp, sp, #44 235 .LCFI2: 236 .cfi_def_cfa_offset 28 237 @ sp needed 238 0108 BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} 239 .L4: 240 .align 2 241 .L3: ARM GAS /tmp/ccWJ27fo.s page 11 242 010c 00380240 .word 1073887232 243 0110 00040240 .word 1073873920 244 0114 00140240 .word 1073878016 245 0118 00080240 .word 1073874944 246 .cfi_endproc 247 .LFE247: 249 .section .text.MX_DMA_Init,"ax",%progbits 250 .align 1 251 .syntax unified 252 .thumb 253 .thumb_func 255 MX_DMA_Init: 256 .LFB246: 258:Core/Src/main.c **** 257 .loc 1 258 1 is_stmt 1 view -0 258 .cfi_startproc 259 @ args = 0, pretend = 0, frame = 8 260 @ frame_needed = 0, uses_anonymous_args = 0 261 0000 00B5 push {lr} 262 .LCFI3: 263 .cfi_def_cfa_offset 4 264 .cfi_offset 14, -4 265 0002 83B0 sub sp, sp, #12 266 .LCFI4: 267 .cfi_def_cfa_offset 16 261:Core/Src/main.c **** 268 .loc 1 261 3 view .LVU71 269 .LBB9: 261:Core/Src/main.c **** 270 .loc 1 261 3 view .LVU72 271 0004 0021 movs r1, #0 272 0006 0191 str r1, [sp, #4] 261:Core/Src/main.c **** 273 .loc 1 261 3 view .LVU73 274 0008 094B ldr r3, .L7 275 000a 1A6B ldr r2, [r3, #48] 276 000c 42F48002 orr r2, r2, #4194304 277 0010 1A63 str r2, [r3, #48] 261:Core/Src/main.c **** 278 .loc 1 261 3 view .LVU74 279 0012 1B6B ldr r3, [r3, #48] 280 0014 03F48003 and r3, r3, #4194304 281 0018 0193 str r3, [sp, #4] 261:Core/Src/main.c **** 282 .loc 1 261 3 view .LVU75 283 001a 019B ldr r3, [sp, #4] 284 .LBE9: 261:Core/Src/main.c **** 285 .loc 1 261 3 view .LVU76 265:Core/Src/main.c **** HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); 286 .loc 1 265 3 view .LVU77 287 001c 0A46 mov r2, r1 288 001e 3820 movs r0, #56 289 0020 FFF7FEFF bl HAL_NVIC_SetPriority 290 .LVL10: 266:Core/Src/main.c **** 291 .loc 1 266 3 view .LVU78 ARM GAS /tmp/ccWJ27fo.s page 12 292 0024 3820 movs r0, #56 293 0026 FFF7FEFF bl HAL_NVIC_EnableIRQ 294 .LVL11: 268:Core/Src/main.c **** 295 .loc 1 268 1 is_stmt 0 view .LVU79 296 002a 03B0 add sp, sp, #12 297 .LCFI5: 298 .cfi_def_cfa_offset 4 299 @ sp needed 300 002c 5DF804FB ldr pc, [sp], #4 301 .L8: 302 .align 2 303 .L7: 304 0030 00380240 .word 1073887232 305 .cfi_endproc 306 .LFE246: 308 .section .text.Error_Handler,"ax",%progbits 309 .align 1 310 .global Error_Handler 311 .syntax unified 312 .thumb 313 .thumb_func 315 Error_Handler: 316 .LFB248: 331:Core/Src/main.c **** 332:Core/Src/main.c **** /* USER CODE BEGIN 4 */ 333:Core/Src/main.c **** 334:Core/Src/main.c **** /* USER CODE END 4 */ 335:Core/Src/main.c **** 336:Core/Src/main.c **** /** 337:Core/Src/main.c **** * @brief This function is executed in case of error occurrence. 338:Core/Src/main.c **** * @retval None 339:Core/Src/main.c **** */ 340:Core/Src/main.c **** void Error_Handler(void) 341:Core/Src/main.c **** { 317 .loc 1 341 1 is_stmt 1 view -0 318 .cfi_startproc 319 @ Volatile: function does not return. 320 @ args = 0, pretend = 0, frame = 0 321 @ frame_needed = 0, uses_anonymous_args = 0 322 @ link register save eliminated. 342:Core/Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */ 343:Core/Src/main.c **** /* User can add his own implementation to report the HAL error return state */ 344:Core/Src/main.c **** __disable_irq(); 323 .loc 1 344 3 view .LVU81 324 .LBB10: 325 .LBI10: 326 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.4.1 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 27. May 2021 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2021 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * ARM GAS /tmp/ccWJ27fo.s page 13 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 24:Drivers/CMSIS/Include/cmsis_gcc.h **** 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H 27:Drivers/CMSIS/Include/cmsis_gcc.h **** 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" 33:Drivers/CMSIS/Include/cmsis_gcc.h **** 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 38:Drivers/CMSIS/Include/cmsis_gcc.h **** 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif ARM GAS /tmp/ccWJ27fo.s page 14 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __COMPILER_BARRIER 117:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __COMPILER_BARRIER() __ASM volatile("":::"memory") 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 119:Drivers/CMSIS/Include/cmsis_gcc.h **** 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ######################### Startup and Lowlevel Init ######################## */ 121:Drivers/CMSIS/Include/cmsis_gcc.h **** 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START 123:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccWJ27fo.s page 15 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Initializes data and bss sections 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details This default implementations initialized all data and additional bss 127:Drivers/CMSIS/Include/cmsis_gcc.h **** sections relying on .copy.table and .zero.table specified properly 128:Drivers/CMSIS/Include/cmsis_gcc.h **** in the used linker script. 129:Drivers/CMSIS/Include/cmsis_gcc.h **** 130:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) 132:Drivers/CMSIS/Include/cmsis_gcc.h **** { 133:Drivers/CMSIS/Include/cmsis_gcc.h **** extern void _start(void) __NO_RETURN; 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 135:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct { 136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t const* src; 137:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest; 138:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen; 139:Drivers/CMSIS/Include/cmsis_gcc.h **** } __copy_table_t; 140:Drivers/CMSIS/Include/cmsis_gcc.h **** 141:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct { 142:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest; 143:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen; 144:Drivers/CMSIS/Include/cmsis_gcc.h **** } __zero_table_t; 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 146:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_start__; 147:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_end__; 148:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_start__; 149:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_end__; 150:Drivers/CMSIS/Include/cmsis_gcc.h **** 151:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable 152:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; iwlen; ++i) { 153:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = pTable->src[i]; 154:Drivers/CMSIS/Include/cmsis_gcc.h **** } 155:Drivers/CMSIS/Include/cmsis_gcc.h **** } 156:Drivers/CMSIS/Include/cmsis_gcc.h **** 157:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable 158:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; iwlen; ++i) { 159:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = 0u; 160:Drivers/CMSIS/Include/cmsis_gcc.h **** } 161:Drivers/CMSIS/Include/cmsis_gcc.h **** } 162:Drivers/CMSIS/Include/cmsis_gcc.h **** 163:Drivers/CMSIS/Include/cmsis_gcc.h **** _start(); 164:Drivers/CMSIS/Include/cmsis_gcc.h **** } 165:Drivers/CMSIS/Include/cmsis_gcc.h **** 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START __cmsis_start 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 168:Drivers/CMSIS/Include/cmsis_gcc.h **** 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP __StackTop 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 172:Drivers/CMSIS/Include/cmsis_gcc.h **** 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT __StackLimit 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 176:Drivers/CMSIS/Include/cmsis_gcc.h **** 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE __Vectors 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 180:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccWJ27fo.s page 16 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 184:Drivers/CMSIS/Include/cmsis_gcc.h **** 185:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 186:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_SEAL 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_SEAL __StackSeal 188:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 189:Drivers/CMSIS/Include/cmsis_gcc.h **** 190:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_SIZE 191:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __TZ_STACK_SEAL_SIZE 8U 192:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 193:Drivers/CMSIS/Include/cmsis_gcc.h **** 194:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_VALUE 195:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL 196:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 197:Drivers/CMSIS/Include/cmsis_gcc.h **** 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 199:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { 200:Drivers/CMSIS/Include/cmsis_gcc.h **** *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; 201:Drivers/CMSIS/Include/cmsis_gcc.h **** } 202:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 203:Drivers/CMSIS/Include/cmsis_gcc.h **** 204:Drivers/CMSIS/Include/cmsis_gcc.h **** 205:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ 206:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 207:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions 208:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 209:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 210:Drivers/CMSIS/Include/cmsis_gcc.h **** 211:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. 212:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" 213:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ 214:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) 215:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) 216:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) 217:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) 218:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 219:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) 220:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) 221:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) 222:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 223:Drivers/CMSIS/Include/cmsis_gcc.h **** 224:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 225:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation 226:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. 227:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 228:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") 229:Drivers/CMSIS/Include/cmsis_gcc.h **** 230:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt 232:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o 233:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 234:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi":::"memory") 235:Drivers/CMSIS/Include/cmsis_gcc.h **** 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 237:Drivers/CMSIS/Include/cmsis_gcc.h **** /** ARM GAS /tmp/ccWJ27fo.s page 17 238:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event 239:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter 240:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. 241:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 242:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe":::"memory") 243:Drivers/CMSIS/Include/cmsis_gcc.h **** 244:Drivers/CMSIS/Include/cmsis_gcc.h **** 245:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 246:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event 247:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. 248:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 249:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 251:Drivers/CMSIS/Include/cmsis_gcc.h **** 252:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 253:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier 254:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, 255:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, 256:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. 257:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 258:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) 259:Drivers/CMSIS/Include/cmsis_gcc.h **** { 260:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); 261:Drivers/CMSIS/Include/cmsis_gcc.h **** } 262:Drivers/CMSIS/Include/cmsis_gcc.h **** 263:Drivers/CMSIS/Include/cmsis_gcc.h **** 264:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 265:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier 266:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. 267:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. 268:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 269:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) 270:Drivers/CMSIS/Include/cmsis_gcc.h **** { 271:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); 272:Drivers/CMSIS/Include/cmsis_gcc.h **** } 273:Drivers/CMSIS/Include/cmsis_gcc.h **** 274:Drivers/CMSIS/Include/cmsis_gcc.h **** 275:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 276:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier 277:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before 278:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. 279:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 280:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) 281:Drivers/CMSIS/Include/cmsis_gcc.h **** { 282:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); 283:Drivers/CMSIS/Include/cmsis_gcc.h **** } 284:Drivers/CMSIS/Include/cmsis_gcc.h **** 285:Drivers/CMSIS/Include/cmsis_gcc.h **** 286:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) 288:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 289:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 290:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 291:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 292:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) 293:Drivers/CMSIS/Include/cmsis_gcc.h **** { 294:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) ARM GAS /tmp/ccWJ27fo.s page 18 295:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); 296:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 297:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 298:Drivers/CMSIS/Include/cmsis_gcc.h **** 299:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 300:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 301:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 302:Drivers/CMSIS/Include/cmsis_gcc.h **** } 303:Drivers/CMSIS/Include/cmsis_gcc.h **** 304:Drivers/CMSIS/Include/cmsis_gcc.h **** 305:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 306:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) 307:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 308:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 309:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 310:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 311:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) 312:Drivers/CMSIS/Include/cmsis_gcc.h **** { 313:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 314:Drivers/CMSIS/Include/cmsis_gcc.h **** 315:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 316:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 317:Drivers/CMSIS/Include/cmsis_gcc.h **** } 318:Drivers/CMSIS/Include/cmsis_gcc.h **** 319:Drivers/CMSIS/Include/cmsis_gcc.h **** 320:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 321:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) 322:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam 323:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 324:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 325:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 326:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) 327:Drivers/CMSIS/Include/cmsis_gcc.h **** { 328:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 329:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); 330:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 331:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; 332:Drivers/CMSIS/Include/cmsis_gcc.h **** 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 334:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 335:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 336:Drivers/CMSIS/Include/cmsis_gcc.h **** } 337:Drivers/CMSIS/Include/cmsis_gcc.h **** 338:Drivers/CMSIS/Include/cmsis_gcc.h **** 339:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v 342:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate 343:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate 344:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value 345:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 346:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) 347:Drivers/CMSIS/Include/cmsis_gcc.h **** { 348:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; 349:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) 350:Drivers/CMSIS/Include/cmsis_gcc.h **** { 351:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; ARM GAS /tmp/ccWJ27fo.s page 19 352:Drivers/CMSIS/Include/cmsis_gcc.h **** } 353:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); 354:Drivers/CMSIS/Include/cmsis_gcc.h **** } 355:Drivers/CMSIS/Include/cmsis_gcc.h **** 356:Drivers/CMSIS/Include/cmsis_gcc.h **** 357:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 358:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint 359:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. 360:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula 361:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. 362:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break 363:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 364:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) 365:Drivers/CMSIS/Include/cmsis_gcc.h **** 366:Drivers/CMSIS/Include/cmsis_gcc.h **** 367:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value 369:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. 370:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 371:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 372:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 373:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) 374:Drivers/CMSIS/Include/cmsis_gcc.h **** { 375:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 377:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 378:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 379:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 380:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); 381:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 382:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ 383:Drivers/CMSIS/Include/cmsis_gcc.h **** 384:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ 385:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) 386:Drivers/CMSIS/Include/cmsis_gcc.h **** { 387:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; 388:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; 389:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; 390:Drivers/CMSIS/Include/cmsis_gcc.h **** } 391:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ 392:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 393:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 394:Drivers/CMSIS/Include/cmsis_gcc.h **** } 395:Drivers/CMSIS/Include/cmsis_gcc.h **** 396:Drivers/CMSIS/Include/cmsis_gcc.h **** 397:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 398:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Count leading zeros 399:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Counts the number of leading zeros of a data value. 400:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to count the leading zeros 401:Drivers/CMSIS/Include/cmsis_gcc.h **** \return number of leading zeros in value 402:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 403:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) 404:Drivers/CMSIS/Include/cmsis_gcc.h **** { 405:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Even though __builtin_clz produces a CLZ instruction on ARM, formally 406:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_clz(0) is undefined behaviour, so handle this case specially. 407:Drivers/CMSIS/Include/cmsis_gcc.h **** This guarantees ARM-compatible results if happening to compile on a non-ARM 408:Drivers/CMSIS/Include/cmsis_gcc.h **** target, and ensures the compiler doesn't decide to activate any ARM GAS /tmp/ccWJ27fo.s page 20 409:Drivers/CMSIS/Include/cmsis_gcc.h **** optimisations using the logic "value was passed to __builtin_clz, so it 410:Drivers/CMSIS/Include/cmsis_gcc.h **** is non-zero". 411:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a 412:Drivers/CMSIS/Include/cmsis_gcc.h **** single CLZ instruction. 413:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 414:Drivers/CMSIS/Include/cmsis_gcc.h **** if (value == 0U) 415:Drivers/CMSIS/Include/cmsis_gcc.h **** { 416:Drivers/CMSIS/Include/cmsis_gcc.h **** return 32U; 417:Drivers/CMSIS/Include/cmsis_gcc.h **** } 418:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_clz(value); 419:Drivers/CMSIS/Include/cmsis_gcc.h **** } 420:Drivers/CMSIS/Include/cmsis_gcc.h **** 421:Drivers/CMSIS/Include/cmsis_gcc.h **** 422:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 423:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 425:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 426:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 427:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (8 bit) 428:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 8 bit value. 429:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 430:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) 431:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 432:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) 433:Drivers/CMSIS/Include/cmsis_gcc.h **** { 434:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 435:Drivers/CMSIS/Include/cmsis_gcc.h **** 436:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 437:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); 438:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 439:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 440:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 441:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 442:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); 443:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 444:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); /* Add explicit type cast here */ 445:Drivers/CMSIS/Include/cmsis_gcc.h **** } 446:Drivers/CMSIS/Include/cmsis_gcc.h **** 447:Drivers/CMSIS/Include/cmsis_gcc.h **** 448:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 449:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (16 bit) 450:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 16 bit values. 451:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 452:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) 453:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 454:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) 455:Drivers/CMSIS/Include/cmsis_gcc.h **** { 456:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 457:Drivers/CMSIS/Include/cmsis_gcc.h **** 458:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 459:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); 460:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 461:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 462:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 463:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 464:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); 465:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif ARM GAS /tmp/ccWJ27fo.s page 21 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); /* Add explicit type cast here */ 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 469:Drivers/CMSIS/Include/cmsis_gcc.h **** 470:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 471:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (32 bit) 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 32 bit values. 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 479:Drivers/CMSIS/Include/cmsis_gcc.h **** 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } 483:Drivers/CMSIS/Include/cmsis_gcc.h **** 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 485:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 486:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (8 bit) 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 8 bit values. 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 490:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 491:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 492:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) 494:Drivers/CMSIS/Include/cmsis_gcc.h **** { 495:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 497:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); 498:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 499:Drivers/CMSIS/Include/cmsis_gcc.h **** } 500:Drivers/CMSIS/Include/cmsis_gcc.h **** 501:Drivers/CMSIS/Include/cmsis_gcc.h **** 502:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 503:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (16 bit) 504:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 16 bit values. 505:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 506:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 507:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 508:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 509:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 510:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) 511:Drivers/CMSIS/Include/cmsis_gcc.h **** { 512:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 513:Drivers/CMSIS/Include/cmsis_gcc.h **** 514:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); 515:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 516:Drivers/CMSIS/Include/cmsis_gcc.h **** } 517:Drivers/CMSIS/Include/cmsis_gcc.h **** 518:Drivers/CMSIS/Include/cmsis_gcc.h **** 519:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 520:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (32 bit) 521:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 32 bit values. 522:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store ARM GAS /tmp/ccWJ27fo.s page 22 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 530:Drivers/CMSIS/Include/cmsis_gcc.h **** 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } 534:Drivers/CMSIS/Include/cmsis_gcc.h **** 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 536:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 537:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Remove the exclusive lock 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Removes the exclusive lock which is created by LDREX. 539:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 540:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __CLREX(void) 541:Drivers/CMSIS/Include/cmsis_gcc.h **** { 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("clrex" ::: "memory"); 543:Drivers/CMSIS/Include/cmsis_gcc.h **** } 544:Drivers/CMSIS/Include/cmsis_gcc.h **** 545:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 546:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 547:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 548:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 549:Drivers/CMSIS/Include/cmsis_gcc.h **** 550:Drivers/CMSIS/Include/cmsis_gcc.h **** 551:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 552:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 553:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 554:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Signed Saturate 556:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Saturates a signed value. 557:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ARG1 Value to be saturated 558:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ARG2 Bit position to saturate to (1..32) 559:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Saturated value 560:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 561:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SSAT(ARG1, ARG2) \ 562:Drivers/CMSIS/Include/cmsis_gcc.h **** __extension__ \ 563:Drivers/CMSIS/Include/cmsis_gcc.h **** ({ \ 564:Drivers/CMSIS/Include/cmsis_gcc.h **** int32_t __RES, __ARG1 = (ARG1); \ 565:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ 566:Drivers/CMSIS/Include/cmsis_gcc.h **** __RES; \ 567:Drivers/CMSIS/Include/cmsis_gcc.h **** }) 568:Drivers/CMSIS/Include/cmsis_gcc.h **** 569:Drivers/CMSIS/Include/cmsis_gcc.h **** 570:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 571:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Unsigned Saturate 572:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Saturates an unsigned value. 573:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ARG1 Value to be saturated 574:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ARG2 Bit position to saturate to (0..31) 575:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Saturated value 576:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 577:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USAT(ARG1, ARG2) \ 578:Drivers/CMSIS/Include/cmsis_gcc.h **** __extension__ \ 579:Drivers/CMSIS/Include/cmsis_gcc.h **** ({ \ ARM GAS /tmp/ccWJ27fo.s page 23 580:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t __RES, __ARG1 = (ARG1); \ 581:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ 582:Drivers/CMSIS/Include/cmsis_gcc.h **** __RES; \ 583:Drivers/CMSIS/Include/cmsis_gcc.h **** }) 584:Drivers/CMSIS/Include/cmsis_gcc.h **** 585:Drivers/CMSIS/Include/cmsis_gcc.h **** 586:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 587:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right with Extend (32 bit) 588:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Moves each bit of a bitstring right by one bit. 589:Drivers/CMSIS/Include/cmsis_gcc.h **** The carry input is shifted in at the left end of the bitstring. 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to rotate 591:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value 592:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 593:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) 594:Drivers/CMSIS/Include/cmsis_gcc.h **** { 595:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 596:Drivers/CMSIS/Include/cmsis_gcc.h **** 597:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 598:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 599:Drivers/CMSIS/Include/cmsis_gcc.h **** } 600:Drivers/CMSIS/Include/cmsis_gcc.h **** 601:Drivers/CMSIS/Include/cmsis_gcc.h **** 602:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 603:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDRT Unprivileged (8 bit) 604:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged LDRT instruction for 8 bit value. 605:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 606:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) 607:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 608:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) 609:Drivers/CMSIS/Include/cmsis_gcc.h **** { 610:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 611:Drivers/CMSIS/Include/cmsis_gcc.h **** 612:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 613:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); 614:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 615:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 616:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 617:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 618:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 620:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); /* Add explicit type cast here */ 621:Drivers/CMSIS/Include/cmsis_gcc.h **** } 622:Drivers/CMSIS/Include/cmsis_gcc.h **** 623:Drivers/CMSIS/Include/cmsis_gcc.h **** 624:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 625:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDRT Unprivileged (16 bit) 626:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged LDRT instruction for 16 bit values. 627:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 628:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) 629:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 630:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) 631:Drivers/CMSIS/Include/cmsis_gcc.h **** { 632:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 633:Drivers/CMSIS/Include/cmsis_gcc.h **** 634:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 635:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); 636:Drivers/CMSIS/Include/cmsis_gcc.h **** #else ARM GAS /tmp/ccWJ27fo.s page 24 637:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 638:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 639:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 640:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); 641:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 642:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); /* Add explicit type cast here */ 643:Drivers/CMSIS/Include/cmsis_gcc.h **** } 644:Drivers/CMSIS/Include/cmsis_gcc.h **** 645:Drivers/CMSIS/Include/cmsis_gcc.h **** 646:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 647:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDRT Unprivileged (32 bit) 648:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged LDRT instruction for 32 bit values. 649:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 650:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) 651:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 652:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) 653:Drivers/CMSIS/Include/cmsis_gcc.h **** { 654:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 655:Drivers/CMSIS/Include/cmsis_gcc.h **** 656:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); 657:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 658:Drivers/CMSIS/Include/cmsis_gcc.h **** } 659:Drivers/CMSIS/Include/cmsis_gcc.h **** 660:Drivers/CMSIS/Include/cmsis_gcc.h **** 661:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 662:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STRT Unprivileged (8 bit) 663:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged STRT instruction for 8 bit values. 664:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 665:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 666:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 667:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) 668:Drivers/CMSIS/Include/cmsis_gcc.h **** { 669:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); 670:Drivers/CMSIS/Include/cmsis_gcc.h **** } 671:Drivers/CMSIS/Include/cmsis_gcc.h **** 672:Drivers/CMSIS/Include/cmsis_gcc.h **** 673:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 674:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STRT Unprivileged (16 bit) 675:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged STRT instruction for 16 bit values. 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { 681:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); 682:Drivers/CMSIS/Include/cmsis_gcc.h **** } 683:Drivers/CMSIS/Include/cmsis_gcc.h **** 684:Drivers/CMSIS/Include/cmsis_gcc.h **** 685:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 686:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STRT Unprivileged (32 bit) 687:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged STRT instruction for 32 bit values. 688:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 689:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 690:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 691:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) 692:Drivers/CMSIS/Include/cmsis_gcc.h **** { 693:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); ARM GAS /tmp/ccWJ27fo.s page 25 694:Drivers/CMSIS/Include/cmsis_gcc.h **** } 695:Drivers/CMSIS/Include/cmsis_gcc.h **** 696:Drivers/CMSIS/Include/cmsis_gcc.h **** #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 697:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 698:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 699:Drivers/CMSIS/Include/cmsis_gcc.h **** 700:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 701:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Signed Saturate 702:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Saturates a signed value. 703:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to be saturated 704:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] sat Bit position to saturate to (1..32) 705:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Saturated value 706:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 707:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) 708:Drivers/CMSIS/Include/cmsis_gcc.h **** { 709:Drivers/CMSIS/Include/cmsis_gcc.h **** if ((sat >= 1U) && (sat <= 32U)) 710:Drivers/CMSIS/Include/cmsis_gcc.h **** { 711:Drivers/CMSIS/Include/cmsis_gcc.h **** const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); 712:Drivers/CMSIS/Include/cmsis_gcc.h **** const int32_t min = -1 - max ; 713:Drivers/CMSIS/Include/cmsis_gcc.h **** if (val > max) 714:Drivers/CMSIS/Include/cmsis_gcc.h **** { 715:Drivers/CMSIS/Include/cmsis_gcc.h **** return max; 716:Drivers/CMSIS/Include/cmsis_gcc.h **** } 717:Drivers/CMSIS/Include/cmsis_gcc.h **** else if (val < min) 718:Drivers/CMSIS/Include/cmsis_gcc.h **** { 719:Drivers/CMSIS/Include/cmsis_gcc.h **** return min; 720:Drivers/CMSIS/Include/cmsis_gcc.h **** } 721:Drivers/CMSIS/Include/cmsis_gcc.h **** } 722:Drivers/CMSIS/Include/cmsis_gcc.h **** return val; 723:Drivers/CMSIS/Include/cmsis_gcc.h **** } 724:Drivers/CMSIS/Include/cmsis_gcc.h **** 725:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 726:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Unsigned Saturate 727:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Saturates an unsigned value. 728:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to be saturated 729:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] sat Bit position to saturate to (0..31) 730:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Saturated value 731:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) 733:Drivers/CMSIS/Include/cmsis_gcc.h **** { 734:Drivers/CMSIS/Include/cmsis_gcc.h **** if (sat <= 31U) 735:Drivers/CMSIS/Include/cmsis_gcc.h **** { 736:Drivers/CMSIS/Include/cmsis_gcc.h **** const uint32_t max = ((1U << sat) - 1U); 737:Drivers/CMSIS/Include/cmsis_gcc.h **** if (val > (int32_t)max) 738:Drivers/CMSIS/Include/cmsis_gcc.h **** { 739:Drivers/CMSIS/Include/cmsis_gcc.h **** return max; 740:Drivers/CMSIS/Include/cmsis_gcc.h **** } 741:Drivers/CMSIS/Include/cmsis_gcc.h **** else if (val < 0) 742:Drivers/CMSIS/Include/cmsis_gcc.h **** { 743:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 744:Drivers/CMSIS/Include/cmsis_gcc.h **** } 745:Drivers/CMSIS/Include/cmsis_gcc.h **** } 746:Drivers/CMSIS/Include/cmsis_gcc.h **** return (uint32_t)val; 747:Drivers/CMSIS/Include/cmsis_gcc.h **** } 748:Drivers/CMSIS/Include/cmsis_gcc.h **** 749:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ ARM GAS /tmp/ccWJ27fo.s page 26 751:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 752:Drivers/CMSIS/Include/cmsis_gcc.h **** 753:Drivers/CMSIS/Include/cmsis_gcc.h **** 754:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 755:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 756:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 757:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire (8 bit) 758:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDAB instruction for 8 bit value. 759:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 760:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) 761:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 762:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) 763:Drivers/CMSIS/Include/cmsis_gcc.h **** { 764:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 765:Drivers/CMSIS/Include/cmsis_gcc.h **** 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 767:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); 768:Drivers/CMSIS/Include/cmsis_gcc.h **** } 769:Drivers/CMSIS/Include/cmsis_gcc.h **** 770:Drivers/CMSIS/Include/cmsis_gcc.h **** 771:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 772:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire (16 bit) 773:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDAH instruction for 16 bit values. 774:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 775:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) 776:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 777:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) 778:Drivers/CMSIS/Include/cmsis_gcc.h **** { 779:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 780:Drivers/CMSIS/Include/cmsis_gcc.h **** 781:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); 783:Drivers/CMSIS/Include/cmsis_gcc.h **** } 784:Drivers/CMSIS/Include/cmsis_gcc.h **** 785:Drivers/CMSIS/Include/cmsis_gcc.h **** 786:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 787:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire (32 bit) 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDA instruction for 32 bit values. 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { 794:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 795:Drivers/CMSIS/Include/cmsis_gcc.h **** 796:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 797:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 798:Drivers/CMSIS/Include/cmsis_gcc.h **** } 799:Drivers/CMSIS/Include/cmsis_gcc.h **** 800:Drivers/CMSIS/Include/cmsis_gcc.h **** 801:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 802:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release (8 bit) 803:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STLB instruction for 8 bit values. 804:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 805:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 806:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 807:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) ARM GAS /tmp/ccWJ27fo.s page 27 808:Drivers/CMSIS/Include/cmsis_gcc.h **** { 809:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 810:Drivers/CMSIS/Include/cmsis_gcc.h **** } 811:Drivers/CMSIS/Include/cmsis_gcc.h **** 812:Drivers/CMSIS/Include/cmsis_gcc.h **** 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 814:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release (16 bit) 815:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STLH instruction for 16 bit values. 816:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 817:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 818:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 819:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) 820:Drivers/CMSIS/Include/cmsis_gcc.h **** { 821:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 822:Drivers/CMSIS/Include/cmsis_gcc.h **** } 823:Drivers/CMSIS/Include/cmsis_gcc.h **** 824:Drivers/CMSIS/Include/cmsis_gcc.h **** 825:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 826:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release (32 bit) 827:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STL instruction for 32 bit values. 828:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 829:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 830:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 831:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) 832:Drivers/CMSIS/Include/cmsis_gcc.h **** { 833:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 834:Drivers/CMSIS/Include/cmsis_gcc.h **** } 835:Drivers/CMSIS/Include/cmsis_gcc.h **** 836:Drivers/CMSIS/Include/cmsis_gcc.h **** 837:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 838:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire Exclusive (8 bit) 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDAB exclusive instruction for 8 bit value. 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 841:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) 842:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 843:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) 844:Drivers/CMSIS/Include/cmsis_gcc.h **** { 845:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 846:Drivers/CMSIS/Include/cmsis_gcc.h **** 847:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 848:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); 849:Drivers/CMSIS/Include/cmsis_gcc.h **** } 850:Drivers/CMSIS/Include/cmsis_gcc.h **** 851:Drivers/CMSIS/Include/cmsis_gcc.h **** 852:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 853:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire Exclusive (16 bit) 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDAH exclusive instruction for 16 bit values. 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 856:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) 857:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 858:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) 859:Drivers/CMSIS/Include/cmsis_gcc.h **** { 860:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 861:Drivers/CMSIS/Include/cmsis_gcc.h **** 862:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 863:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); 864:Drivers/CMSIS/Include/cmsis_gcc.h **** } ARM GAS /tmp/ccWJ27fo.s page 28 865:Drivers/CMSIS/Include/cmsis_gcc.h **** 866:Drivers/CMSIS/Include/cmsis_gcc.h **** 867:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 868:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire Exclusive (32 bit) 869:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDA exclusive instruction for 32 bit values. 870:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 871:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) 872:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 873:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) 874:Drivers/CMSIS/Include/cmsis_gcc.h **** { 875:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 876:Drivers/CMSIS/Include/cmsis_gcc.h **** 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 878:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 879:Drivers/CMSIS/Include/cmsis_gcc.h **** } 880:Drivers/CMSIS/Include/cmsis_gcc.h **** 881:Drivers/CMSIS/Include/cmsis_gcc.h **** 882:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 883:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release Exclusive (8 bit) 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STLB exclusive instruction for 8 bit values. 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 886:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 887:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 888:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 889:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) 891:Drivers/CMSIS/Include/cmsis_gcc.h **** { 892:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 893:Drivers/CMSIS/Include/cmsis_gcc.h **** 894:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem 895:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 896:Drivers/CMSIS/Include/cmsis_gcc.h **** } 897:Drivers/CMSIS/Include/cmsis_gcc.h **** 898:Drivers/CMSIS/Include/cmsis_gcc.h **** 899:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 900:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release Exclusive (16 bit) 901:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STLH exclusive instruction for 16 bit values. 902:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 903:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 904:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 905:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 906:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) 908:Drivers/CMSIS/Include/cmsis_gcc.h **** { 909:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 910:Drivers/CMSIS/Include/cmsis_gcc.h **** 911:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem 912:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 913:Drivers/CMSIS/Include/cmsis_gcc.h **** } 914:Drivers/CMSIS/Include/cmsis_gcc.h **** 915:Drivers/CMSIS/Include/cmsis_gcc.h **** 916:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release Exclusive (32 bit) 918:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STL exclusive instruction for 32 bit values. 919:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 920:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 921:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded ARM GAS /tmp/ccWJ27fo.s page 29 922:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 923:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 924:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) 925:Drivers/CMSIS/Include/cmsis_gcc.h **** { 926:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 927:Drivers/CMSIS/Include/cmsis_gcc.h **** 928:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memo 929:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 930:Drivers/CMSIS/Include/cmsis_gcc.h **** } 931:Drivers/CMSIS/Include/cmsis_gcc.h **** 932:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 933:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 934:Drivers/CMSIS/Include/cmsis_gcc.h **** 935:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ 936:Drivers/CMSIS/Include/cmsis_gcc.h **** 937:Drivers/CMSIS/Include/cmsis_gcc.h **** 938:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ 939:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface 940:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 941:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 942:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 943:Drivers/CMSIS/Include/cmsis_gcc.h **** 944:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 945:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts 946:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. 947:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 948:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 949:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) 950:Drivers/CMSIS/Include/cmsis_gcc.h **** { 951:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); 952:Drivers/CMSIS/Include/cmsis_gcc.h **** } 953:Drivers/CMSIS/Include/cmsis_gcc.h **** 954:Drivers/CMSIS/Include/cmsis_gcc.h **** 955:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 956:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts 957:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting special-purpose register PRIMASK. 958:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 959:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 960:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) 327 .loc 2 960 27 view .LVU82 328 .LBB11: 961:Drivers/CMSIS/Include/cmsis_gcc.h **** { 962:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); 329 .loc 2 962 3 view .LVU83 330 .syntax unified 331 @ 962 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 332 0000 72B6 cpsid i 333 @ 0 "" 2 334 .thumb 335 .syntax unified 336 .L10: 337 .LBE11: 338 .LBE10: 345:Core/Src/main.c **** while (1) 339 .loc 1 345 3 view .LVU84 346:Core/Src/main.c **** { 347:Core/Src/main.c **** } ARM GAS /tmp/ccWJ27fo.s page 30 340 .loc 1 347 3 view .LVU85 345:Core/Src/main.c **** while (1) 341 .loc 1 345 9 view .LVU86 342 0002 FEE7 b .L10 343 .cfi_endproc 344 .LFE248: 346 .section .text.MX_ADC1_Init,"ax",%progbits 347 .align 1 348 .syntax unified 349 .thumb 350 .thumb_func 352 MX_ADC1_Init: 353 .LFB245: 208:Core/Src/main.c **** 354 .loc 1 208 1 view -0 355 .cfi_startproc 356 @ args = 0, pretend = 0, frame = 16 357 @ frame_needed = 0, uses_anonymous_args = 0 358 0000 00B5 push {lr} 359 .LCFI6: 360 .cfi_def_cfa_offset 4 361 .cfi_offset 14, -4 362 0002 85B0 sub sp, sp, #20 363 .LCFI7: 364 .cfi_def_cfa_offset 24 214:Core/Src/main.c **** 365 .loc 1 214 3 view .LVU88 214:Core/Src/main.c **** 366 .loc 1 214 26 is_stmt 0 view .LVU89 367 0004 0023 movs r3, #0 368 0006 0093 str r3, [sp] 369 0008 0193 str r3, [sp, #4] 370 000a 0293 str r3, [sp, #8] 371 000c 0393 str r3, [sp, #12] 222:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; 372 .loc 1 222 3 is_stmt 1 view .LVU90 222:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; 373 .loc 1 222 18 is_stmt 0 view .LVU91 374 000e 1648 ldr r0, .L17 375 0010 164A ldr r2, .L17+4 376 0012 0260 str r2, [r0] 223:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; 377 .loc 1 223 3 is_stmt 1 view .LVU92 223:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; 378 .loc 1 223 29 is_stmt 0 view .LVU93 379 0014 4FF48032 mov r2, #65536 380 0018 4260 str r2, [r0, #4] 224:Core/Src/main.c **** hadc1.Init.ScanConvMode = DISABLE; 381 .loc 1 224 3 is_stmt 1 view .LVU94 224:Core/Src/main.c **** hadc1.Init.ScanConvMode = DISABLE; 382 .loc 1 224 25 is_stmt 0 view .LVU95 383 001a 8360 str r3, [r0, #8] 225:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; 384 .loc 1 225 3 is_stmt 1 view .LVU96 225:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; 385 .loc 1 225 27 is_stmt 0 view .LVU97 386 001c 0361 str r3, [r0, #16] ARM GAS /tmp/ccWJ27fo.s page 31 226:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; 387 .loc 1 226 3 is_stmt 1 view .LVU98 226:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; 388 .loc 1 226 33 is_stmt 0 view .LVU99 389 001e 0376 strb r3, [r0, #24] 227:Core/Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 390 .loc 1 227 3 is_stmt 1 view .LVU100 227:Core/Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 391 .loc 1 227 36 is_stmt 0 view .LVU101 392 0020 80F82030 strb r3, [r0, #32] 228:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_Ext_IT11; 393 .loc 1 228 3 is_stmt 1 view .LVU102 228:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_Ext_IT11; 394 .loc 1 228 35 is_stmt 0 view .LVU103 395 0024 4FF08052 mov r2, #268435456 396 0028 C262 str r2, [r0, #44] 229:Core/Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 397 .loc 1 229 3 is_stmt 1 view .LVU104 229:Core/Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 398 .loc 1 229 31 is_stmt 0 view .LVU105 399 002a 4FF07062 mov r2, #251658240 400 002e 8262 str r2, [r0, #40] 230:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1; 401 .loc 1 230 3 is_stmt 1 view .LVU106 230:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1; 402 .loc 1 230 24 is_stmt 0 view .LVU107 403 0030 C360 str r3, [r0, #12] 231:Core/Src/main.c **** hadc1.Init.DMAContinuousRequests = ENABLE; 404 .loc 1 231 3 is_stmt 1 view .LVU108 231:Core/Src/main.c **** hadc1.Init.DMAContinuousRequests = ENABLE; 405 .loc 1 231 30 is_stmt 0 view .LVU109 406 0032 0123 movs r3, #1 407 0034 C361 str r3, [r0, #28] 232:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 408 .loc 1 232 3 is_stmt 1 view .LVU110 232:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 409 .loc 1 232 36 is_stmt 0 view .LVU111 410 0036 80F83030 strb r3, [r0, #48] 233:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) 411 .loc 1 233 3 is_stmt 1 view .LVU112 233:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) 412 .loc 1 233 27 is_stmt 0 view .LVU113 413 003a 4361 str r3, [r0, #20] 234:Core/Src/main.c **** { 414 .loc 1 234 3 is_stmt 1 view .LVU114 234:Core/Src/main.c **** { 415 .loc 1 234 7 is_stmt 0 view .LVU115 416 003c FFF7FEFF bl HAL_ADC_Init 417 .LVL12: 234:Core/Src/main.c **** { 418 .loc 1 234 6 discriminator 1 view .LVU116 419 0040 68B9 cbnz r0, .L15 241:Core/Src/main.c **** sConfig.Rank = 1; 420 .loc 1 241 3 is_stmt 1 view .LVU117 241:Core/Src/main.c **** sConfig.Rank = 1; 421 .loc 1 241 19 is_stmt 0 view .LVU118 422 0042 0323 movs r3, #3 ARM GAS /tmp/ccWJ27fo.s page 32 423 0044 0093 str r3, [sp] 242:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; 424 .loc 1 242 3 is_stmt 1 view .LVU119 242:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; 425 .loc 1 242 16 is_stmt 0 view .LVU120 426 0046 0123 movs r3, #1 427 0048 0193 str r3, [sp, #4] 243:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 428 .loc 1 243 3 is_stmt 1 view .LVU121 243:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 429 .loc 1 243 24 is_stmt 0 view .LVU122 430 004a 0023 movs r3, #0 431 004c 0293 str r3, [sp, #8] 244:Core/Src/main.c **** { 432 .loc 1 244 3 is_stmt 1 view .LVU123 244:Core/Src/main.c **** { 433 .loc 1 244 7 is_stmt 0 view .LVU124 434 004e 6946 mov r1, sp 435 0050 0548 ldr r0, .L17 436 0052 FFF7FEFF bl HAL_ADC_ConfigChannel 437 .LVL13: 244:Core/Src/main.c **** { 438 .loc 1 244 6 discriminator 1 view .LVU125 439 0056 20B9 cbnz r0, .L16 252:Core/Src/main.c **** 440 .loc 1 252 1 view .LVU126 441 0058 05B0 add sp, sp, #20 442 .LCFI8: 443 .cfi_remember_state 444 .cfi_def_cfa_offset 4 445 @ sp needed 446 005a 5DF804FB ldr pc, [sp], #4 447 .L15: 448 .LCFI9: 449 .cfi_restore_state 236:Core/Src/main.c **** } 450 .loc 1 236 5 is_stmt 1 view .LVU127 451 005e FFF7FEFF bl Error_Handler 452 .LVL14: 453 .L16: 246:Core/Src/main.c **** } 454 .loc 1 246 5 view .LVU128 455 0062 FFF7FEFF bl Error_Handler 456 .LVL15: 457 .L18: 458 0066 00BF .align 2 459 .L17: 460 0068 00000000 .word hadc1 461 006c 00200140 .word 1073815552 462 .cfi_endproc 463 .LFE245: 465 .section .text.SystemClock_Config,"ax",%progbits 466 .align 1 467 .global SystemClock_Config 468 .syntax unified 469 .thumb 470 .thumb_func ARM GAS /tmp/ccWJ27fo.s page 33 472 SystemClock_Config: 473 .LFB244: 162:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 474 .loc 1 162 1 view -0 475 .cfi_startproc 476 @ args = 0, pretend = 0, frame = 80 477 @ frame_needed = 0, uses_anonymous_args = 0 478 0000 00B5 push {lr} 479 .LCFI10: 480 .cfi_def_cfa_offset 4 481 .cfi_offset 14, -4 482 0002 95B0 sub sp, sp, #84 483 .LCFI11: 484 .cfi_def_cfa_offset 88 163:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 485 .loc 1 163 3 view .LVU130 163:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 486 .loc 1 163 22 is_stmt 0 view .LVU131 487 0004 3022 movs r2, #48 488 0006 0021 movs r1, #0 489 0008 08A8 add r0, sp, #32 490 000a FFF7FEFF bl memset 491 .LVL16: 164:Core/Src/main.c **** 492 .loc 1 164 3 is_stmt 1 view .LVU132 164:Core/Src/main.c **** 493 .loc 1 164 22 is_stmt 0 view .LVU133 494 000e 0023 movs r3, #0 495 0010 0393 str r3, [sp, #12] 496 0012 0493 str r3, [sp, #16] 497 0014 0593 str r3, [sp, #20] 498 0016 0693 str r3, [sp, #24] 499 0018 0793 str r3, [sp, #28] 168:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 500 .loc 1 168 3 is_stmt 1 view .LVU134 501 .LBB12: 168:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 502 .loc 1 168 3 view .LVU135 503 001a 0193 str r3, [sp, #4] 168:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 504 .loc 1 168 3 view .LVU136 505 001c 214A ldr r2, .L25 506 001e 116C ldr r1, [r2, #64] 507 0020 41F08051 orr r1, r1, #268435456 508 0024 1164 str r1, [r2, #64] 168:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 509 .loc 1 168 3 view .LVU137 510 0026 126C ldr r2, [r2, #64] 511 0028 02F08052 and r2, r2, #268435456 512 002c 0192 str r2, [sp, #4] 168:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 513 .loc 1 168 3 view .LVU138 514 002e 019A ldr r2, [sp, #4] 515 .LBE12: 168:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 516 .loc 1 168 3 view .LVU139 169:Core/Src/main.c **** ARM GAS /tmp/ccWJ27fo.s page 34 517 .loc 1 169 3 view .LVU140 518 .LBB13: 169:Core/Src/main.c **** 519 .loc 1 169 3 view .LVU141 520 0030 0293 str r3, [sp, #8] 169:Core/Src/main.c **** 521 .loc 1 169 3 view .LVU142 522 0032 1D4B ldr r3, .L25+4 523 0034 1A68 ldr r2, [r3] 524 0036 42F44042 orr r2, r2, #49152 525 003a 1A60 str r2, [r3] 169:Core/Src/main.c **** 526 .loc 1 169 3 view .LVU143 527 003c 1B68 ldr r3, [r3] 528 003e 03F44043 and r3, r3, #49152 529 0042 0293 str r3, [sp, #8] 169:Core/Src/main.c **** 530 .loc 1 169 3 view .LVU144 531 0044 029B ldr r3, [sp, #8] 532 .LBE13: 169:Core/Src/main.c **** 533 .loc 1 169 3 view .LVU145 174:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 534 .loc 1 174 3 view .LVU146 174:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 535 .loc 1 174 36 is_stmt 0 view .LVU147 536 0046 0123 movs r3, #1 537 0048 0893 str r3, [sp, #32] 175:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 538 .loc 1 175 3 is_stmt 1 view .LVU148 175:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 539 .loc 1 175 30 is_stmt 0 view .LVU149 540 004a 4FF48033 mov r3, #65536 541 004e 0993 str r3, [sp, #36] 176:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 542 .loc 1 176 3 is_stmt 1 view .LVU150 176:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 543 .loc 1 176 34 is_stmt 0 view .LVU151 544 0050 0223 movs r3, #2 545 0052 0E93 str r3, [sp, #56] 177:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 8; 546 .loc 1 177 3 is_stmt 1 view .LVU152 177:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 8; 547 .loc 1 177 35 is_stmt 0 view .LVU153 548 0054 4FF48002 mov r2, #4194304 549 0058 0F92 str r2, [sp, #60] 178:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 336; 550 .loc 1 178 3 is_stmt 1 view .LVU154 178:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 336; 551 .loc 1 178 30 is_stmt 0 view .LVU155 552 005a 0822 movs r2, #8 553 005c 1092 str r2, [sp, #64] 179:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 554 .loc 1 179 3 is_stmt 1 view .LVU156 179:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 555 .loc 1 179 30 is_stmt 0 view .LVU157 556 005e 4FF4A872 mov r2, #336 ARM GAS /tmp/ccWJ27fo.s page 35 557 0062 1192 str r2, [sp, #68] 180:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 7; 558 .loc 1 180 3 is_stmt 1 view .LVU158 180:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 7; 559 .loc 1 180 30 is_stmt 0 view .LVU159 560 0064 1293 str r3, [sp, #72] 181:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 561 .loc 1 181 3 is_stmt 1 view .LVU160 181:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 562 .loc 1 181 30 is_stmt 0 view .LVU161 563 0066 0723 movs r3, #7 564 0068 1393 str r3, [sp, #76] 182:Core/Src/main.c **** { 565 .loc 1 182 3 is_stmt 1 view .LVU162 182:Core/Src/main.c **** { 566 .loc 1 182 7 is_stmt 0 view .LVU163 567 006a 08A8 add r0, sp, #32 568 006c FFF7FEFF bl HAL_RCC_OscConfig 569 .LVL17: 182:Core/Src/main.c **** { 570 .loc 1 182 6 discriminator 1 view .LVU164 571 0070 98B9 cbnz r0, .L23 189:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 572 .loc 1 189 3 is_stmt 1 view .LVU165 189:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 573 .loc 1 189 31 is_stmt 0 view .LVU166 574 0072 0F23 movs r3, #15 575 0074 0393 str r3, [sp, #12] 191:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 576 .loc 1 191 3 is_stmt 1 view .LVU167 191:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 577 .loc 1 191 34 is_stmt 0 view .LVU168 578 0076 0223 movs r3, #2 579 0078 0493 str r3, [sp, #16] 192:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 580 .loc 1 192 3 is_stmt 1 view .LVU169 192:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 581 .loc 1 192 35 is_stmt 0 view .LVU170 582 007a 0023 movs r3, #0 583 007c 0593 str r3, [sp, #20] 193:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 584 .loc 1 193 3 is_stmt 1 view .LVU171 193:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 585 .loc 1 193 36 is_stmt 0 view .LVU172 586 007e 4FF4A053 mov r3, #5120 587 0082 0693 str r3, [sp, #24] 194:Core/Src/main.c **** 588 .loc 1 194 3 is_stmt 1 view .LVU173 194:Core/Src/main.c **** 589 .loc 1 194 36 is_stmt 0 view .LVU174 590 0084 4FF48053 mov r3, #4096 591 0088 0793 str r3, [sp, #28] 196:Core/Src/main.c **** { 592 .loc 1 196 3 is_stmt 1 view .LVU175 196:Core/Src/main.c **** { 593 .loc 1 196 7 is_stmt 0 view .LVU176 594 008a 0521 movs r1, #5 ARM GAS /tmp/ccWJ27fo.s page 36 595 008c 03A8 add r0, sp, #12 596 008e FFF7FEFF bl HAL_RCC_ClockConfig 597 .LVL18: 196:Core/Src/main.c **** { 598 .loc 1 196 6 discriminator 1 view .LVU177 599 0092 20B9 cbnz r0, .L24 200:Core/Src/main.c **** 600 .loc 1 200 1 view .LVU178 601 0094 15B0 add sp, sp, #84 602 .LCFI12: 603 .cfi_remember_state 604 .cfi_def_cfa_offset 4 605 @ sp needed 606 0096 5DF804FB ldr pc, [sp], #4 607 .L23: 608 .LCFI13: 609 .cfi_restore_state 184:Core/Src/main.c **** } 610 .loc 1 184 5 is_stmt 1 view .LVU179 611 009a FFF7FEFF bl Error_Handler 612 .LVL19: 613 .L24: 198:Core/Src/main.c **** } 614 .loc 1 198 5 view .LVU180 615 009e FFF7FEFF bl Error_Handler 616 .LVL20: 617 .L26: 618 00a2 00BF .align 2 619 .L25: 620 00a4 00380240 .word 1073887232 621 00a8 00700040 .word 1073770496 622 .cfi_endproc 623 .LFE244: 625 .global __aeabi_ldivmod 626 .section .text.main,"ax",%progbits 627 .align 1 628 .global main 629 .syntax unified 630 .thumb 631 .thumb_func 633 main: 634 .LFB243: 78:Core/Src/main.c **** 635 .loc 1 78 1 view -0 636 .cfi_startproc 637 @ Volatile: function does not return. 638 @ args = 0, pretend = 0, frame = 0 639 @ frame_needed = 0, uses_anonymous_args = 0 640 0000 08B5 push {r3, lr} 641 .LCFI14: 642 .cfi_def_cfa_offset 8 643 .cfi_offset 3, -8 644 .cfi_offset 14, -4 87:Core/Src/main.c **** 645 .loc 1 87 3 view .LVU182 646 0002 FFF7FEFF bl HAL_Init 647 .LVL21: ARM GAS /tmp/ccWJ27fo.s page 37 94:Core/Src/main.c **** 648 .loc 1 94 3 view .LVU183 649 0006 FFF7FEFF bl SystemClock_Config 650 .LVL22: 101:Core/Src/main.c **** MX_DMA_Init(); 651 .loc 1 101 3 view .LVU184 652 000a FFF7FEFF bl MX_GPIO_Init 653 .LVL23: 102:Core/Src/main.c **** MX_ADC1_Init(); 654 .loc 1 102 3 view .LVU185 655 000e FFF7FEFF bl MX_DMA_Init 656 .LVL24: 103:Core/Src/main.c **** MX_USB_DEVICE_Init(); 657 .loc 1 103 3 view .LVU186 658 0012 FFF7FEFF bl MX_ADC1_Init 659 .LVL25: 104:Core/Src/main.c **** /* USER CODE BEGIN 2 */ 660 .loc 1 104 3 view .LVU187 661 0016 FFF7FEFF bl MX_USB_DEVICE_Init 662 .LVL26: 106:Core/Src/main.c **** HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADC1_buff_circular, ADC_BUFF_SIZE); 663 .loc 1 106 3 view .LVU188 664 001a 0122 movs r2, #1 665 001c 8021 movs r1, #128 666 001e 6C48 ldr r0, .L32+8 667 0020 FFF7FEFF bl HAL_GPIO_WritePin 668 .LVL27: 107:Core/Src/main.c **** 669 .loc 1 107 3 view .LVU189 670 0024 6422 movs r2, #100 671 0026 6B49 ldr r1, .L32+12 672 0028 6B48 ldr r0, .L32+16 673 002a FFF7FEFF bl HAL_ADC_Start_DMA 674 .LVL28: 109:Core/Src/main.c **** ADC_proc_shadow.N = 0; 675 .loc 1 109 3 view .LVU190 109:Core/Src/main.c **** ADC_proc_shadow.N = 0; 676 .loc 1 109 26 is_stmt 0 view .LVU191 677 002e 6B4A ldr r2, .L32+20 678 0030 0023 movs r3, #0 679 0032 1370 strb r3, [r2] 110:Core/Src/main.c **** ADC_proc_shadow.sum = 0; 680 .loc 1 110 3 is_stmt 1 view .LVU192 110:Core/Src/main.c **** ADC_proc_shadow.sum = 0; 681 .loc 1 110 21 is_stmt 0 view .LVU193 682 0034 D360 str r3, [r2, #12] 111:Core/Src/main.c **** ADC_proc_shadow.avg = 0; 683 .loc 1 111 3 is_stmt 1 view .LVU194 111:Core/Src/main.c **** ADC_proc_shadow.avg = 0; 684 .loc 1 111 23 is_stmt 0 view .LVU195 685 0036 5360 str r3, [r2, #4] 112:Core/Src/main.c **** 686 .loc 1 112 3 is_stmt 1 view .LVU196 112:Core/Src/main.c **** 687 .loc 1 112 23 is_stmt 0 view .LVU197 688 0038 9360 str r3, [r2, #8] 114:Core/Src/main.c **** ADC_proc.N = 0; ARM GAS /tmp/ccWJ27fo.s page 38 689 .loc 1 114 3 is_stmt 1 view .LVU198 114:Core/Src/main.c **** ADC_proc.N = 0; 690 .loc 1 114 19 is_stmt 0 view .LVU199 691 003a 694A ldr r2, .L32+24 692 003c 1370 strb r3, [r2] 115:Core/Src/main.c **** ADC_proc.sum = 0; 693 .loc 1 115 3 is_stmt 1 view .LVU200 115:Core/Src/main.c **** ADC_proc.sum = 0; 694 .loc 1 115 14 is_stmt 0 view .LVU201 695 003e D360 str r3, [r2, #12] 116:Core/Src/main.c **** ADC_proc.avg = 0; 696 .loc 1 116 3 is_stmt 1 view .LVU202 116:Core/Src/main.c **** ADC_proc.avg = 0; 697 .loc 1 116 16 is_stmt 0 view .LVU203 698 0040 5360 str r3, [r2, #4] 117:Core/Src/main.c **** 699 .loc 1 117 3 is_stmt 1 view .LVU204 117:Core/Src/main.c **** 700 .loc 1 117 16 is_stmt 0 view .LVU205 701 0042 9360 str r3, [r2, #8] 702 .L28: 123:Core/Src/main.c **** { 703 .loc 1 123 3 is_stmt 1 view .LVU206 125:Core/Src/main.c **** //HAL_Delay(100); 704 .loc 1 125 5 view .LVU207 705 0044 4FF48041 mov r1, #16384 706 0048 6148 ldr r0, .L32+8 707 004a FFF7FEFF bl HAL_GPIO_TogglePin 708 .LVL29: 128:Core/Src/main.c **** ADC_proc_shadow.avg = ADC_proc_shadow.sum / ADC_proc_shadow.N; 709 .loc 1 128 5 view .LVU208 128:Core/Src/main.c **** ADC_proc_shadow.avg = ADC_proc_shadow.sum / ADC_proc_shadow.N; 710 .loc 1 128 24 is_stmt 0 view .LVU209 711 004e 634B ldr r3, .L32+20 712 0050 1B78 ldrb r3, [r3] @ zero_extendqisi2 128:Core/Src/main.c **** ADC_proc_shadow.avg = ADC_proc_shadow.sum / ADC_proc_shadow.N; 713 .loc 1 128 8 view .LVU210 714 0052 022B cmp r3, #2 715 0054 F6D1 bne .L28 716 .LBB14: 129:Core/Src/main.c **** ADC_proc_shadow.status = 1; // reset for next accumulation 717 .loc 1 129 7 is_stmt 1 view .LVU211 129:Core/Src/main.c **** ADC_proc_shadow.status = 1; // reset for next accumulation 718 .loc 1 129 44 is_stmt 0 view .LVU212 719 0056 614B ldr r3, .L32+20 720 0058 5C68 ldr r4, [r3, #4] 129:Core/Src/main.c **** ADC_proc_shadow.status = 1; // reset for next accumulation 721 .loc 1 129 66 view .LVU213 722 005a DA68 ldr r2, [r3, #12] 129:Core/Src/main.c **** ADC_proc_shadow.status = 1; // reset for next accumulation 723 .loc 1 129 49 view .LVU214 724 005c B4FBF2F4 udiv r4, r4, r2 129:Core/Src/main.c **** ADC_proc_shadow.status = 1; // reset for next accumulation 725 .loc 1 129 27 view .LVU215 726 0060 9C60 str r4, [r3, #8] 130:Core/Src/main.c **** ADC_proc_shadow.sum = 0; 727 .loc 1 130 7 is_stmt 1 view .LVU216 ARM GAS /tmp/ccWJ27fo.s page 39 130:Core/Src/main.c **** ADC_proc_shadow.sum = 0; 728 .loc 1 130 30 is_stmt 0 view .LVU217 729 0062 0122 movs r2, #1 730 0064 1A70 strb r2, [r3] 131:Core/Src/main.c **** ADC_proc_shadow.N = 0; 731 .loc 1 131 7 is_stmt 1 view .LVU218 131:Core/Src/main.c **** ADC_proc_shadow.N = 0; 732 .loc 1 131 27 is_stmt 0 view .LVU219 733 0066 0021 movs r1, #0 734 0068 5960 str r1, [r3, #4] 132:Core/Src/main.c **** 735 .loc 1 132 7 is_stmt 1 view .LVU220 132:Core/Src/main.c **** 736 .loc 1 132 25 is_stmt 0 view .LVU221 737 006a D960 str r1, [r3, #12] 135:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 1] = (ADC_proc_shadow.avg / 1000000000) % 10 + '0'; 738 .loc 1 135 7 is_stmt 1 view .LVU222 135:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 1] = (ADC_proc_shadow.avg / 1000000000) % 10 + '0'; 739 .loc 1 135 59 is_stmt 0 view .LVU223 740 006c 56A3 adr r3, .L32 741 006e D3E90023 ldrd r2, [r3] 742 0072 2046 mov r0, r4 743 0074 FFF7FEFF bl __aeabi_ldivmod 744 .LVL30: 745 0078 8446 mov ip, r0 135:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 1] = (ADC_proc_shadow.avg / 1000000000) % 10 + '0'; 746 .loc 1 135 74 view .LVU224 747 007a 4FEAE17E asr lr, r1, #31 748 007e 0EF00302 and r2, lr, #3 749 0082 20F07043 bic r3, r0, #-268435456 750 0086 000F lsrs r0, r0, #28 751 0088 40EA0110 orr r0, r0, r1, lsl #4 752 008c 20F07040 bic r0, r0, #-268435456 753 0090 0344 add r3, r3, r0 754 0092 03EB1163 add r3, r3, r1, lsr #24 755 0096 1344 add r3, r3, r2 756 0098 524A ldr r2, .L32+28 757 009a A2FB0305 umull r0, r5, r2, r3 758 009e 25F00300 bic r0, r5, #3 759 00a2 00EB9500 add r0, r0, r5, lsr #2 760 00a6 1B1A subs r3, r3, r0 761 00a8 2EF0030E bic lr, lr, #3 762 00ac 7344 add r3, r3, lr 763 00ae BCEB0300 subs r0, ip, r3 764 00b2 61EBE371 sbc r1, r1, r3, asr #31 765 00b6 4FF0CC33 mov r3, #-858993460 766 00ba 00FB03F3 mul r3, r0, r3 767 00be 02FB0133 mla r3, r2, r1, r3 768 00c2 A0FB0202 umull r0, r2, r0, r2 769 00c6 1A44 add r2, r2, r3 770 00c8 D30F lsrs r3, r2, #31 771 00ca 1B18 adds r3, r3, r0 772 00cc 42F10002 adc r2, r2, #0 773 00d0 5B08 lsrs r3, r3, #1 774 00d2 43EAC273 orr r3, r3, r2, lsl #31 775 00d6 03EB8303 add r3, r3, r3, lsl #2 776 00da ACEB430C sub ip, ip, r3, lsl #1 ARM GAS /tmp/ccWJ27fo.s page 40 135:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 1] = (ADC_proc_shadow.avg / 1000000000) % 10 + '0'; 777 .loc 1 135 79 view .LVU225 778 00de 0CF1300C add ip, ip, #48 135:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 1] = (ADC_proc_shadow.avg / 1000000000) % 10 + '0'; 779 .loc 1 135 36 view .LVU226 780 00e2 4148 ldr r0, .L32+32 781 00e4 80F814C0 strb ip, [r0, #20] 136:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 2] = (ADC_proc_shadow.avg / 10000000) % 10 + '0'; 782 .loc 1 136 7 is_stmt 1 view .LVU227 136:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 2] = (ADC_proc_shadow.avg / 10000000) % 10 + '0'; 783 .loc 1 136 59 is_stmt 0 view .LVU228 784 00e8 620A lsrs r2, r4, #9 785 00ea 404B ldr r3, .L32+36 786 00ec A3FB0232 umull r3, r2, r3, r2 136:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 2] = (ADC_proc_shadow.avg / 10000000) % 10 + '0'; 787 .loc 1 136 73 view .LVU229 788 00f0 3C4B ldr r3, .L32+28 789 00f2 D209 lsrs r2, r2, #7 136:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 2] = (ADC_proc_shadow.avg / 10000000) % 10 + '0'; 790 .loc 1 136 78 view .LVU230 791 00f4 3032 adds r2, r2, #48 136:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 2] = (ADC_proc_shadow.avg / 10000000) % 10 + '0'; 792 .loc 1 136 36 view .LVU231 793 00f6 4275 strb r2, [r0, #21] 137:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 3] = (ADC_proc_shadow.avg / 1000000) % 10 + '0'; 794 .loc 1 137 7 is_stmt 1 view .LVU232 137:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 3] = (ADC_proc_shadow.avg / 1000000) % 10 + '0'; 795 .loc 1 137 59 is_stmt 0 view .LVU233 796 00f8 3D49 ldr r1, .L32+40 797 00fa A1FB0421 umull r2, r1, r1, r4 798 00fe 890D lsrs r1, r1, #22 137:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 3] = (ADC_proc_shadow.avg / 1000000) % 10 + '0'; 799 .loc 1 137 71 view .LVU234 800 0100 A3FB0152 umull r5, r2, r3, r1 801 0104 D208 lsrs r2, r2, #3 802 0106 02EB8202 add r2, r2, r2, lsl #2 803 010a A1EB4202 sub r2, r1, r2, lsl #1 137:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 3] = (ADC_proc_shadow.avg / 1000000) % 10 + '0'; 804 .loc 1 137 76 view .LVU235 805 010e 3032 adds r2, r2, #48 137:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 3] = (ADC_proc_shadow.avg / 1000000) % 10 + '0'; 806 .loc 1 137 36 view .LVU236 807 0110 8275 strb r2, [r0, #22] 138:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 4] = (ADC_proc_shadow.avg / 100000) % 10 + '0'; 808 .loc 1 138 7 is_stmt 1 view .LVU237 138:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 4] = (ADC_proc_shadow.avg / 100000) % 10 + '0'; 809 .loc 1 138 59 is_stmt 0 view .LVU238 810 0112 3849 ldr r1, .L32+44 811 0114 A1FB0421 umull r2, r1, r1, r4 812 0118 890C lsrs r1, r1, #18 138:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 4] = (ADC_proc_shadow.avg / 100000) % 10 + '0'; 813 .loc 1 138 70 view .LVU239 814 011a A3FB0152 umull r5, r2, r3, r1 815 011e D208 lsrs r2, r2, #3 816 0120 02EB8202 add r2, r2, r2, lsl #2 817 0124 A1EB4202 sub r2, r1, r2, lsl #1 138:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 4] = (ADC_proc_shadow.avg / 100000) % 10 + '0'; ARM GAS /tmp/ccWJ27fo.s page 41 818 .loc 1 138 75 view .LVU240 819 0128 3032 adds r2, r2, #48 138:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 4] = (ADC_proc_shadow.avg / 100000) % 10 + '0'; 820 .loc 1 138 36 view .LVU241 821 012a C275 strb r2, [r0, #23] 139:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 5] = (ADC_proc_shadow.avg / 10000) % 10 + '0'; 822 .loc 1 139 7 is_stmt 1 view .LVU242 139:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 5] = (ADC_proc_shadow.avg / 10000) % 10 + '0'; 823 .loc 1 139 59 is_stmt 0 view .LVU243 824 012c 6109 lsrs r1, r4, #5 825 012e 324A ldr r2, .L32+48 826 0130 A2FB0121 umull r2, r1, r2, r1 827 0134 C909 lsrs r1, r1, #7 139:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 5] = (ADC_proc_shadow.avg / 10000) % 10 + '0'; 828 .loc 1 139 69 view .LVU244 829 0136 A3FB0152 umull r5, r2, r3, r1 830 013a D208 lsrs r2, r2, #3 831 013c 02EB8202 add r2, r2, r2, lsl #2 832 0140 A1EB4202 sub r2, r1, r2, lsl #1 139:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 5] = (ADC_proc_shadow.avg / 10000) % 10 + '0'; 833 .loc 1 139 74 view .LVU245 834 0144 3032 adds r2, r2, #48 139:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 5] = (ADC_proc_shadow.avg / 10000) % 10 + '0'; 835 .loc 1 139 36 view .LVU246 836 0146 0276 strb r2, [r0, #24] 140:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 6] = (ADC_proc_shadow.avg / 1000) % 10 + '0'; 837 .loc 1 140 7 is_stmt 1 view .LVU247 140:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 6] = (ADC_proc_shadow.avg / 1000) % 10 + '0'; 838 .loc 1 140 59 is_stmt 0 view .LVU248 839 0148 2C49 ldr r1, .L32+52 840 014a A1FB0421 umull r2, r1, r1, r4 841 014e 490B lsrs r1, r1, #13 140:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 6] = (ADC_proc_shadow.avg / 1000) % 10 + '0'; 842 .loc 1 140 68 view .LVU249 843 0150 A3FB0152 umull r5, r2, r3, r1 844 0154 D208 lsrs r2, r2, #3 845 0156 02EB8202 add r2, r2, r2, lsl #2 846 015a A1EB4202 sub r2, r1, r2, lsl #1 140:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 6] = (ADC_proc_shadow.avg / 1000) % 10 + '0'; 847 .loc 1 140 73 view .LVU250 848 015e 3032 adds r2, r2, #48 140:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 6] = (ADC_proc_shadow.avg / 1000) % 10 + '0'; 849 .loc 1 140 36 view .LVU251 850 0160 4276 strb r2, [r0, #25] 141:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 7] = (ADC_proc_shadow.avg / 100) % 10 + '0'; 851 .loc 1 141 7 is_stmt 1 view .LVU252 141:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 7] = (ADC_proc_shadow.avg / 100) % 10 + '0'; 852 .loc 1 141 59 is_stmt 0 view .LVU253 853 0162 2749 ldr r1, .L32+56 854 0164 A1FB0421 umull r2, r1, r1, r4 855 0168 8909 lsrs r1, r1, #6 141:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 7] = (ADC_proc_shadow.avg / 100) % 10 + '0'; 856 .loc 1 141 67 view .LVU254 857 016a A3FB0152 umull r5, r2, r3, r1 858 016e D208 lsrs r2, r2, #3 859 0170 02EB8202 add r2, r2, r2, lsl #2 860 0174 A1EB4202 sub r2, r1, r2, lsl #1 ARM GAS /tmp/ccWJ27fo.s page 42 141:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 7] = (ADC_proc_shadow.avg / 100) % 10 + '0'; 861 .loc 1 141 72 view .LVU255 862 0178 3032 adds r2, r2, #48 141:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 7] = (ADC_proc_shadow.avg / 100) % 10 + '0'; 863 .loc 1 141 36 view .LVU256 864 017a 8276 strb r2, [r0, #26] 142:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 8] = (ADC_proc_shadow.avg / 10) % 10 + '0'; 865 .loc 1 142 7 is_stmt 1 view .LVU257 142:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 8] = (ADC_proc_shadow.avg / 10) % 10 + '0'; 866 .loc 1 142 59 is_stmt 0 view .LVU258 867 017c 2149 ldr r1, .L32+60 868 017e A1FB0421 umull r2, r1, r1, r4 869 0182 4909 lsrs r1, r1, #5 142:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 8] = (ADC_proc_shadow.avg / 10) % 10 + '0'; 870 .loc 1 142 66 view .LVU259 871 0184 A3FB0152 umull r5, r2, r3, r1 872 0188 D208 lsrs r2, r2, #3 873 018a 02EB8202 add r2, r2, r2, lsl #2 874 018e A1EB4202 sub r2, r1, r2, lsl #1 142:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 8] = (ADC_proc_shadow.avg / 10) % 10 + '0'; 875 .loc 1 142 71 view .LVU260 876 0192 3032 adds r2, r2, #48 142:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 8] = (ADC_proc_shadow.avg / 10) % 10 + '0'; 877 .loc 1 142 36 view .LVU261 878 0194 C276 strb r2, [r0, #27] 143:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 9] = (ADC_proc_shadow.avg / 1) % 10 + '0'; 879 .loc 1 143 7 is_stmt 1 view .LVU262 143:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 9] = (ADC_proc_shadow.avg / 1) % 10 + '0'; 880 .loc 1 143 59 is_stmt 0 view .LVU263 881 0196 A3FB0412 umull r1, r2, r3, r4 882 019a D208 lsrs r2, r2, #3 143:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 9] = (ADC_proc_shadow.avg / 1) % 10 + '0'; 883 .loc 1 143 65 view .LVU264 884 019c A3FB0213 umull r1, r3, r3, r2 885 01a0 DB08 lsrs r3, r3, #3 886 01a2 03EB8303 add r3, r3, r3, lsl #2 887 01a6 A2EB4303 sub r3, r2, r3, lsl #1 143:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 9] = (ADC_proc_shadow.avg / 1) % 10 + '0'; 888 .loc 1 143 70 view .LVU265 889 01aa 3033 adds r3, r3, #48 143:Core/Src/main.c **** ADC_msg[ADC_msg_val_pos + 9] = (ADC_proc_shadow.avg / 1) % 10 + '0'; 890 .loc 1 143 36 view .LVU266 891 01ac 0377 strb r3, [r0, #28] 144:Core/Src/main.c **** CDC_Transmit_FS((uint8_t *)ADC_msg, ADC_msg_len); 892 .loc 1 144 7 is_stmt 1 view .LVU267 144:Core/Src/main.c **** CDC_Transmit_FS((uint8_t *)ADC_msg, ADC_msg_len); 893 .loc 1 144 64 is_stmt 0 view .LVU268 894 01ae 02EB8202 add r2, r2, r2, lsl #2 895 01b2 A4EB4204 sub r4, r4, r2, lsl #1 144:Core/Src/main.c **** CDC_Transmit_FS((uint8_t *)ADC_msg, ADC_msg_len); 896 .loc 1 144 69 view .LVU269 897 01b6 3034 adds r4, r4, #48 144:Core/Src/main.c **** CDC_Transmit_FS((uint8_t *)ADC_msg, ADC_msg_len); 898 .loc 1 144 36 view .LVU270 899 01b8 4477 strb r4, [r0, #29] 145:Core/Src/main.c **** 900 .loc 1 145 7 is_stmt 1 view .LVU271 ARM GAS /tmp/ccWJ27fo.s page 43 901 01ba 2021 movs r1, #32 902 01bc FFF7FEFF bl CDC_Transmit_FS 903 .LVL31: 904 01c0 40E7 b .L28 905 .L33: 906 01c2 00BFAFF3 .align 3 906 0080 907 .L32: 908 01c8 00E40B54 .word 1410065408 909 01cc 02000000 .word 2 910 01d0 00040240 .word 1073873920 911 01d4 00000000 .word ADC1_buff_circular 912 01d8 00000000 .word hadc1 913 01dc 00000000 .word ADC_proc_shadow 914 01e0 00000000 .word ADC_proc 915 01e4 CDCCCCCC .word -858993459 916 01e8 00000000 .word ADC_msg 917 01ec 834B0400 .word 281475 918 01f0 6BCA5F6B .word 1801439851 919 01f4 83DE1B43 .word 1125899907 920 01f8 C55A7C0A .word 175921861 921 01fc 5917B7D1 .word -776530087 922 0200 D34D6210 .word 274877907 923 0204 1F85EB51 .word 1374389535 924 .LBE14: 925 .cfi_endproc 926 .LFE243: 928 .global ADC_msg 929 .section .data.ADC_msg,"aw" 930 .align 2 933 ADC_msg: 934 0000 52656365 .ascii "Received ADC value: ??????????\015\012\000" 934 69766564 934 20414443 934 2076616C 934 75653A20 935 .global ADC1_buff_circular 936 .section .bss.ADC1_buff_circular,"aw",%nobits 937 .align 2 940 ADC1_buff_circular: 941 0000 00000000 .space 200 941 00000000 941 00000000 941 00000000 941 00000000 942 .global Sweep_state 943 .section .bss.Sweep_state,"aw",%nobits 944 .align 2 947 Sweep_state: 948 0000 00000000 .space 12 948 00000000 948 00000000 949 .global ADC_proc_shadow 950 .section .bss.ADC_proc_shadow,"aw",%nobits 951 .align 2 954 ADC_proc_shadow: 955 0000 00000000 .space 16 ARM GAS /tmp/ccWJ27fo.s page 44 955 00000000 955 00000000 955 00000000 956 .global ADC_proc 957 .section .bss.ADC_proc,"aw",%nobits 958 .align 2 961 ADC_proc: 962 0000 00000000 .space 16 962 00000000 962 00000000 962 00000000 963 .global hdma_adc1 964 .section .bss.hdma_adc1,"aw",%nobits 965 .align 2 968 hdma_adc1: 969 0000 00000000 .space 96 969 00000000 969 00000000 969 00000000 969 00000000 970 .global hadc1 971 .section .bss.hadc1,"aw",%nobits 972 .align 2 975 hadc1: 976 0000 00000000 .space 72 976 00000000 976 00000000 976 00000000 976 00000000 977 .global curr_step_start_N 978 .section .bss.curr_step_start_N,"aw",%nobits 979 .align 2 982 curr_step_start_N: 983 0000 00000000 .space 4 984 .text 985 .Letext0: 986 .file 3 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h" 987 .file 4 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" 988 .file 5 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" 989 .file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h" 990 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h" 991 .file 8 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h" 992 .file 9 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h" 993 .file 10 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h" 994 .file 11 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h" 995 .file 12 "Core/Inc/main.h" 996 .file 13 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h" 997 .file 14 "USB_DEVICE/App/usb_device.h" 998 .file 15 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h" 999 .file 16 "" ARM GAS /tmp/ccWJ27fo.s page 45 DEFINED SYMBOLS *ABS*:00000000 main.c /tmp/ccWJ27fo.s:21 .text.MX_GPIO_Init:00000000 $t /tmp/ccWJ27fo.s:26 .text.MX_GPIO_Init:00000000 MX_GPIO_Init /tmp/ccWJ27fo.s:242 .text.MX_GPIO_Init:0000010c $d /tmp/ccWJ27fo.s:250 .text.MX_DMA_Init:00000000 $t /tmp/ccWJ27fo.s:255 .text.MX_DMA_Init:00000000 MX_DMA_Init /tmp/ccWJ27fo.s:304 .text.MX_DMA_Init:00000030 $d /tmp/ccWJ27fo.s:309 .text.Error_Handler:00000000 $t /tmp/ccWJ27fo.s:315 .text.Error_Handler:00000000 Error_Handler /tmp/ccWJ27fo.s:347 .text.MX_ADC1_Init:00000000 $t /tmp/ccWJ27fo.s:352 .text.MX_ADC1_Init:00000000 MX_ADC1_Init /tmp/ccWJ27fo.s:460 .text.MX_ADC1_Init:00000068 $d /tmp/ccWJ27fo.s:975 .bss.hadc1:00000000 hadc1 /tmp/ccWJ27fo.s:466 .text.SystemClock_Config:00000000 $t /tmp/ccWJ27fo.s:472 .text.SystemClock_Config:00000000 SystemClock_Config /tmp/ccWJ27fo.s:620 .text.SystemClock_Config:000000a4 $d /tmp/ccWJ27fo.s:627 .text.main:00000000 $t /tmp/ccWJ27fo.s:633 .text.main:00000000 main /tmp/ccWJ27fo.s:908 .text.main:000001c8 $d /tmp/ccWJ27fo.s:940 .bss.ADC1_buff_circular:00000000 ADC1_buff_circular /tmp/ccWJ27fo.s:954 .bss.ADC_proc_shadow:00000000 ADC_proc_shadow /tmp/ccWJ27fo.s:961 .bss.ADC_proc:00000000 ADC_proc /tmp/ccWJ27fo.s:933 .data.ADC_msg:00000000 ADC_msg /tmp/ccWJ27fo.s:930 .data.ADC_msg:00000000 $d /tmp/ccWJ27fo.s:937 .bss.ADC1_buff_circular:00000000 $d /tmp/ccWJ27fo.s:947 .bss.Sweep_state:00000000 Sweep_state /tmp/ccWJ27fo.s:944 .bss.Sweep_state:00000000 $d /tmp/ccWJ27fo.s:951 .bss.ADC_proc_shadow:00000000 $d /tmp/ccWJ27fo.s:958 .bss.ADC_proc:00000000 $d /tmp/ccWJ27fo.s:968 .bss.hdma_adc1:00000000 hdma_adc1 /tmp/ccWJ27fo.s:965 .bss.hdma_adc1:00000000 $d /tmp/ccWJ27fo.s:972 .bss.hadc1:00000000 $d /tmp/ccWJ27fo.s:982 .bss.curr_step_start_N:00000000 curr_step_start_N /tmp/ccWJ27fo.s:979 .bss.curr_step_start_N:00000000 $d UNDEFINED SYMBOLS HAL_GPIO_WritePin HAL_GPIO_Init HAL_NVIC_SetPriority HAL_NVIC_EnableIRQ HAL_ADC_Init HAL_ADC_ConfigChannel memset HAL_RCC_OscConfig HAL_RCC_ClockConfig __aeabi_ldivmod HAL_Init MX_USB_DEVICE_Init HAL_ADC_Start_DMA HAL_GPIO_TogglePin CDC_Transmit_FS