What I changed
- Core/Inc/main.h:76
- Set ADC_BUFF_SIZE from 50 to 64 so each half is even (32). This keeps the “i &
1” parity consistent across half-buffer boundaries.
- Core/Src/stm32f4xx_it.c:388
- Fixed N after splitting the first half: ADC_proc.N = (ADC_BUFF_SIZE/2 -
Sweep_state.curr_step_start_DMA_N)/2;
- Previously it used (Sweep_state.curr_step_start_DMA_N)/2, which was wrong for
that segment.
Why this helps
- With ADC_BUFF_SIZE=50, half-size is 25 (odd). That flips ON/OFF labeling each half
because i & 1 parity shifts by 25, mixing levels and driving avg_ON and avg_OFF
together.
- The N bug skewed normalization, further flattening differences between averages.
How to verify
- Build and flash: make && make flash.
- Observe avg_ON/avg_OFF over CDC. They should now differ consistently; inverting
meандр should swap them cleanly.
- If still needed, I can add a global sample counter (sample_seq) for fully robust
ON/OFF classification without relying on buffer indices.
What I changed
- Core/Inc/main.h:76
- Set ADC_BUFF_SIZE from 50 to 64 so each half is even (32). This keeps the “i &
1” parity consistent across half-buffer boundaries.
- Core/Src/stm32f4xx_it.c:388
- Fixed N after splitting the first half: ADC_proc.N = (ADC_BUFF_SIZE/2 -
Sweep_state.curr_step_start_DMA_N)/2;
- Previously it used (Sweep_state.curr_step_start_DMA_N)/2, which was wrong for
that segment.
Why this helps
- With ADC_BUFF_SIZE=50, half-size is 25 (odd). That flips ON/OFF labeling each half
because i & 1 parity shifts by 25, mixing levels and driving avg_ON and avg_OFF
together.
- The N bug skewed normalization, further flattening differences between averages.
How to verify
- Build and flash: make && make flash.
- Observe avg_ON/avg_OFF over CDC. They should now differ consistently; inverting
meандр should swap them cleanly.
- If still needed, I can add a global sample counter (sample_seq) for fully robust
ON/OFF classification without relying on buffer indices.
