From d0ef88b6b944d692b1528c2cb0d240786e0abd18 Mon Sep 17 00:00:00 2001 From: Theodor Chikin Date: Thu, 18 Dec 2025 20:03:14 +0300 Subject: [PATCH] implemented DMA-based averager. Avg res is dumped to USB_VCP. But it is not compiles --- Core/Src/main.c | 37 + Core/Src/stm32f4xx_it.c | 12 +- build/main.lst | 1877 +++++++++++++++++++++++---------------- build/main.o | Bin 19536 -> 20912 bytes 4 files changed, 1174 insertions(+), 752 deletions(-) diff --git a/Core/Src/main.c b/Core/Src/main.c index c2df412..50b5756 100644 --- a/Core/Src/main.c +++ b/Core/Src/main.c @@ -59,6 +59,14 @@ static void MX_ADC1_Init(void); /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ +struct ADC_proc{ + uint8_t status; // 0 - stopped, 1 - started-filling, 2 - filled + uint32_t sum; + uint32_t avg; + uint32_t N; +} adc_process; + + #define ADC_BUFF_SIZE 100 uint16_t ADC1_buff_circular[ADC_BUFF_SIZE]; /* USER CODE END 0 */ @@ -98,6 +106,11 @@ int main(void) /* USER CODE BEGIN 2 */ HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_SET); HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADC1_buff_circular, ADC_BUFF_SIZE); + adc_process.status = 0; // ADC started + adc_process.N = 0; + adc_process.sum = 0; + adc_process.avg = 0; + /* USER CODE END 2 */ /* Infinite loop */ @@ -106,7 +119,31 @@ int main(void) { HAL_GPIO_TogglePin(LED_RED_GPIO_Port, LED_RED_Pin); HAL_Delay(100); + + if (adc_process.status == 2) { + adc_process.avg = adc_process.sum / adc_process.N; + adc_process.status = 1; // reset for next accumulation + adc_process.sum = 0; + adc_process.N = 0; + char digits[10] = {0}; + digits[0] = (adc_process.avg / 1000000000) % 10 + '0'; + digits[1] = (adc_process.avg / 100000000) % 10 + '0'; + digits[2] = (adc_process.avg / 10000000) % 10 + '0'; + digits[3] = (adc_process.avg / 1000000) % 10 + '0'; + digits[4] = (adc_process.avg / 100000) % 10 + '0'; + digits[5] = (adc_process.avg / 10000) % 10 + '0'; + digits[6] = (adc_process.avg / 1000) % 10 + '0'; + digits[7] = (adc_process.avg / 100) % 10 + '0'; + digits[8] = (adc_process.avg / 10) % 10 + '0'; + digits[9] = (adc_process.avg / 1) % 10 + '0'; + + CDC_Transmit_FS((uint8_t *)"ADC Average calculated: ", 24); + CDC_Transmit_FS((uint8_t *)digits, 10); + CDC_Transmit_FS((uint8_t *)"\r\n", 2); + + } CDC_Transmit_FS((uint8_t *)"Hello from STM32!\r\n", 19); + /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ diff --git a/Core/Src/stm32f4xx_it.c b/Core/Src/stm32f4xx_it.c index ccb711b..a9dc560 100644 --- a/Core/Src/stm32f4xx_it.c +++ b/Core/Src/stm32f4xx_it.c @@ -58,7 +58,7 @@ extern PCD_HandleTypeDef hpcd_USB_OTG_FS; extern DMA_HandleTypeDef hdma_adc1; /* USER CODE BEGIN EV */ - +extern struct ADC_proc adc_process; /* USER CODE END EV */ /******************************************************************************/ @@ -232,6 +232,11 @@ void OTG_FS_IRQHandler(void) void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) { HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_SET); + for (uint32_t i = ADC_BUFF_SIZE/2; i < ADC_BUFF_SIZE; i++) { + adc_process.sum += ADC1_buff_circular[i]; + } + adc_process.N += ADC_BUFF_SIZE - ADC_BUFF_SIZE/2; + adc_process.status = 2; // buffer filled // This function is called when the first half of the ADC buffer is filled // You can process the first half of ADC1_buff_circular here } @@ -243,6 +248,11 @@ void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) //HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_RESET); HAL_GPIO_TogglePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin); + for (uint32_t i = 0; i < ADC_BUFF_SIZE/2; i++) { + adc_process.sum += ADC1_buff_circular[i]; + } + adc_process.N += ADC_BUFF_SIZE/2; + // This function is called when the first half of the ADC buffer is filled // You can process the first half of ADC1_buff_circular here } diff --git a/build/main.lst b/build/main.lst index b25a012..ce14ea9 100644 --- a/build/main.lst +++ b/build/main.lst @@ -1,4 +1,4 @@ -ARM GAS /tmp/cchXeloq.s page 1 +ARM GAS /tmp/ccYDS01w.s page 1 1 .cpu cortex-m4 @@ -58,7 +58,7 @@ ARM GAS /tmp/cchXeloq.s page 1 29:Core/Src/main.c **** /* USER CODE BEGIN PTD */ 30:Core/Src/main.c **** 31:Core/Src/main.c **** /* USER CODE END PTD */ - ARM GAS /tmp/cchXeloq.s page 2 + ARM GAS /tmp/ccYDS01w.s page 2 32:Core/Src/main.c **** @@ -91,191 +91,231 @@ ARM GAS /tmp/cchXeloq.s page 1 59:Core/Src/main.c **** 60:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/ 61:Core/Src/main.c **** /* USER CODE BEGIN 0 */ - 62:Core/Src/main.c **** #define ADC_BUFF_SIZE 100 - 63:Core/Src/main.c **** uint16_t ADC1_buff_circular[ADC_BUFF_SIZE]; - 64:Core/Src/main.c **** /* USER CODE END 0 */ - 65:Core/Src/main.c **** - 66:Core/Src/main.c **** /** - 67:Core/Src/main.c **** * @brief The application entry point. - 68:Core/Src/main.c **** * @retval int - 69:Core/Src/main.c **** */ - 70:Core/Src/main.c **** int main(void) - 71:Core/Src/main.c **** { - 72:Core/Src/main.c **** - 73:Core/Src/main.c **** /* USER CODE BEGIN 1 */ - 74:Core/Src/main.c **** - 75:Core/Src/main.c **** /* USER CODE END 1 */ - 76:Core/Src/main.c **** - 77:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ - 78:Core/Src/main.c **** - 79:Core/Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - 80:Core/Src/main.c **** HAL_Init(); - 81:Core/Src/main.c **** - 82:Core/Src/main.c **** /* USER CODE BEGIN Init */ - 83:Core/Src/main.c **** - 84:Core/Src/main.c **** /* USER CODE END Init */ - 85:Core/Src/main.c **** - 86:Core/Src/main.c **** /* Configure the system clock */ - 87:Core/Src/main.c **** SystemClock_Config(); - 88:Core/Src/main.c **** - ARM GAS /tmp/cchXeloq.s page 3 + 62:Core/Src/main.c **** struct ADC_proc{ + 63:Core/Src/main.c **** uint8_t status; // 0 - stopped, 1 - started-filling, 2 - filled + 64:Core/Src/main.c **** uint32_t sum; + 65:Core/Src/main.c **** uint32_t avg; + 66:Core/Src/main.c **** uint32_t N; + 67:Core/Src/main.c **** } adc_process; + 68:Core/Src/main.c **** + 69:Core/Src/main.c **** + 70:Core/Src/main.c **** #define ADC_BUFF_SIZE 100 + 71:Core/Src/main.c **** uint16_t ADC1_buff_circular[ADC_BUFF_SIZE]; + 72:Core/Src/main.c **** /* USER CODE END 0 */ + 73:Core/Src/main.c **** + 74:Core/Src/main.c **** /** + 75:Core/Src/main.c **** * @brief The application entry point. + 76:Core/Src/main.c **** * @retval int + 77:Core/Src/main.c **** */ + 78:Core/Src/main.c **** int main(void) + 79:Core/Src/main.c **** { + 80:Core/Src/main.c **** + 81:Core/Src/main.c **** /* USER CODE BEGIN 1 */ + 82:Core/Src/main.c **** + 83:Core/Src/main.c **** /* USER CODE END 1 */ + 84:Core/Src/main.c **** + 85:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ + 86:Core/Src/main.c **** + 87:Core/Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + 88:Core/Src/main.c **** HAL_Init(); + ARM GAS /tmp/ccYDS01w.s page 3 - 89:Core/Src/main.c **** /* USER CODE BEGIN SysInit */ - 90:Core/Src/main.c **** - 91:Core/Src/main.c **** /* USER CODE END SysInit */ - 92:Core/Src/main.c **** - 93:Core/Src/main.c **** /* Initialize all configured peripherals */ - 94:Core/Src/main.c **** MX_GPIO_Init(); - 95:Core/Src/main.c **** MX_DMA_Init(); - 96:Core/Src/main.c **** MX_ADC1_Init(); - 97:Core/Src/main.c **** MX_USB_DEVICE_Init(); - 98:Core/Src/main.c **** /* USER CODE BEGIN 2 */ - 99:Core/Src/main.c **** HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_SET); - 100:Core/Src/main.c **** HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADC1_buff_circular, ADC_BUFF_SIZE); - 101:Core/Src/main.c **** /* USER CODE END 2 */ - 102:Core/Src/main.c **** - 103:Core/Src/main.c **** /* Infinite loop */ - 104:Core/Src/main.c **** /* USER CODE BEGIN WHILE */ - 105:Core/Src/main.c **** while (1) - 106:Core/Src/main.c **** { - 107:Core/Src/main.c **** HAL_GPIO_TogglePin(LED_RED_GPIO_Port, LED_RED_Pin); - 108:Core/Src/main.c **** HAL_Delay(100); - 109:Core/Src/main.c **** CDC_Transmit_FS((uint8_t *)"Hello from STM32!\r\n", 19); - 110:Core/Src/main.c **** /* USER CODE END WHILE */ - 111:Core/Src/main.c **** - 112:Core/Src/main.c **** /* USER CODE BEGIN 3 */ - 113:Core/Src/main.c **** } - 114:Core/Src/main.c **** /* USER CODE END 3 */ - 115:Core/Src/main.c **** } - 116:Core/Src/main.c **** - 117:Core/Src/main.c **** /** - 118:Core/Src/main.c **** * @brief System Clock Configuration - 119:Core/Src/main.c **** * @retval None - 120:Core/Src/main.c **** */ - 121:Core/Src/main.c **** void SystemClock_Config(void) - 122:Core/Src/main.c **** { - 123:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - 124:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - 125:Core/Src/main.c **** - 126:Core/Src/main.c **** /** Configure the main internal regulator output voltage - 127:Core/Src/main.c **** */ - 128:Core/Src/main.c **** __HAL_RCC_PWR_CLK_ENABLE(); - 129:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - 130:Core/Src/main.c **** - 131:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters - 132:Core/Src/main.c **** * in the RCC_OscInitTypeDef structure. - 133:Core/Src/main.c **** */ - 134:Core/Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - 135:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; - 136:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - 137:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - 138:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 8; - 139:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 336; - 140:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - 141:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 7; - 142:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - 143:Core/Src/main.c **** { - 144:Core/Src/main.c **** Error_Handler(); - 145:Core/Src/main.c **** } - ARM GAS /tmp/cchXeloq.s page 4 + 89:Core/Src/main.c **** + 90:Core/Src/main.c **** /* USER CODE BEGIN Init */ + 91:Core/Src/main.c **** + 92:Core/Src/main.c **** /* USER CODE END Init */ + 93:Core/Src/main.c **** + 94:Core/Src/main.c **** /* Configure the system clock */ + 95:Core/Src/main.c **** SystemClock_Config(); + 96:Core/Src/main.c **** + 97:Core/Src/main.c **** /* USER CODE BEGIN SysInit */ + 98:Core/Src/main.c **** + 99:Core/Src/main.c **** /* USER CODE END SysInit */ + 100:Core/Src/main.c **** + 101:Core/Src/main.c **** /* Initialize all configured peripherals */ + 102:Core/Src/main.c **** MX_GPIO_Init(); + 103:Core/Src/main.c **** MX_DMA_Init(); + 104:Core/Src/main.c **** MX_ADC1_Init(); + 105:Core/Src/main.c **** MX_USB_DEVICE_Init(); + 106:Core/Src/main.c **** /* USER CODE BEGIN 2 */ + 107:Core/Src/main.c **** HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_SET); + 108:Core/Src/main.c **** HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADC1_buff_circular, ADC_BUFF_SIZE); + 109:Core/Src/main.c **** adc_process.status = 0; // ADC started + 110:Core/Src/main.c **** adc_process.N = 0; + 111:Core/Src/main.c **** adc_process.sum = 0; + 112:Core/Src/main.c **** adc_process.avg = 0; + 113:Core/Src/main.c **** + 114:Core/Src/main.c **** /* USER CODE END 2 */ + 115:Core/Src/main.c **** + 116:Core/Src/main.c **** /* Infinite loop */ + 117:Core/Src/main.c **** /* USER CODE BEGIN WHILE */ + 118:Core/Src/main.c **** while (1) + 119:Core/Src/main.c **** { + 120:Core/Src/main.c **** HAL_GPIO_TogglePin(LED_RED_GPIO_Port, LED_RED_Pin); + 121:Core/Src/main.c **** HAL_Delay(100); + 122:Core/Src/main.c **** + 123:Core/Src/main.c **** if (adc_process.status == 2) { + 124:Core/Src/main.c **** adc_process.avg = adc_process.sum / adc_process.N; + 125:Core/Src/main.c **** adc_process.status = 1; // reset for next accumulation + 126:Core/Src/main.c **** adc_process.sum = 0; + 127:Core/Src/main.c **** adc_process.N = 0; + 128:Core/Src/main.c **** char digits[10] = {0}; + 129:Core/Src/main.c **** digits[0] = (adc_process.avg / 1000000000) % 10 + '0'; + 130:Core/Src/main.c **** digits[1] = (adc_process.avg / 100000000) % 10 + '0'; + 131:Core/Src/main.c **** digits[2] = (adc_process.avg / 10000000) % 10 + '0'; + 132:Core/Src/main.c **** digits[3] = (adc_process.avg / 1000000) % 10 + '0'; + 133:Core/Src/main.c **** digits[4] = (adc_process.avg / 100000) % 10 + '0'; + 134:Core/Src/main.c **** digits[5] = (adc_process.avg / 10000) % 10 + '0'; + 135:Core/Src/main.c **** digits[6] = (adc_process.avg / 1000) % 10 + '0'; + 136:Core/Src/main.c **** digits[7] = (adc_process.avg / 100) % 10 + '0'; + 137:Core/Src/main.c **** digits[8] = (adc_process.avg / 10) % 10 + '0'; + 138:Core/Src/main.c **** digits[9] = (adc_process.avg / 1) % 10 + '0'; + 139:Core/Src/main.c **** + 140:Core/Src/main.c **** CDC_Transmit_FS((uint8_t *)"ADC Average calculated: ", 24); + 141:Core/Src/main.c **** CDC_Transmit_FS((uint8_t *)digits, 10); + 142:Core/Src/main.c **** CDC_Transmit_FS((uint8_t *)"\r\n", 2); + 143:Core/Src/main.c **** + 144:Core/Src/main.c **** } + 145:Core/Src/main.c **** CDC_Transmit_FS((uint8_t *)"Hello from STM32!\r\n", 19); + ARM GAS /tmp/ccYDS01w.s page 4 - 146:Core/Src/main.c **** - 147:Core/Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks - 148:Core/Src/main.c **** */ - 149:Core/Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - 150:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - 151:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - 152:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - 153:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - 154:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - 155:Core/Src/main.c **** - 156:Core/Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) - 157:Core/Src/main.c **** { - 158:Core/Src/main.c **** Error_Handler(); - 159:Core/Src/main.c **** } - 160:Core/Src/main.c **** } - 161:Core/Src/main.c **** - 162:Core/Src/main.c **** /** - 163:Core/Src/main.c **** * @brief ADC1 Initialization Function - 164:Core/Src/main.c **** * @param None - 165:Core/Src/main.c **** * @retval None - 166:Core/Src/main.c **** */ - 167:Core/Src/main.c **** static void MX_ADC1_Init(void) - 168:Core/Src/main.c **** { - 169:Core/Src/main.c **** - 170:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 0 */ - 171:Core/Src/main.c **** - 172:Core/Src/main.c **** /* USER CODE END ADC1_Init 0 */ - 173:Core/Src/main.c **** - 174:Core/Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0}; - 175:Core/Src/main.c **** - 176:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 1 */ - 177:Core/Src/main.c **** - 178:Core/Src/main.c **** /* USER CODE END ADC1_Init 1 */ - 179:Core/Src/main.c **** - 180:Core/Src/main.c **** /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of con - 181:Core/Src/main.c **** */ - 182:Core/Src/main.c **** hadc1.Instance = ADC1; - 183:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; - 184:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; - 185:Core/Src/main.c **** hadc1.Init.ScanConvMode = DISABLE; - 186:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; - 187:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; - 188:Core/Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; - 189:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_Ext_IT11; - 190:Core/Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; - 191:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1; - 192:Core/Src/main.c **** hadc1.Init.DMAContinuousRequests = ENABLE; - 193:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; - 194:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) - 195:Core/Src/main.c **** { - 196:Core/Src/main.c **** Error_Handler(); - 197:Core/Src/main.c **** } + 146:Core/Src/main.c **** + 147:Core/Src/main.c **** /* USER CODE END WHILE */ + 148:Core/Src/main.c **** + 149:Core/Src/main.c **** /* USER CODE BEGIN 3 */ + 150:Core/Src/main.c **** } + 151:Core/Src/main.c **** /* USER CODE END 3 */ + 152:Core/Src/main.c **** } + 153:Core/Src/main.c **** + 154:Core/Src/main.c **** /** + 155:Core/Src/main.c **** * @brief System Clock Configuration + 156:Core/Src/main.c **** * @retval None + 157:Core/Src/main.c **** */ + 158:Core/Src/main.c **** void SystemClock_Config(void) + 159:Core/Src/main.c **** { + 160:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 161:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 162:Core/Src/main.c **** + 163:Core/Src/main.c **** /** Configure the main internal regulator output voltage + 164:Core/Src/main.c **** */ + 165:Core/Src/main.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 166:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 167:Core/Src/main.c **** + 168:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters + 169:Core/Src/main.c **** * in the RCC_OscInitTypeDef structure. + 170:Core/Src/main.c **** */ + 171:Core/Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + 172:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 173:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 174:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + 175:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 8; + 176:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 336; + 177:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + 178:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 7; + 179:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 180:Core/Src/main.c **** { + 181:Core/Src/main.c **** Error_Handler(); + 182:Core/Src/main.c **** } + 183:Core/Src/main.c **** + 184:Core/Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks + 185:Core/Src/main.c **** */ + 186:Core/Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 187:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + 188:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + 189:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 190:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + 191:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + 192:Core/Src/main.c **** + 193:Core/Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + 194:Core/Src/main.c **** { + 195:Core/Src/main.c **** Error_Handler(); + 196:Core/Src/main.c **** } + 197:Core/Src/main.c **** } 198:Core/Src/main.c **** - 199:Core/Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it - 200:Core/Src/main.c **** */ - 201:Core/Src/main.c **** sConfig.Channel = ADC_CHANNEL_3; - 202:Core/Src/main.c **** sConfig.Rank = 1; - ARM GAS /tmp/cchXeloq.s page 5 + 199:Core/Src/main.c **** /** + 200:Core/Src/main.c **** * @brief ADC1 Initialization Function + 201:Core/Src/main.c **** * @param None + 202:Core/Src/main.c **** * @retval None + ARM GAS /tmp/ccYDS01w.s page 5 - 203:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; - 204:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - 205:Core/Src/main.c **** { - 206:Core/Src/main.c **** Error_Handler(); - 207:Core/Src/main.c **** } - 208:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 2 */ - 209:Core/Src/main.c **** - 210:Core/Src/main.c **** /* USER CODE END ADC1_Init 2 */ - 211:Core/Src/main.c **** - 212:Core/Src/main.c **** } - 213:Core/Src/main.c **** - 214:Core/Src/main.c **** /** - 215:Core/Src/main.c **** * Enable DMA controller clock - 216:Core/Src/main.c **** */ - 217:Core/Src/main.c **** static void MX_DMA_Init(void) - 218:Core/Src/main.c **** { - 219:Core/Src/main.c **** - 220:Core/Src/main.c **** /* DMA controller clock enable */ - 221:Core/Src/main.c **** __HAL_RCC_DMA2_CLK_ENABLE(); - 222:Core/Src/main.c **** - 223:Core/Src/main.c **** /* DMA interrupt init */ - 224:Core/Src/main.c **** /* DMA2_Stream0_IRQn interrupt configuration */ - 225:Core/Src/main.c **** HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 0, 0); - 226:Core/Src/main.c **** HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); - 227:Core/Src/main.c **** - 228:Core/Src/main.c **** } - 229:Core/Src/main.c **** - 230:Core/Src/main.c **** /** - 231:Core/Src/main.c **** * @brief GPIO Initialization Function - 232:Core/Src/main.c **** * @param None - 233:Core/Src/main.c **** * @retval None - 234:Core/Src/main.c **** */ - 235:Core/Src/main.c **** static void MX_GPIO_Init(void) - 236:Core/Src/main.c **** { - 28 .loc 1 236 1 view -0 + 203:Core/Src/main.c **** */ + 204:Core/Src/main.c **** static void MX_ADC1_Init(void) + 205:Core/Src/main.c **** { + 206:Core/Src/main.c **** + 207:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 0 */ + 208:Core/Src/main.c **** + 209:Core/Src/main.c **** /* USER CODE END ADC1_Init 0 */ + 210:Core/Src/main.c **** + 211:Core/Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0}; + 212:Core/Src/main.c **** + 213:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 1 */ + 214:Core/Src/main.c **** + 215:Core/Src/main.c **** /* USER CODE END ADC1_Init 1 */ + 216:Core/Src/main.c **** + 217:Core/Src/main.c **** /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of con + 218:Core/Src/main.c **** */ + 219:Core/Src/main.c **** hadc1.Instance = ADC1; + 220:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; + 221:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; + 222:Core/Src/main.c **** hadc1.Init.ScanConvMode = DISABLE; + 223:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; + 224:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; + 225:Core/Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; + 226:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_Ext_IT11; + 227:Core/Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + 228:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1; + 229:Core/Src/main.c **** hadc1.Init.DMAContinuousRequests = ENABLE; + 230:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + 231:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) + 232:Core/Src/main.c **** { + 233:Core/Src/main.c **** Error_Handler(); + 234:Core/Src/main.c **** } + 235:Core/Src/main.c **** + 236:Core/Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it + 237:Core/Src/main.c **** */ + 238:Core/Src/main.c **** sConfig.Channel = ADC_CHANNEL_3; + 239:Core/Src/main.c **** sConfig.Rank = 1; + 240:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; + 241:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + 242:Core/Src/main.c **** { + 243:Core/Src/main.c **** Error_Handler(); + 244:Core/Src/main.c **** } + 245:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 2 */ + 246:Core/Src/main.c **** + 247:Core/Src/main.c **** /* USER CODE END ADC1_Init 2 */ + 248:Core/Src/main.c **** + 249:Core/Src/main.c **** } + 250:Core/Src/main.c **** + 251:Core/Src/main.c **** /** + 252:Core/Src/main.c **** * Enable DMA controller clock + 253:Core/Src/main.c **** */ + 254:Core/Src/main.c **** static void MX_DMA_Init(void) + 255:Core/Src/main.c **** { + 256:Core/Src/main.c **** + 257:Core/Src/main.c **** /* DMA controller clock enable */ + 258:Core/Src/main.c **** __HAL_RCC_DMA2_CLK_ENABLE(); + 259:Core/Src/main.c **** + ARM GAS /tmp/ccYDS01w.s page 6 + + + 260:Core/Src/main.c **** /* DMA interrupt init */ + 261:Core/Src/main.c **** /* DMA2_Stream0_IRQn interrupt configuration */ + 262:Core/Src/main.c **** HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 0, 0); + 263:Core/Src/main.c **** HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); + 264:Core/Src/main.c **** + 265:Core/Src/main.c **** } + 266:Core/Src/main.c **** + 267:Core/Src/main.c **** /** + 268:Core/Src/main.c **** * @brief GPIO Initialization Function + 269:Core/Src/main.c **** * @param None + 270:Core/Src/main.c **** * @retval None + 271:Core/Src/main.c **** */ + 272:Core/Src/main.c **** static void MX_GPIO_Init(void) + 273:Core/Src/main.c **** { + 28 .loc 1 273 1 view -0 29 .cfi_startproc 30 @ args = 0, pretend = 0, frame = 40 31 @ frame_needed = 0, uses_anonymous_args = 0 @@ -288,188 +328,188 @@ ARM GAS /tmp/cchXeloq.s page 1 38 0002 8BB0 sub sp, sp, #44 39 .LCFI1: 40 .cfi_def_cfa_offset 56 - 237:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; - 41 .loc 1 237 3 view .LVU1 - 42 .loc 1 237 20 is_stmt 0 view .LVU2 + 274:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; + 41 .loc 1 274 3 view .LVU1 + 42 .loc 1 274 20 is_stmt 0 view .LVU2 43 0004 0024 movs r4, #0 44 0006 0594 str r4, [sp, #20] 45 0008 0694 str r4, [sp, #24] 46 000a 0794 str r4, [sp, #28] 47 000c 0894 str r4, [sp, #32] 48 000e 0994 str r4, [sp, #36] - 238:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */ - ARM GAS /tmp/cchXeloq.s page 6 - - - 239:Core/Src/main.c **** - 240:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_1 */ - 241:Core/Src/main.c **** - 242:Core/Src/main.c **** /* GPIO Ports Clock Enable */ - 243:Core/Src/main.c **** __HAL_RCC_GPIOH_CLK_ENABLE(); - 49 .loc 1 243 3 is_stmt 1 view .LVU3 + 275:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */ + 276:Core/Src/main.c **** + 277:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_1 */ + 278:Core/Src/main.c **** + 279:Core/Src/main.c **** /* GPIO Ports Clock Enable */ + 280:Core/Src/main.c **** __HAL_RCC_GPIOH_CLK_ENABLE(); + 49 .loc 1 280 3 is_stmt 1 view .LVU3 50 .LBB4: - 51 .loc 1 243 3 view .LVU4 + 51 .loc 1 280 3 view .LVU4 52 0010 0094 str r4, [sp] - 53 .loc 1 243 3 view .LVU5 + 53 .loc 1 280 3 view .LVU5 54 0012 2B4B ldr r3, .L3 55 0014 1A6B ldr r2, [r3, #48] 56 0016 42F08002 orr r2, r2, #128 57 001a 1A63 str r2, [r3, #48] - 58 .loc 1 243 3 view .LVU6 + 58 .loc 1 280 3 view .LVU6 59 001c 1A6B ldr r2, [r3, #48] 60 001e 02F08002 and r2, r2, #128 61 0022 0092 str r2, [sp] - 62 .loc 1 243 3 view .LVU7 + 62 .loc 1 280 3 view .LVU7 63 0024 009A ldr r2, [sp] + ARM GAS /tmp/ccYDS01w.s page 7 + + 64 .LBE4: - 65 .loc 1 243 3 view .LVU8 - 244:Core/Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); - 66 .loc 1 244 3 view .LVU9 + 65 .loc 1 280 3 view .LVU8 + 281:Core/Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); + 66 .loc 1 281 3 view .LVU9 67 .LBB5: - 68 .loc 1 244 3 view .LVU10 + 68 .loc 1 281 3 view .LVU10 69 0026 0194 str r4, [sp, #4] - 70 .loc 1 244 3 view .LVU11 + 70 .loc 1 281 3 view .LVU11 71 0028 1A6B ldr r2, [r3, #48] 72 002a 42F00402 orr r2, r2, #4 73 002e 1A63 str r2, [r3, #48] - 74 .loc 1 244 3 view .LVU12 + 74 .loc 1 281 3 view .LVU12 75 0030 1A6B ldr r2, [r3, #48] 76 0032 02F00402 and r2, r2, #4 77 0036 0192 str r2, [sp, #4] - 78 .loc 1 244 3 view .LVU13 + 78 .loc 1 281 3 view .LVU13 79 0038 019A ldr r2, [sp, #4] 80 .LBE5: - 81 .loc 1 244 3 view .LVU14 - 245:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); - 82 .loc 1 245 3 view .LVU15 + 81 .loc 1 281 3 view .LVU14 + 282:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 82 .loc 1 282 3 view .LVU15 83 .LBB6: - 84 .loc 1 245 3 view .LVU16 + 84 .loc 1 282 3 view .LVU16 85 003a 0294 str r4, [sp, #8] - 86 .loc 1 245 3 view .LVU17 + 86 .loc 1 282 3 view .LVU17 87 003c 1A6B ldr r2, [r3, #48] 88 003e 42F00102 orr r2, r2, #1 89 0042 1A63 str r2, [r3, #48] - 90 .loc 1 245 3 view .LVU18 + 90 .loc 1 282 3 view .LVU18 91 0044 1A6B ldr r2, [r3, #48] 92 0046 02F00102 and r2, r2, #1 93 004a 0292 str r2, [sp, #8] - 94 .loc 1 245 3 view .LVU19 + 94 .loc 1 282 3 view .LVU19 95 004c 029A ldr r2, [sp, #8] 96 .LBE6: - 97 .loc 1 245 3 view .LVU20 - 246:Core/Src/main.c **** __HAL_RCC_GPIOF_CLK_ENABLE(); - ARM GAS /tmp/cchXeloq.s page 7 - - - 98 .loc 1 246 3 view .LVU21 + 97 .loc 1 282 3 view .LVU20 + 283:Core/Src/main.c **** __HAL_RCC_GPIOF_CLK_ENABLE(); + 98 .loc 1 283 3 view .LVU21 99 .LBB7: - 100 .loc 1 246 3 view .LVU22 + 100 .loc 1 283 3 view .LVU22 101 004e 0394 str r4, [sp, #12] - 102 .loc 1 246 3 view .LVU23 + 102 .loc 1 283 3 view .LVU23 103 0050 1A6B ldr r2, [r3, #48] 104 0052 42F02002 orr r2, r2, #32 105 0056 1A63 str r2, [r3, #48] - 106 .loc 1 246 3 view .LVU24 + 106 .loc 1 283 3 view .LVU24 107 0058 1A6B ldr r2, [r3, #48] 108 005a 02F02002 and r2, r2, #32 109 005e 0392 str r2, [sp, #12] - 110 .loc 1 246 3 view .LVU25 + 110 .loc 1 283 3 view .LVU25 111 0060 039A ldr r2, [sp, #12] 112 .LBE7: - 113 .loc 1 246 3 view .LVU26 - 247:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); - 114 .loc 1 247 3 view .LVU27 + 113 .loc 1 283 3 view .LVU26 + 284:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 114 .loc 1 284 3 view .LVU27 115 .LBB8: - 116 .loc 1 247 3 view .LVU28 + 116 .loc 1 284 3 view .LVU28 + ARM GAS /tmp/ccYDS01w.s page 8 + + 117 0062 0494 str r4, [sp, #16] - 118 .loc 1 247 3 view .LVU29 + 118 .loc 1 284 3 view .LVU29 119 0064 1A6B ldr r2, [r3, #48] 120 0066 42F00202 orr r2, r2, #2 121 006a 1A63 str r2, [r3, #48] - 122 .loc 1 247 3 view .LVU30 + 122 .loc 1 284 3 view .LVU30 123 006c 1B6B ldr r3, [r3, #48] 124 006e 03F00203 and r3, r3, #2 125 0072 0493 str r3, [sp, #16] - 126 .loc 1 247 3 view .LVU31 + 126 .loc 1 284 3 view .LVU31 127 0074 049B ldr r3, [sp, #16] 128 .LBE8: - 129 .loc 1 247 3 view .LVU32 - 248:Core/Src/main.c **** - 249:Core/Src/main.c **** /*Configure GPIO pin Output Level */ - 250:Core/Src/main.c **** HAL_GPIO_WritePin(LED_RED_GPIO_Port, LED_RED_Pin, GPIO_PIN_RESET); - 130 .loc 1 250 3 view .LVU33 + 129 .loc 1 284 3 view .LVU32 + 285:Core/Src/main.c **** + 286:Core/Src/main.c **** /*Configure GPIO pin Output Level */ + 287:Core/Src/main.c **** HAL_GPIO_WritePin(LED_RED_GPIO_Port, LED_RED_Pin, GPIO_PIN_RESET); + 130 .loc 1 287 3 view .LVU33 131 0076 134D ldr r5, .L3+4 132 0078 2246 mov r2, r4 133 007a 4FF48041 mov r1, #16384 134 007e 2846 mov r0, r5 135 0080 FFF7FEFF bl HAL_GPIO_WritePin 136 .LVL0: - 251:Core/Src/main.c **** - 252:Core/Src/main.c **** /*Configure GPIO pin Output Level */ - 253:Core/Src/main.c **** HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_SET); - 137 .loc 1 253 3 view .LVU34 + 288:Core/Src/main.c **** + 289:Core/Src/main.c **** /*Configure GPIO pin Output Level */ + 290:Core/Src/main.c **** HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_SET); + 137 .loc 1 290 3 view .LVU34 138 0084 0122 movs r2, #1 139 0086 8021 movs r1, #128 140 0088 2846 mov r0, r5 141 008a FFF7FEFF bl HAL_GPIO_WritePin 142 .LVL1: - 254:Core/Src/main.c **** - 255:Core/Src/main.c **** /*Configure GPIO pin : PF11 */ - 256:Core/Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_11; - 143 .loc 1 256 3 view .LVU35 - 144 .loc 1 256 23 is_stmt 0 view .LVU36 - ARM GAS /tmp/cchXeloq.s page 8 - - + 291:Core/Src/main.c **** + 292:Core/Src/main.c **** /*Configure GPIO pin : PF11 */ + 293:Core/Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_11; + 143 .loc 1 293 3 view .LVU35 + 144 .loc 1 293 23 is_stmt 0 view .LVU36 145 008e 4FF40063 mov r3, #2048 146 0092 0593 str r3, [sp, #20] - 257:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; - 147 .loc 1 257 3 is_stmt 1 view .LVU37 - 148 .loc 1 257 24 is_stmt 0 view .LVU38 + 294:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + 147 .loc 1 294 3 is_stmt 1 view .LVU37 + 148 .loc 1 294 24 is_stmt 0 view .LVU38 149 0094 4FF48813 mov r3, #1114112 150 0098 0693 str r3, [sp, #24] - 258:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; - 151 .loc 1 258 3 is_stmt 1 view .LVU39 - 152 .loc 1 258 24 is_stmt 0 view .LVU40 + 295:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 151 .loc 1 295 3 is_stmt 1 view .LVU39 + 152 .loc 1 295 24 is_stmt 0 view .LVU40 153 009a 0794 str r4, [sp, #28] - 259:Core/Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - 154 .loc 1 259 3 is_stmt 1 view .LVU41 + 296:Core/Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + 154 .loc 1 296 3 is_stmt 1 view .LVU41 155 009c 05A9 add r1, sp, #20 156 009e 0A48 ldr r0, .L3+8 157 00a0 FFF7FEFF bl HAL_GPIO_Init 158 .LVL2: - 260:Core/Src/main.c **** - 261:Core/Src/main.c **** /*Configure GPIO pins : LED_RED_Pin LED_BLUE_Pin */ - 262:Core/Src/main.c **** GPIO_InitStruct.Pin = LED_RED_Pin|LED_BLUE_Pin; - 159 .loc 1 262 3 view .LVU42 - 160 .loc 1 262 23 is_stmt 0 view .LVU43 + 297:Core/Src/main.c **** + 298:Core/Src/main.c **** /*Configure GPIO pins : LED_RED_Pin LED_BLUE_Pin */ + 299:Core/Src/main.c **** GPIO_InitStruct.Pin = LED_RED_Pin|LED_BLUE_Pin; + ARM GAS /tmp/ccYDS01w.s page 9 + + + 159 .loc 1 299 3 view .LVU42 + 160 .loc 1 299 23 is_stmt 0 view .LVU43 161 00a4 4FF48143 mov r3, #16512 162 00a8 0593 str r3, [sp, #20] - 263:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 163 .loc 1 263 3 is_stmt 1 view .LVU44 - 164 .loc 1 263 24 is_stmt 0 view .LVU45 + 300:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 163 .loc 1 300 3 is_stmt 1 view .LVU44 + 164 .loc 1 300 24 is_stmt 0 view .LVU45 165 00aa 0123 movs r3, #1 166 00ac 0693 str r3, [sp, #24] - 264:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; - 167 .loc 1 264 3 is_stmt 1 view .LVU46 - 168 .loc 1 264 24 is_stmt 0 view .LVU47 + 301:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 167 .loc 1 301 3 is_stmt 1 view .LVU46 + 168 .loc 1 301 24 is_stmt 0 view .LVU47 169 00ae 0794 str r4, [sp, #28] - 265:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 170 .loc 1 265 3 is_stmt 1 view .LVU48 - 171 .loc 1 265 25 is_stmt 0 view .LVU49 + 302:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 170 .loc 1 302 3 is_stmt 1 view .LVU48 + 171 .loc 1 302 25 is_stmt 0 view .LVU49 172 00b0 0894 str r4, [sp, #32] - 266:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - 173 .loc 1 266 3 is_stmt 1 view .LVU50 + 303:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 173 .loc 1 303 3 is_stmt 1 view .LVU50 174 00b2 05A9 add r1, sp, #20 175 00b4 2846 mov r0, r5 176 00b6 FFF7FEFF bl HAL_GPIO_Init 177 .LVL3: - 267:Core/Src/main.c **** - 268:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_2 */ - 269:Core/Src/main.c **** - 270:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_2 */ - 271:Core/Src/main.c **** } - 178 .loc 1 271 1 is_stmt 0 view .LVU51 + 304:Core/Src/main.c **** + 305:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_2 */ + 306:Core/Src/main.c **** + 307:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_2 */ + 308:Core/Src/main.c **** } + 178 .loc 1 308 1 is_stmt 0 view .LVU51 179 00ba 0BB0 add sp, sp, #44 180 .LCFI2: 181 .cfi_def_cfa_offset 12 @@ -478,9 +518,6 @@ ARM GAS /tmp/cchXeloq.s page 1 184 .L4: 185 00be 00BF .align 2 186 .L3: - ARM GAS /tmp/cchXeloq.s page 9 - - 187 00c0 00380240 .word 1073887232 188 00c4 00040240 .word 1073873920 189 00c8 00140240 .word 1073878016 @@ -493,58 +530,58 @@ ARM GAS /tmp/cchXeloq.s page 1 197 .thumb_func 199 MX_DMA_Init: 200 .LFB246: - 218:Core/Src/main.c **** - 201 .loc 1 218 1 is_stmt 1 view -0 + 255:Core/Src/main.c **** + 201 .loc 1 255 1 is_stmt 1 view -0 202 .cfi_startproc 203 @ args = 0, pretend = 0, frame = 8 204 @ frame_needed = 0, uses_anonymous_args = 0 205 0000 00B5 push {lr} 206 .LCFI3: 207 .cfi_def_cfa_offset 4 + ARM GAS /tmp/ccYDS01w.s page 10 + + 208 .cfi_offset 14, -4 209 0002 83B0 sub sp, sp, #12 210 .LCFI4: 211 .cfi_def_cfa_offset 16 - 221:Core/Src/main.c **** - 212 .loc 1 221 3 view .LVU53 + 258:Core/Src/main.c **** + 212 .loc 1 258 3 view .LVU53 213 .LBB9: - 221:Core/Src/main.c **** - 214 .loc 1 221 3 view .LVU54 + 258:Core/Src/main.c **** + 214 .loc 1 258 3 view .LVU54 215 0004 0021 movs r1, #0 216 0006 0191 str r1, [sp, #4] - 221:Core/Src/main.c **** - 217 .loc 1 221 3 view .LVU55 + 258:Core/Src/main.c **** + 217 .loc 1 258 3 view .LVU55 218 0008 094B ldr r3, .L7 219 000a 1A6B ldr r2, [r3, #48] 220 000c 42F48002 orr r2, r2, #4194304 221 0010 1A63 str r2, [r3, #48] - 221:Core/Src/main.c **** - 222 .loc 1 221 3 view .LVU56 + 258:Core/Src/main.c **** + 222 .loc 1 258 3 view .LVU56 223 0012 1B6B ldr r3, [r3, #48] 224 0014 03F48003 and r3, r3, #4194304 225 0018 0193 str r3, [sp, #4] - 221:Core/Src/main.c **** - 226 .loc 1 221 3 view .LVU57 + 258:Core/Src/main.c **** + 226 .loc 1 258 3 view .LVU57 227 001a 019B ldr r3, [sp, #4] 228 .LBE9: - 221:Core/Src/main.c **** - 229 .loc 1 221 3 view .LVU58 - 225:Core/Src/main.c **** HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); - 230 .loc 1 225 3 view .LVU59 + 258:Core/Src/main.c **** + 229 .loc 1 258 3 view .LVU58 + 262:Core/Src/main.c **** HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); + 230 .loc 1 262 3 view .LVU59 231 001c 0A46 mov r2, r1 232 001e 3820 movs r0, #56 233 0020 FFF7FEFF bl HAL_NVIC_SetPriority 234 .LVL4: - 226:Core/Src/main.c **** - 235 .loc 1 226 3 view .LVU60 + 263:Core/Src/main.c **** + 235 .loc 1 263 3 view .LVU60 236 0024 3820 movs r0, #56 - ARM GAS /tmp/cchXeloq.s page 10 - - 237 0026 FFF7FEFF bl HAL_NVIC_EnableIRQ 238 .LVL5: - 228:Core/Src/main.c **** - 239 .loc 1 228 1 is_stmt 0 view .LVU61 + 265:Core/Src/main.c **** + 239 .loc 1 265 1 is_stmt 0 view .LVU61 240 002a 03B0 add sp, sp, #12 241 .LCFI5: 242 .cfi_def_cfa_offset 4 @@ -561,30 +598,33 @@ ARM GAS /tmp/cchXeloq.s page 1 254 .global Error_Handler 255 .syntax unified 256 .thumb + ARM GAS /tmp/ccYDS01w.s page 11 + + 257 .thumb_func 259 Error_Handler: 260 .LFB248: - 272:Core/Src/main.c **** - 273:Core/Src/main.c **** /* USER CODE BEGIN 4 */ - 274:Core/Src/main.c **** - 275:Core/Src/main.c **** /* USER CODE END 4 */ - 276:Core/Src/main.c **** - 277:Core/Src/main.c **** /** - 278:Core/Src/main.c **** * @brief This function is executed in case of error occurrence. - 279:Core/Src/main.c **** * @retval None - 280:Core/Src/main.c **** */ - 281:Core/Src/main.c **** void Error_Handler(void) - 282:Core/Src/main.c **** { - 261 .loc 1 282 1 is_stmt 1 view -0 + 309:Core/Src/main.c **** + 310:Core/Src/main.c **** /* USER CODE BEGIN 4 */ + 311:Core/Src/main.c **** + 312:Core/Src/main.c **** /* USER CODE END 4 */ + 313:Core/Src/main.c **** + 314:Core/Src/main.c **** /** + 315:Core/Src/main.c **** * @brief This function is executed in case of error occurrence. + 316:Core/Src/main.c **** * @retval None + 317:Core/Src/main.c **** */ + 318:Core/Src/main.c **** void Error_Handler(void) + 319:Core/Src/main.c **** { + 261 .loc 1 319 1 is_stmt 1 view -0 262 .cfi_startproc 263 @ Volatile: function does not return. 264 @ args = 0, pretend = 0, frame = 0 265 @ frame_needed = 0, uses_anonymous_args = 0 266 @ link register save eliminated. - 283:Core/Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */ - 284:Core/Src/main.c **** /* User can add his own implementation to report the HAL error return state */ - 285:Core/Src/main.c **** __disable_irq(); - 267 .loc 1 285 3 view .LVU63 + 320:Core/Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */ + 321:Core/Src/main.c **** /* User can add his own implementation to report the HAL error return state */ + 322:Core/Src/main.c **** __disable_irq(); + 267 .loc 1 322 3 view .LVU63 268 .LBB10: 269 .LBI10: 270 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" @@ -598,9 +638,6 @@ ARM GAS /tmp/cchXeloq.s page 1 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2021 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 - ARM GAS /tmp/cchXeloq.s page 11 - - 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. @@ -621,6 +658,9 @@ ARM GAS /tmp/cchXeloq.s page 1 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + ARM GAS /tmp/ccYDS01w.s page 12 + + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" 33:Drivers/CMSIS/Include/cmsis_gcc.h **** @@ -658,9 +698,6 @@ ARM GAS /tmp/cchXeloq.s page 1 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION - ARM GAS /tmp/cchXeloq.s page 12 - - 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ @@ -681,6 +718,9 @@ ARM GAS /tmp/cchXeloq.s page 1 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + ARM GAS /tmp/ccYDS01w.s page 13 + + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; @@ -718,9 +758,6 @@ ARM GAS /tmp/cchXeloq.s page 1 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** - ARM GAS /tmp/cchXeloq.s page 13 - - 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Initializes data and bss sections 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details This default implementations initialized all data and additional bss 127:Drivers/CMSIS/Include/cmsis_gcc.h **** sections relying on .copy.table and .zero.table specified properly @@ -741,6 +778,9 @@ ARM GAS /tmp/cchXeloq.s page 1 142:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest; 143:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen; 144:Drivers/CMSIS/Include/cmsis_gcc.h **** } __zero_table_t; + ARM GAS /tmp/ccYDS01w.s page 14 + + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 146:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_start__; 147:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_end__; @@ -778,9 +818,6 @@ ARM GAS /tmp/cchXeloq.s page 1 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 180:Drivers/CMSIS/Include/cmsis_gcc.h **** 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE - ARM GAS /tmp/cchXeloq.s page 14 - - 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 184:Drivers/CMSIS/Include/cmsis_gcc.h **** @@ -801,6 +838,9 @@ ARM GAS /tmp/cchXeloq.s page 1 199:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { 200:Drivers/CMSIS/Include/cmsis_gcc.h **** *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; 201:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccYDS01w.s page 15 + + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 203:Drivers/CMSIS/Include/cmsis_gcc.h **** 204:Drivers/CMSIS/Include/cmsis_gcc.h **** @@ -838,9 +878,6 @@ ARM GAS /tmp/cchXeloq.s page 1 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 237:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 238:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event - ARM GAS /tmp/cchXeloq.s page 15 - - 239:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter 240:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. 241:Drivers/CMSIS/Include/cmsis_gcc.h **** */ @@ -861,6 +898,9 @@ ARM GAS /tmp/cchXeloq.s page 1 256:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. 257:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 258:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + ARM GAS /tmp/ccYDS01w.s page 16 + + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** { 260:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); 261:Drivers/CMSIS/Include/cmsis_gcc.h **** } @@ -898,9 +938,6 @@ ARM GAS /tmp/cchXeloq.s page 1 293:Drivers/CMSIS/Include/cmsis_gcc.h **** { 294:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) 295:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); - ARM GAS /tmp/cchXeloq.s page 16 - - 296:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 297:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 298:Drivers/CMSIS/Include/cmsis_gcc.h **** @@ -921,6 +958,9 @@ ARM GAS /tmp/cchXeloq.s page 1 313:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 314:Drivers/CMSIS/Include/cmsis_gcc.h **** 315:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + ARM GAS /tmp/ccYDS01w.s page 17 + + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 317:Drivers/CMSIS/Include/cmsis_gcc.h **** } 318:Drivers/CMSIS/Include/cmsis_gcc.h **** @@ -958,9 +998,6 @@ ARM GAS /tmp/cchXeloq.s page 1 350:Drivers/CMSIS/Include/cmsis_gcc.h **** { 351:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; 352:Drivers/CMSIS/Include/cmsis_gcc.h **** } - ARM GAS /tmp/cchXeloq.s page 17 - - 353:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); 354:Drivers/CMSIS/Include/cmsis_gcc.h **** } 355:Drivers/CMSIS/Include/cmsis_gcc.h **** @@ -981,6 +1018,9 @@ ARM GAS /tmp/cchXeloq.s page 1 370:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 371:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 372:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccYDS01w.s page 18 + + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) 374:Drivers/CMSIS/Include/cmsis_gcc.h **** { 375:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; @@ -1018,9 +1058,6 @@ ARM GAS /tmp/cchXeloq.s page 1 407:Drivers/CMSIS/Include/cmsis_gcc.h **** This guarantees ARM-compatible results if happening to compile on a non-ARM 408:Drivers/CMSIS/Include/cmsis_gcc.h **** target, and ensures the compiler doesn't decide to activate any 409:Drivers/CMSIS/Include/cmsis_gcc.h **** optimisations using the logic "value was passed to __builtin_clz, so it - ARM GAS /tmp/cchXeloq.s page 18 - - 410:Drivers/CMSIS/Include/cmsis_gcc.h **** is non-zero". 411:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a 412:Drivers/CMSIS/Include/cmsis_gcc.h **** single CLZ instruction. @@ -1041,6 +1078,9 @@ ARM GAS /tmp/cchXeloq.s page 1 427:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (8 bit) 428:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 8 bit value. 429:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data + ARM GAS /tmp/ccYDS01w.s page 19 + + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) 431:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 432:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) @@ -1078,9 +1118,6 @@ ARM GAS /tmp/cchXeloq.s page 1 464:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); 465:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); /* Add explicit type cast here */ - ARM GAS /tmp/cchXeloq.s page 19 - - 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 469:Drivers/CMSIS/Include/cmsis_gcc.h **** @@ -1101,6 +1138,9 @@ ARM GAS /tmp/cchXeloq.s page 1 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 485:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 486:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (8 bit) + ARM GAS /tmp/ccYDS01w.s page 20 + + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 8 bit values. 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location @@ -1138,9 +1178,6 @@ ARM GAS /tmp/cchXeloq.s page 1 521:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 32 bit values. 522:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location - ARM GAS /tmp/cchXeloq.s page 20 - - 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ @@ -1161,6 +1198,9 @@ ARM GAS /tmp/cchXeloq.s page 1 541:Drivers/CMSIS/Include/cmsis_gcc.h **** { 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("clrex" ::: "memory"); 543:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccYDS01w.s page 21 + + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** 545:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 546:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ @@ -1198,9 +1238,6 @@ ARM GAS /tmp/cchXeloq.s page 1 578:Drivers/CMSIS/Include/cmsis_gcc.h **** __extension__ \ 579:Drivers/CMSIS/Include/cmsis_gcc.h **** ({ \ 580:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t __RES, __ARG1 = (ARG1); \ - ARM GAS /tmp/cchXeloq.s page 21 - - 581:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ 582:Drivers/CMSIS/Include/cmsis_gcc.h **** __RES; \ 583:Drivers/CMSIS/Include/cmsis_gcc.h **** }) @@ -1221,6 +1258,9 @@ ARM GAS /tmp/cchXeloq.s page 1 598:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 599:Drivers/CMSIS/Include/cmsis_gcc.h **** } 600:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccYDS01w.s page 22 + + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** 602:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 603:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDRT Unprivileged (8 bit) @@ -1258,9 +1298,6 @@ ARM GAS /tmp/cchXeloq.s page 1 635:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); 636:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 637:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - ARM GAS /tmp/cchXeloq.s page 22 - - 638:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 639:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 640:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); @@ -1281,6 +1318,9 @@ ARM GAS /tmp/cchXeloq.s page 1 655:Drivers/CMSIS/Include/cmsis_gcc.h **** 656:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); 657:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + ARM GAS /tmp/ccYDS01w.s page 23 + + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** } 659:Drivers/CMSIS/Include/cmsis_gcc.h **** 660:Drivers/CMSIS/Include/cmsis_gcc.h **** @@ -1318,9 +1358,6 @@ ARM GAS /tmp/cchXeloq.s page 1 692:Drivers/CMSIS/Include/cmsis_gcc.h **** { 693:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); 694:Drivers/CMSIS/Include/cmsis_gcc.h **** } - ARM GAS /tmp/cchXeloq.s page 23 - - 695:Drivers/CMSIS/Include/cmsis_gcc.h **** 696:Drivers/CMSIS/Include/cmsis_gcc.h **** #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 697:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ @@ -1341,6 +1378,9 @@ ARM GAS /tmp/cchXeloq.s page 1 712:Drivers/CMSIS/Include/cmsis_gcc.h **** const int32_t min = -1 - max ; 713:Drivers/CMSIS/Include/cmsis_gcc.h **** if (val > max) 714:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/ccYDS01w.s page 24 + + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** return max; 716:Drivers/CMSIS/Include/cmsis_gcc.h **** } 717:Drivers/CMSIS/Include/cmsis_gcc.h **** else if (val < min) @@ -1378,9 +1418,6 @@ ARM GAS /tmp/cchXeloq.s page 1 749:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 751:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - ARM GAS /tmp/cchXeloq.s page 24 - - 752:Drivers/CMSIS/Include/cmsis_gcc.h **** 753:Drivers/CMSIS/Include/cmsis_gcc.h **** 754:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ @@ -1401,6 +1438,9 @@ ARM GAS /tmp/cchXeloq.s page 1 769:Drivers/CMSIS/Include/cmsis_gcc.h **** 770:Drivers/CMSIS/Include/cmsis_gcc.h **** 771:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccYDS01w.s page 25 + + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire (16 bit) 773:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDAH instruction for 16 bit values. 774:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data @@ -1438,9 +1478,6 @@ ARM GAS /tmp/cchXeloq.s page 1 806:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 807:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) 808:Drivers/CMSIS/Include/cmsis_gcc.h **** { - ARM GAS /tmp/cchXeloq.s page 25 - - 809:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 810:Drivers/CMSIS/Include/cmsis_gcc.h **** } 811:Drivers/CMSIS/Include/cmsis_gcc.h **** @@ -1461,6 +1498,9 @@ ARM GAS /tmp/cchXeloq.s page 1 826:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release (32 bit) 827:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STL instruction for 32 bit values. 828:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store + ARM GAS /tmp/ccYDS01w.s page 26 + + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 830:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 831:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) @@ -1498,9 +1538,6 @@ ARM GAS /tmp/cchXeloq.s page 1 863:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); 864:Drivers/CMSIS/Include/cmsis_gcc.h **** } 865:Drivers/CMSIS/Include/cmsis_gcc.h **** - ARM GAS /tmp/cchXeloq.s page 26 - - 866:Drivers/CMSIS/Include/cmsis_gcc.h **** 867:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 868:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire Exclusive (32 bit) @@ -1521,6 +1558,9 @@ ARM GAS /tmp/cchXeloq.s page 1 883:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release Exclusive (8 bit) 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STLB exclusive instruction for 8 bit values. 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store + ARM GAS /tmp/ccYDS01w.s page 27 + + 886:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 887:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 888:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed @@ -1558,9 +1598,6 @@ ARM GAS /tmp/cchXeloq.s page 1 920:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 921:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 922:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed - ARM GAS /tmp/cchXeloq.s page 27 - - 923:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 924:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) 925:Drivers/CMSIS/Include/cmsis_gcc.h **** { @@ -1581,6 +1618,9 @@ ARM GAS /tmp/cchXeloq.s page 1 940:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 941:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 942:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccYDS01w.s page 28 + + 943:Drivers/CMSIS/Include/cmsis_gcc.h **** 944:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 945:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts @@ -1613,16 +1653,13 @@ ARM GAS /tmp/cchXeloq.s page 1 280 .L10: 281 .LBE11: 282 .LBE10: - 286:Core/Src/main.c **** while (1) - 283 .loc 1 286 3 view .LVU66 - 287:Core/Src/main.c **** { - 288:Core/Src/main.c **** } - 284 .loc 1 288 3 view .LVU67 - ARM GAS /tmp/cchXeloq.s page 28 - - - 286:Core/Src/main.c **** while (1) - 285 .loc 1 286 9 view .LVU68 + 323:Core/Src/main.c **** while (1) + 283 .loc 1 323 3 view .LVU66 + 324:Core/Src/main.c **** { + 325:Core/Src/main.c **** } + 284 .loc 1 325 3 view .LVU67 + 323:Core/Src/main.c **** while (1) + 285 .loc 1 323 9 view .LVU68 286 0002 FEE7 b .L10 287 .cfi_endproc 288 .LFE248: @@ -1633,139 +1670,142 @@ ARM GAS /tmp/cchXeloq.s page 1 294 .thumb_func 296 MX_ADC1_Init: 297 .LFB245: - 168:Core/Src/main.c **** - 298 .loc 1 168 1 view -0 + 205:Core/Src/main.c **** + 298 .loc 1 205 1 view -0 299 .cfi_startproc 300 @ args = 0, pretend = 0, frame = 16 301 @ frame_needed = 0, uses_anonymous_args = 0 302 0000 00B5 push {lr} 303 .LCFI6: 304 .cfi_def_cfa_offset 4 + ARM GAS /tmp/ccYDS01w.s page 29 + + 305 .cfi_offset 14, -4 306 0002 85B0 sub sp, sp, #20 307 .LCFI7: 308 .cfi_def_cfa_offset 24 - 174:Core/Src/main.c **** - 309 .loc 1 174 3 view .LVU70 - 174:Core/Src/main.c **** - 310 .loc 1 174 26 is_stmt 0 view .LVU71 + 211:Core/Src/main.c **** + 309 .loc 1 211 3 view .LVU70 + 211:Core/Src/main.c **** + 310 .loc 1 211 26 is_stmt 0 view .LVU71 311 0004 0023 movs r3, #0 312 0006 0093 str r3, [sp] 313 0008 0193 str r3, [sp, #4] 314 000a 0293 str r3, [sp, #8] 315 000c 0393 str r3, [sp, #12] - 182:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; - 316 .loc 1 182 3 is_stmt 1 view .LVU72 - 182:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; - 317 .loc 1 182 18 is_stmt 0 view .LVU73 + 219:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; + 316 .loc 1 219 3 is_stmt 1 view .LVU72 + 219:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; + 317 .loc 1 219 18 is_stmt 0 view .LVU73 318 000e 1648 ldr r0, .L17 319 0010 164A ldr r2, .L17+4 320 0012 0260 str r2, [r0] - 183:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; - 321 .loc 1 183 3 is_stmt 1 view .LVU74 - 183:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; - 322 .loc 1 183 29 is_stmt 0 view .LVU75 + 220:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; + 321 .loc 1 220 3 is_stmt 1 view .LVU74 + 220:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; + 322 .loc 1 220 29 is_stmt 0 view .LVU75 323 0014 4FF48032 mov r2, #65536 324 0018 4260 str r2, [r0, #4] - 184:Core/Src/main.c **** hadc1.Init.ScanConvMode = DISABLE; - 325 .loc 1 184 3 is_stmt 1 view .LVU76 - 184:Core/Src/main.c **** hadc1.Init.ScanConvMode = DISABLE; - 326 .loc 1 184 25 is_stmt 0 view .LVU77 + 221:Core/Src/main.c **** hadc1.Init.ScanConvMode = DISABLE; + 325 .loc 1 221 3 is_stmt 1 view .LVU76 + 221:Core/Src/main.c **** hadc1.Init.ScanConvMode = DISABLE; + 326 .loc 1 221 25 is_stmt 0 view .LVU77 327 001a 8360 str r3, [r0, #8] - 185:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; - 328 .loc 1 185 3 is_stmt 1 view .LVU78 - 185:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; - 329 .loc 1 185 27 is_stmt 0 view .LVU79 + 222:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; + 328 .loc 1 222 3 is_stmt 1 view .LVU78 + 222:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; + 329 .loc 1 222 27 is_stmt 0 view .LVU79 330 001c 0361 str r3, [r0, #16] - 186:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; - ARM GAS /tmp/cchXeloq.s page 29 - - - 331 .loc 1 186 3 is_stmt 1 view .LVU80 - 186:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; - 332 .loc 1 186 33 is_stmt 0 view .LVU81 + 223:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; + 331 .loc 1 223 3 is_stmt 1 view .LVU80 + 223:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; + 332 .loc 1 223 33 is_stmt 0 view .LVU81 333 001e 0376 strb r3, [r0, #24] - 187:Core/Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; - 334 .loc 1 187 3 is_stmt 1 view .LVU82 - 187:Core/Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; - 335 .loc 1 187 36 is_stmt 0 view .LVU83 + 224:Core/Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; + 334 .loc 1 224 3 is_stmt 1 view .LVU82 + 224:Core/Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; + 335 .loc 1 224 36 is_stmt 0 view .LVU83 336 0020 80F82030 strb r3, [r0, #32] - 188:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_Ext_IT11; - 337 .loc 1 188 3 is_stmt 1 view .LVU84 - 188:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_Ext_IT11; - 338 .loc 1 188 35 is_stmt 0 view .LVU85 + 225:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_Ext_IT11; + 337 .loc 1 225 3 is_stmt 1 view .LVU84 + 225:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_Ext_IT11; + 338 .loc 1 225 35 is_stmt 0 view .LVU85 339 0024 4FF08052 mov r2, #268435456 340 0028 C262 str r2, [r0, #44] - 189:Core/Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; - 341 .loc 1 189 3 is_stmt 1 view .LVU86 - 189:Core/Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; - 342 .loc 1 189 31 is_stmt 0 view .LVU87 + 226:Core/Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + 341 .loc 1 226 3 is_stmt 1 view .LVU86 + 226:Core/Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + 342 .loc 1 226 31 is_stmt 0 view .LVU87 343 002a 4FF07062 mov r2, #251658240 + ARM GAS /tmp/ccYDS01w.s page 30 + + 344 002e 8262 str r2, [r0, #40] - 190:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1; - 345 .loc 1 190 3 is_stmt 1 view .LVU88 - 190:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1; - 346 .loc 1 190 24 is_stmt 0 view .LVU89 + 227:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1; + 345 .loc 1 227 3 is_stmt 1 view .LVU88 + 227:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1; + 346 .loc 1 227 24 is_stmt 0 view .LVU89 347 0030 C360 str r3, [r0, #12] - 191:Core/Src/main.c **** hadc1.Init.DMAContinuousRequests = ENABLE; - 348 .loc 1 191 3 is_stmt 1 view .LVU90 - 191:Core/Src/main.c **** hadc1.Init.DMAContinuousRequests = ENABLE; - 349 .loc 1 191 30 is_stmt 0 view .LVU91 + 228:Core/Src/main.c **** hadc1.Init.DMAContinuousRequests = ENABLE; + 348 .loc 1 228 3 is_stmt 1 view .LVU90 + 228:Core/Src/main.c **** hadc1.Init.DMAContinuousRequests = ENABLE; + 349 .loc 1 228 30 is_stmt 0 view .LVU91 350 0032 0123 movs r3, #1 351 0034 C361 str r3, [r0, #28] - 192:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; - 352 .loc 1 192 3 is_stmt 1 view .LVU92 - 192:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; - 353 .loc 1 192 36 is_stmt 0 view .LVU93 + 229:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + 352 .loc 1 229 3 is_stmt 1 view .LVU92 + 229:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + 353 .loc 1 229 36 is_stmt 0 view .LVU93 354 0036 80F83030 strb r3, [r0, #48] - 193:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) - 355 .loc 1 193 3 is_stmt 1 view .LVU94 - 193:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) - 356 .loc 1 193 27 is_stmt 0 view .LVU95 + 230:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) + 355 .loc 1 230 3 is_stmt 1 view .LVU94 + 230:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) + 356 .loc 1 230 27 is_stmt 0 view .LVU95 357 003a 4361 str r3, [r0, #20] - 194:Core/Src/main.c **** { - 358 .loc 1 194 3 is_stmt 1 view .LVU96 - 194:Core/Src/main.c **** { - 359 .loc 1 194 7 is_stmt 0 view .LVU97 + 231:Core/Src/main.c **** { + 358 .loc 1 231 3 is_stmt 1 view .LVU96 + 231:Core/Src/main.c **** { + 359 .loc 1 231 7 is_stmt 0 view .LVU97 360 003c FFF7FEFF bl HAL_ADC_Init 361 .LVL6: - 194:Core/Src/main.c **** { - 362 .loc 1 194 6 discriminator 1 view .LVU98 + 231:Core/Src/main.c **** { + 362 .loc 1 231 6 discriminator 1 view .LVU98 363 0040 68B9 cbnz r0, .L15 - 201:Core/Src/main.c **** sConfig.Rank = 1; - 364 .loc 1 201 3 is_stmt 1 view .LVU99 - 201:Core/Src/main.c **** sConfig.Rank = 1; - 365 .loc 1 201 19 is_stmt 0 view .LVU100 + 238:Core/Src/main.c **** sConfig.Rank = 1; + 364 .loc 1 238 3 is_stmt 1 view .LVU99 + 238:Core/Src/main.c **** sConfig.Rank = 1; + 365 .loc 1 238 19 is_stmt 0 view .LVU100 366 0042 0323 movs r3, #3 367 0044 0093 str r3, [sp] - ARM GAS /tmp/cchXeloq.s page 30 - - - 202:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; - 368 .loc 1 202 3 is_stmt 1 view .LVU101 - 202:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; - 369 .loc 1 202 16 is_stmt 0 view .LVU102 + 239:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; + 368 .loc 1 239 3 is_stmt 1 view .LVU101 + 239:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; + 369 .loc 1 239 16 is_stmt 0 view .LVU102 370 0046 0123 movs r3, #1 371 0048 0193 str r3, [sp, #4] - 203:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - 372 .loc 1 203 3 is_stmt 1 view .LVU103 - 203:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - 373 .loc 1 203 24 is_stmt 0 view .LVU104 + 240:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + 372 .loc 1 240 3 is_stmt 1 view .LVU103 + 240:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + 373 .loc 1 240 24 is_stmt 0 view .LVU104 374 004a 0023 movs r3, #0 375 004c 0293 str r3, [sp, #8] - 204:Core/Src/main.c **** { - 376 .loc 1 204 3 is_stmt 1 view .LVU105 - 204:Core/Src/main.c **** { - 377 .loc 1 204 7 is_stmt 0 view .LVU106 + 241:Core/Src/main.c **** { + 376 .loc 1 241 3 is_stmt 1 view .LVU105 + 241:Core/Src/main.c **** { + 377 .loc 1 241 7 is_stmt 0 view .LVU106 378 004e 6946 mov r1, sp 379 0050 0548 ldr r0, .L17 380 0052 FFF7FEFF bl HAL_ADC_ConfigChannel 381 .LVL7: - 204:Core/Src/main.c **** { - 382 .loc 1 204 6 discriminator 1 view .LVU107 + ARM GAS /tmp/ccYDS01w.s page 31 + + + 241:Core/Src/main.c **** { + 382 .loc 1 241 6 discriminator 1 view .LVU107 383 0056 20B9 cbnz r0, .L16 - 212:Core/Src/main.c **** - 384 .loc 1 212 1 view .LVU108 + 249:Core/Src/main.c **** + 384 .loc 1 249 1 view .LVU108 385 0058 05B0 add sp, sp, #20 386 .LCFI8: 387 .cfi_remember_state @@ -1775,13 +1815,13 @@ ARM GAS /tmp/cchXeloq.s page 1 391 .L15: 392 .LCFI9: 393 .cfi_restore_state - 196:Core/Src/main.c **** } - 394 .loc 1 196 5 is_stmt 1 view .LVU109 + 233:Core/Src/main.c **** } + 394 .loc 1 233 5 is_stmt 1 view .LVU109 395 005e FFF7FEFF bl Error_Handler 396 .LVL8: 397 .L16: - 206:Core/Src/main.c **** } - 398 .loc 1 206 5 view .LVU110 + 243:Core/Src/main.c **** } + 398 .loc 1 243 5 view .LVU110 399 0062 FFF7FEFF bl Error_Handler 400 .LVL9: 401 .L18: @@ -1798,12 +1838,9 @@ ARM GAS /tmp/cchXeloq.s page 1 413 .thumb 414 .thumb_func 416 SystemClock_Config: - ARM GAS /tmp/cchXeloq.s page 31 - - 417 .LFB244: - 122:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - 418 .loc 1 122 1 view -0 + 159:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 418 .loc 1 159 1 view -0 419 .cfi_startproc 420 @ args = 0, pretend = 0, frame = 80 421 @ frame_needed = 0, uses_anonymous_args = 0 @@ -1814,180 +1851,180 @@ ARM GAS /tmp/cchXeloq.s page 1 426 0002 95B0 sub sp, sp, #84 427 .LCFI11: 428 .cfi_def_cfa_offset 88 - 123:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - 429 .loc 1 123 3 view .LVU112 - 123:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - 430 .loc 1 123 22 is_stmt 0 view .LVU113 + 160:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 429 .loc 1 160 3 view .LVU112 + 160:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 430 .loc 1 160 22 is_stmt 0 view .LVU113 431 0004 3022 movs r2, #48 432 0006 0021 movs r1, #0 433 0008 08A8 add r0, sp, #32 + ARM GAS /tmp/ccYDS01w.s page 32 + + 434 000a FFF7FEFF bl memset 435 .LVL10: - 124:Core/Src/main.c **** - 436 .loc 1 124 3 is_stmt 1 view .LVU114 - 124:Core/Src/main.c **** - 437 .loc 1 124 22 is_stmt 0 view .LVU115 + 161:Core/Src/main.c **** + 436 .loc 1 161 3 is_stmt 1 view .LVU114 + 161:Core/Src/main.c **** + 437 .loc 1 161 22 is_stmt 0 view .LVU115 438 000e 0023 movs r3, #0 439 0010 0393 str r3, [sp, #12] 440 0012 0493 str r3, [sp, #16] 441 0014 0593 str r3, [sp, #20] 442 0016 0693 str r3, [sp, #24] 443 0018 0793 str r3, [sp, #28] - 128:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - 444 .loc 1 128 3 is_stmt 1 view .LVU116 + 165:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 444 .loc 1 165 3 is_stmt 1 view .LVU116 445 .LBB12: - 128:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - 446 .loc 1 128 3 view .LVU117 + 165:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 446 .loc 1 165 3 view .LVU117 447 001a 0193 str r3, [sp, #4] - 128:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - 448 .loc 1 128 3 view .LVU118 + 165:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 448 .loc 1 165 3 view .LVU118 449 001c 214A ldr r2, .L25 450 001e 116C ldr r1, [r2, #64] 451 0020 41F08051 orr r1, r1, #268435456 452 0024 1164 str r1, [r2, #64] - 128:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - 453 .loc 1 128 3 view .LVU119 + 165:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 453 .loc 1 165 3 view .LVU119 454 0026 126C ldr r2, [r2, #64] 455 0028 02F08052 and r2, r2, #268435456 456 002c 0192 str r2, [sp, #4] - 128:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - 457 .loc 1 128 3 view .LVU120 + 165:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 457 .loc 1 165 3 view .LVU120 458 002e 019A ldr r2, [sp, #4] 459 .LBE12: - 128:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - 460 .loc 1 128 3 view .LVU121 - 129:Core/Src/main.c **** - 461 .loc 1 129 3 view .LVU122 - ARM GAS /tmp/cchXeloq.s page 32 - - + 165:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 460 .loc 1 165 3 view .LVU121 + 166:Core/Src/main.c **** + 461 .loc 1 166 3 view .LVU122 462 .LBB13: - 129:Core/Src/main.c **** - 463 .loc 1 129 3 view .LVU123 + 166:Core/Src/main.c **** + 463 .loc 1 166 3 view .LVU123 464 0030 0293 str r3, [sp, #8] - 129:Core/Src/main.c **** - 465 .loc 1 129 3 view .LVU124 + 166:Core/Src/main.c **** + 465 .loc 1 166 3 view .LVU124 466 0032 1D4B ldr r3, .L25+4 467 0034 1A68 ldr r2, [r3] 468 0036 42F44042 orr r2, r2, #49152 469 003a 1A60 str r2, [r3] - 129:Core/Src/main.c **** - 470 .loc 1 129 3 view .LVU125 + 166:Core/Src/main.c **** + 470 .loc 1 166 3 view .LVU125 471 003c 1B68 ldr r3, [r3] 472 003e 03F44043 and r3, r3, #49152 473 0042 0293 str r3, [sp, #8] - 129:Core/Src/main.c **** - 474 .loc 1 129 3 view .LVU126 + 166:Core/Src/main.c **** + 474 .loc 1 166 3 view .LVU126 475 0044 029B ldr r3, [sp, #8] 476 .LBE13: - 129:Core/Src/main.c **** - 477 .loc 1 129 3 view .LVU127 - 134:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; - 478 .loc 1 134 3 view .LVU128 - 134:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; - 479 .loc 1 134 36 is_stmt 0 view .LVU129 + 166:Core/Src/main.c **** + ARM GAS /tmp/ccYDS01w.s page 33 + + + 477 .loc 1 166 3 view .LVU127 + 171:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 478 .loc 1 171 3 view .LVU128 + 171:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 479 .loc 1 171 36 is_stmt 0 view .LVU129 480 0046 0123 movs r3, #1 481 0048 0893 str r3, [sp, #32] - 135:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - 482 .loc 1 135 3 is_stmt 1 view .LVU130 - 135:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - 483 .loc 1 135 30 is_stmt 0 view .LVU131 + 172:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 482 .loc 1 172 3 is_stmt 1 view .LVU130 + 172:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 483 .loc 1 172 30 is_stmt 0 view .LVU131 484 004a 4FF48033 mov r3, #65536 485 004e 0993 str r3, [sp, #36] - 136:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - 486 .loc 1 136 3 is_stmt 1 view .LVU132 - 136:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - 487 .loc 1 136 34 is_stmt 0 view .LVU133 + 173:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + 486 .loc 1 173 3 is_stmt 1 view .LVU132 + 173:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + 487 .loc 1 173 34 is_stmt 0 view .LVU133 488 0050 0223 movs r3, #2 489 0052 0E93 str r3, [sp, #56] - 137:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 8; - 490 .loc 1 137 3 is_stmt 1 view .LVU134 - 137:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 8; - 491 .loc 1 137 35 is_stmt 0 view .LVU135 + 174:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 8; + 490 .loc 1 174 3 is_stmt 1 view .LVU134 + 174:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 8; + 491 .loc 1 174 35 is_stmt 0 view .LVU135 492 0054 4FF48002 mov r2, #4194304 493 0058 0F92 str r2, [sp, #60] - 138:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 336; - 494 .loc 1 138 3 is_stmt 1 view .LVU136 - 138:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 336; - 495 .loc 1 138 30 is_stmt 0 view .LVU137 + 175:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 336; + 494 .loc 1 175 3 is_stmt 1 view .LVU136 + 175:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 336; + 495 .loc 1 175 30 is_stmt 0 view .LVU137 496 005a 0822 movs r2, #8 497 005c 1092 str r2, [sp, #64] - 139:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - 498 .loc 1 139 3 is_stmt 1 view .LVU138 - 139:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - 499 .loc 1 139 30 is_stmt 0 view .LVU139 + 176:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + 498 .loc 1 176 3 is_stmt 1 view .LVU138 + 176:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + 499 .loc 1 176 30 is_stmt 0 view .LVU139 500 005e 4FF4A872 mov r2, #336 501 0062 1192 str r2, [sp, #68] - ARM GAS /tmp/cchXeloq.s page 33 - - - 140:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 7; - 502 .loc 1 140 3 is_stmt 1 view .LVU140 - 140:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 7; - 503 .loc 1 140 30 is_stmt 0 view .LVU141 + 177:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 7; + 502 .loc 1 177 3 is_stmt 1 view .LVU140 + 177:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 7; + 503 .loc 1 177 30 is_stmt 0 view .LVU141 504 0064 1293 str r3, [sp, #72] - 141:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - 505 .loc 1 141 3 is_stmt 1 view .LVU142 - 141:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - 506 .loc 1 141 30 is_stmt 0 view .LVU143 + 178:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 505 .loc 1 178 3 is_stmt 1 view .LVU142 + 178:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 506 .loc 1 178 30 is_stmt 0 view .LVU143 507 0066 0723 movs r3, #7 508 0068 1393 str r3, [sp, #76] - 142:Core/Src/main.c **** { - 509 .loc 1 142 3 is_stmt 1 view .LVU144 - 142:Core/Src/main.c **** { - 510 .loc 1 142 7 is_stmt 0 view .LVU145 + 179:Core/Src/main.c **** { + 509 .loc 1 179 3 is_stmt 1 view .LVU144 + 179:Core/Src/main.c **** { + 510 .loc 1 179 7 is_stmt 0 view .LVU145 511 006a 08A8 add r0, sp, #32 512 006c FFF7FEFF bl HAL_RCC_OscConfig 513 .LVL11: - 142:Core/Src/main.c **** { - 514 .loc 1 142 6 discriminator 1 view .LVU146 + 179:Core/Src/main.c **** { + 514 .loc 1 179 6 discriminator 1 view .LVU146 + ARM GAS /tmp/ccYDS01w.s page 34 + + 515 0070 98B9 cbnz r0, .L23 - 149:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - 516 .loc 1 149 3 is_stmt 1 view .LVU147 - 149:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - 517 .loc 1 149 31 is_stmt 0 view .LVU148 + 186:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + 516 .loc 1 186 3 is_stmt 1 view .LVU147 + 186:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + 517 .loc 1 186 31 is_stmt 0 view .LVU148 518 0072 0F23 movs r3, #15 519 0074 0393 str r3, [sp, #12] - 151:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - 520 .loc 1 151 3 is_stmt 1 view .LVU149 - 151:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - 521 .loc 1 151 34 is_stmt 0 view .LVU150 + 188:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 520 .loc 1 188 3 is_stmt 1 view .LVU149 + 188:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 521 .loc 1 188 34 is_stmt 0 view .LVU150 522 0076 0223 movs r3, #2 523 0078 0493 str r3, [sp, #16] - 152:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - 524 .loc 1 152 3 is_stmt 1 view .LVU151 - 152:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - 525 .loc 1 152 35 is_stmt 0 view .LVU152 + 189:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + 524 .loc 1 189 3 is_stmt 1 view .LVU151 + 189:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + 525 .loc 1 189 35 is_stmt 0 view .LVU152 526 007a 0023 movs r3, #0 527 007c 0593 str r3, [sp, #20] - 153:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - 528 .loc 1 153 3 is_stmt 1 view .LVU153 - 153:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - 529 .loc 1 153 36 is_stmt 0 view .LVU154 + 190:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + 528 .loc 1 190 3 is_stmt 1 view .LVU153 + 190:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + 529 .loc 1 190 36 is_stmt 0 view .LVU154 530 007e 4FF4A053 mov r3, #5120 531 0082 0693 str r3, [sp, #24] - 154:Core/Src/main.c **** - 532 .loc 1 154 3 is_stmt 1 view .LVU155 - 154:Core/Src/main.c **** - 533 .loc 1 154 36 is_stmt 0 view .LVU156 + 191:Core/Src/main.c **** + 532 .loc 1 191 3 is_stmt 1 view .LVU155 + 191:Core/Src/main.c **** + 533 .loc 1 191 36 is_stmt 0 view .LVU156 534 0084 4FF48053 mov r3, #4096 535 0088 0793 str r3, [sp, #28] - 156:Core/Src/main.c **** { - 536 .loc 1 156 3 is_stmt 1 view .LVU157 - 156:Core/Src/main.c **** { - 537 .loc 1 156 7 is_stmt 0 view .LVU158 + 193:Core/Src/main.c **** { + 536 .loc 1 193 3 is_stmt 1 view .LVU157 + 193:Core/Src/main.c **** { + 537 .loc 1 193 7 is_stmt 0 view .LVU158 538 008a 0521 movs r1, #5 539 008c 03A8 add r0, sp, #12 - ARM GAS /tmp/cchXeloq.s page 34 - - 540 008e FFF7FEFF bl HAL_RCC_ClockConfig 541 .LVL12: - 156:Core/Src/main.c **** { - 542 .loc 1 156 6 discriminator 1 view .LVU159 + 193:Core/Src/main.c **** { + 542 .loc 1 193 6 discriminator 1 view .LVU159 543 0092 20B9 cbnz r0, .L24 - 160:Core/Src/main.c **** - 544 .loc 1 160 1 view .LVU160 + 197:Core/Src/main.c **** + 544 .loc 1 197 1 view .LVU160 545 0094 15B0 add sp, sp, #84 546 .LCFI12: 547 .cfi_remember_state @@ -1997,13 +2034,16 @@ ARM GAS /tmp/cchXeloq.s page 1 551 .L23: 552 .LCFI13: 553 .cfi_restore_state - 144:Core/Src/main.c **** } - 554 .loc 1 144 5 is_stmt 1 view .LVU161 + 181:Core/Src/main.c **** } + 554 .loc 1 181 5 is_stmt 1 view .LVU161 555 009a FFF7FEFF bl Error_Handler 556 .LVL13: + ARM GAS /tmp/ccYDS01w.s page 35 + + 557 .L24: - 158:Core/Src/main.c **** } - 558 .loc 1 158 5 view .LVU162 + 195:Core/Src/main.c **** } + 558 .loc 1 195 5 view .LVU162 559 009e FFF7FEFF bl Error_Handler 560 .LVL14: 561 .L26: @@ -2016,182 +2056,517 @@ ARM GAS /tmp/cchXeloq.s page 1 569 .section .rodata.main.str1.4,"aMS",%progbits,1 570 .align 2 571 .LC0: - 572 0000 48656C6C .ascii "Hello from STM32!\015\012\000" - 572 6F206672 - 572 6F6D2053 - 572 544D3332 - 572 210D0A00 - 573 .section .text.main,"ax",%progbits - 574 .align 1 - 575 .global main - 576 .syntax unified - 577 .thumb - 578 .thumb_func - 580 main: - 581 .LFB243: - 71:Core/Src/main.c **** - 582 .loc 1 71 1 view -0 - 583 .cfi_startproc - 584 @ Volatile: function does not return. - 585 @ args = 0, pretend = 0, frame = 0 - 586 @ frame_needed = 0, uses_anonymous_args = 0 - 587 0000 08B5 push {r3, lr} - 588 .LCFI14: - 589 .cfi_def_cfa_offset 8 - ARM GAS /tmp/cchXeloq.s page 35 + 572 0000 41444320 .ascii "ADC Average calculated: \000" + 572 41766572 + 572 61676520 + 572 63616C63 + 572 756C6174 + 573 0019 000000 .align 2 + 574 .LC1: + 575 001c 0D0A00 .ascii "\015\012\000" + 576 001f 00 .align 2 + 577 .LC2: + 578 0020 48656C6C .ascii "Hello from STM32!\015\012\000" + 578 6F206672 + 578 6F6D2053 + 578 544D3332 + 578 210D0A00 + 579 .section .text.main,"ax",%progbits + 580 .align 1 + 581 .global main + 582 .syntax unified + 583 .thumb + 584 .thumb_func + 586 main: + 587 .LFB243: + 79:Core/Src/main.c **** + 588 .loc 1 79 1 view -0 + 589 .cfi_startproc + 590 @ Volatile: function does not return. + 591 @ args = 0, pretend = 0, frame = 16 + 592 @ frame_needed = 0, uses_anonymous_args = 0 + 593 0000 00B5 push {lr} + 594 .LCFI14: + 595 .cfi_def_cfa_offset 4 + 596 .cfi_offset 14, -4 + 597 0002 85B0 sub sp, sp, #20 + 598 .LCFI15: + 599 .cfi_def_cfa_offset 24 + 88:Core/Src/main.c **** + 600 .loc 1 88 3 view .LVU164 + 601 0004 FFF7FEFF bl HAL_Init + 602 .LVL15: + 95:Core/Src/main.c **** + 603 .loc 1 95 3 view .LVU165 + ARM GAS /tmp/ccYDS01w.s page 36 - 590 .cfi_offset 3, -8 - 591 .cfi_offset 14, -4 - 80:Core/Src/main.c **** - 592 .loc 1 80 3 view .LVU164 - 593 0002 FFF7FEFF bl HAL_Init - 594 .LVL15: - 87:Core/Src/main.c **** - 595 .loc 1 87 3 view .LVU165 - 596 0006 FFF7FEFF bl SystemClock_Config - 597 .LVL16: - 94:Core/Src/main.c **** MX_DMA_Init(); - 598 .loc 1 94 3 view .LVU166 - 599 000a FFF7FEFF bl MX_GPIO_Init - 600 .LVL17: - 95:Core/Src/main.c **** MX_ADC1_Init(); - 601 .loc 1 95 3 view .LVU167 - 602 000e FFF7FEFF bl MX_DMA_Init - 603 .LVL18: - 96:Core/Src/main.c **** MX_USB_DEVICE_Init(); - 604 .loc 1 96 3 view .LVU168 - 605 0012 FFF7FEFF bl MX_ADC1_Init - 606 .LVL19: - 97:Core/Src/main.c **** /* USER CODE BEGIN 2 */ - 607 .loc 1 97 3 view .LVU169 - 608 0016 FFF7FEFF bl MX_USB_DEVICE_Init - 609 .LVL20: - 99:Core/Src/main.c **** HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADC1_buff_circular, ADC_BUFF_SIZE); - 610 .loc 1 99 3 view .LVU170 - 611 001a 0122 movs r2, #1 - 612 001c 8021 movs r1, #128 - 613 001e 0A48 ldr r0, .L30 - 614 0020 FFF7FEFF bl HAL_GPIO_WritePin - 615 .LVL21: - 100:Core/Src/main.c **** /* USER CODE END 2 */ - 616 .loc 1 100 3 view .LVU171 - 617 0024 6422 movs r2, #100 - 618 0026 0949 ldr r1, .L30+4 - 619 0028 0948 ldr r0, .L30+8 - 620 002a FFF7FEFF bl HAL_ADC_Start_DMA - 621 .LVL22: - 622 .L28: - 105:Core/Src/main.c **** { - 623 .loc 1 105 3 view .LVU172 - 624 .LBB14: - 107:Core/Src/main.c **** HAL_Delay(100); - 625 .loc 1 107 5 view .LVU173 - 626 002e 4FF48041 mov r1, #16384 - 627 0032 0548 ldr r0, .L30 - 628 0034 FFF7FEFF bl HAL_GPIO_TogglePin - 629 .LVL23: - 108:Core/Src/main.c **** CDC_Transmit_FS((uint8_t *)"Hello from STM32!\r\n", 19); - 630 .loc 1 108 5 view .LVU174 - 631 0038 6420 movs r0, #100 - 632 003a FFF7FEFF bl HAL_Delay - 633 .LVL24: - 109:Core/Src/main.c **** /* USER CODE END WHILE */ - 634 .loc 1 109 5 discriminator 1 view .LVU175 - ARM GAS /tmp/cchXeloq.s page 36 + 604 0008 FFF7FEFF bl SystemClock_Config + 605 .LVL16: + 102:Core/Src/main.c **** MX_DMA_Init(); + 606 .loc 1 102 3 view .LVU166 + 607 000c FFF7FEFF bl MX_GPIO_Init + 608 .LVL17: + 103:Core/Src/main.c **** MX_ADC1_Init(); + 609 .loc 1 103 3 view .LVU167 + 610 0010 FFF7FEFF bl MX_DMA_Init + 611 .LVL18: + 104:Core/Src/main.c **** MX_USB_DEVICE_Init(); + 612 .loc 1 104 3 view .LVU168 + 613 0014 FFF7FEFF bl MX_ADC1_Init + 614 .LVL19: + 105:Core/Src/main.c **** /* USER CODE BEGIN 2 */ + 615 .loc 1 105 3 view .LVU169 + 616 0018 FFF7FEFF bl MX_USB_DEVICE_Init + 617 .LVL20: + 107:Core/Src/main.c **** HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADC1_buff_circular, ADC_BUFF_SIZE); + 618 .loc 1 107 3 view .LVU170 + 619 001c 0122 movs r2, #1 + 620 001e 8021 movs r1, #128 + 621 0020 6448 ldr r0, .L32 + 622 0022 FFF7FEFF bl HAL_GPIO_WritePin + 623 .LVL21: + 108:Core/Src/main.c **** adc_process.status = 0; // ADC started + 624 .loc 1 108 3 view .LVU171 + 625 0026 6422 movs r2, #100 + 626 0028 6349 ldr r1, .L32+4 + 627 002a 6448 ldr r0, .L32+8 + 628 002c FFF7FEFF bl HAL_ADC_Start_DMA + 629 .LVL22: + 109:Core/Src/main.c **** adc_process.N = 0; + 630 .loc 1 109 3 view .LVU172 + 109:Core/Src/main.c **** adc_process.N = 0; + 631 .loc 1 109 22 is_stmt 0 view .LVU173 + 632 0030 634B ldr r3, .L32+12 + 633 0032 0022 movs r2, #0 + 634 0034 1A70 strb r2, [r3] + 110:Core/Src/main.c **** adc_process.sum = 0; + 635 .loc 1 110 3 is_stmt 1 view .LVU174 + 110:Core/Src/main.c **** adc_process.sum = 0; + 636 .loc 1 110 17 is_stmt 0 view .LVU175 + 637 0036 DA60 str r2, [r3, #12] + 111:Core/Src/main.c **** adc_process.avg = 0; + 638 .loc 1 111 3 is_stmt 1 view .LVU176 + 111:Core/Src/main.c **** adc_process.avg = 0; + 639 .loc 1 111 19 is_stmt 0 view .LVU177 + 640 0038 5A60 str r2, [r3, #4] + 112:Core/Src/main.c **** + 641 .loc 1 112 3 is_stmt 1 view .LVU178 + 112:Core/Src/main.c **** + 642 .loc 1 112 19 is_stmt 0 view .LVU179 + 643 003a 9A60 str r2, [r3, #8] + 644 003c ACE0 b .L29 + 645 .L31: + 646 .LBB14: + ARM GAS /tmp/ccYDS01w.s page 37 - 635 003e 1321 movs r1, #19 - 636 0040 0448 ldr r0, .L30+12 - 637 0042 FFF7FEFF bl CDC_Transmit_FS - 638 .LVL25: - 639 .LBE14: - 105:Core/Src/main.c **** { - 640 .loc 1 105 9 view .LVU176 - 641 0046 F2E7 b .L28 - 642 .L31: - 643 .align 2 - 644 .L30: - 645 0048 00040240 .word 1073873920 - 646 004c 00000000 .word ADC1_buff_circular - 647 0050 00000000 .word hadc1 - 648 0054 00000000 .word .LC0 - 649 .cfi_endproc - 650 .LFE243: - 652 .global ADC1_buff_circular - 653 .section .bss.ADC1_buff_circular,"aw",%nobits - 654 .align 2 - 657 ADC1_buff_circular: - 658 0000 00000000 .space 200 - 658 00000000 - 658 00000000 - 658 00000000 - 658 00000000 - 659 .global hdma_adc1 - 660 .section .bss.hdma_adc1,"aw",%nobits - 661 .align 2 - 664 hdma_adc1: - 665 0000 00000000 .space 96 - 665 00000000 - 665 00000000 - 665 00000000 - 665 00000000 - 666 .global hadc1 - 667 .section .bss.hadc1,"aw",%nobits - 668 .align 2 - 671 hadc1: - 672 0000 00000000 .space 72 - 672 00000000 - 672 00000000 - 672 00000000 - 672 00000000 - 673 .text - 674 .Letext0: - 675 .file 3 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h" - 676 .file 4 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" - 677 .file 5 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" - 678 .file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h" - 679 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h" - 680 .file 8 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h" - 681 .file 9 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h" - 682 .file 10 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h" - 683 .file 11 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h" - 684 .file 12 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h" - 685 .file 13 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h" - ARM GAS /tmp/cchXeloq.s page 37 + 647 .LBB15: + 124:Core/Src/main.c **** adc_process.status = 1; // reset for next accumulation + 648 .loc 1 124 7 is_stmt 1 view .LVU180 + 124:Core/Src/main.c **** adc_process.status = 1; // reset for next accumulation + 649 .loc 1 124 36 is_stmt 0 view .LVU181 + 650 003e 604B ldr r3, .L32+12 + 651 0040 5A68 ldr r2, [r3, #4] + 124:Core/Src/main.c **** adc_process.status = 1; // reset for next accumulation + 652 .loc 1 124 54 view .LVU182 + 653 0042 D968 ldr r1, [r3, #12] + 124:Core/Src/main.c **** adc_process.status = 1; // reset for next accumulation + 654 .loc 1 124 41 view .LVU183 + 655 0044 B2FBF1F2 udiv r2, r2, r1 + 124:Core/Src/main.c **** adc_process.status = 1; // reset for next accumulation + 656 .loc 1 124 23 view .LVU184 + 657 0048 9A60 str r2, [r3, #8] + 125:Core/Src/main.c **** adc_process.sum = 0; + 658 .loc 1 125 7 is_stmt 1 view .LVU185 + 125:Core/Src/main.c **** adc_process.sum = 0; + 659 .loc 1 125 26 is_stmt 0 view .LVU186 + 660 004a 0121 movs r1, #1 + 661 004c 1970 strb r1, [r3] + 126:Core/Src/main.c **** adc_process.N = 0; + 662 .loc 1 126 7 is_stmt 1 view .LVU187 + 126:Core/Src/main.c **** adc_process.N = 0; + 663 .loc 1 126 23 is_stmt 0 view .LVU188 + 664 004e 0021 movs r1, #0 + 665 0050 5960 str r1, [r3, #4] + 127:Core/Src/main.c **** char digits[10] = {0}; + 666 .loc 1 127 7 is_stmt 1 view .LVU189 + 127:Core/Src/main.c **** char digits[10] = {0}; + 667 .loc 1 127 21 is_stmt 0 view .LVU190 + 668 0052 D960 str r1, [r3, #12] + 128:Core/Src/main.c **** digits[0] = (adc_process.avg / 1000000000) % 10 + '0'; + 669 .loc 1 128 7 is_stmt 1 view .LVU191 + 128:Core/Src/main.c **** digits[0] = (adc_process.avg / 1000000000) % 10 + '0'; + 670 .loc 1 128 12 is_stmt 0 view .LVU192 + 671 0054 0191 str r1, [sp, #4] + 672 0056 0291 str r1, [sp, #8] + 673 0058 ADF80C10 strh r1, [sp, #12] @ movhi + 129:Core/Src/main.c **** digits[1] = (adc_process.avg / 100000000) % 10 + '0'; + 674 .loc 1 129 7 is_stmt 1 view .LVU193 + 129:Core/Src/main.c **** digits[1] = (adc_process.avg / 100000000) % 10 + '0'; + 675 .loc 1 129 36 is_stmt 0 view .LVU194 + 676 005c 510A lsrs r1, r2, #9 + 677 005e 594B ldr r3, .L32+16 + 678 0060 A3FB0131 umull r3, r1, r3, r1 + 129:Core/Src/main.c **** digits[1] = (adc_process.avg / 100000000) % 10 + '0'; + 679 .loc 1 129 50 view .LVU195 + 680 0064 584B ldr r3, .L32+20 + 681 0066 C909 lsrs r1, r1, #7 + 129:Core/Src/main.c **** digits[1] = (adc_process.avg / 100000000) % 10 + '0'; + 682 .loc 1 129 55 view .LVU196 + 683 0068 3031 adds r1, r1, #48 + 129:Core/Src/main.c **** digits[1] = (adc_process.avg / 100000000) % 10 + '0'; + 684 .loc 1 129 17 view .LVU197 + 685 006a 8DF80410 strb r1, [sp, #4] + ARM GAS /tmp/ccYDS01w.s page 38 - 686 .file 14 "USB_DEVICE/App/usb_device.h" - 687 .file 15 "" - ARM GAS /tmp/cchXeloq.s page 38 + 130:Core/Src/main.c **** digits[2] = (adc_process.avg / 10000000) % 10 + '0'; + 686 .loc 1 130 7 is_stmt 1 view .LVU198 + 130:Core/Src/main.c **** digits[2] = (adc_process.avg / 10000000) % 10 + '0'; + 687 .loc 1 130 36 is_stmt 0 view .LVU199 + 688 006e 5748 ldr r0, .L32+24 + 689 0070 A0FB0210 umull r1, r0, r0, r2 + 690 0074 400E lsrs r0, r0, #25 + 130:Core/Src/main.c **** digits[2] = (adc_process.avg / 10000000) % 10 + '0'; + 691 .loc 1 130 49 view .LVU200 + 692 0076 A3FB00C1 umull ip, r1, r3, r0 + 693 007a C908 lsrs r1, r1, #3 + 694 007c 01EB8101 add r1, r1, r1, lsl #2 + 695 0080 4FEA410C lsl ip, r1, #1 + 696 0084 A0EB0C01 sub r1, r0, ip + 130:Core/Src/main.c **** digits[2] = (adc_process.avg / 10000000) % 10 + '0'; + 697 .loc 1 130 54 view .LVU201 + 698 0088 3031 adds r1, r1, #48 + 130:Core/Src/main.c **** digits[2] = (adc_process.avg / 10000000) % 10 + '0'; + 699 .loc 1 130 17 view .LVU202 + 700 008a 8DF80510 strb r1, [sp, #5] + 131:Core/Src/main.c **** digits[3] = (adc_process.avg / 1000000) % 10 + '0'; + 701 .loc 1 131 7 is_stmt 1 view .LVU203 + 131:Core/Src/main.c **** digits[3] = (adc_process.avg / 1000000) % 10 + '0'; + 702 .loc 1 131 36 is_stmt 0 view .LVU204 + 703 008e 5048 ldr r0, .L32+28 + 704 0090 A0FB0210 umull r1, r0, r0, r2 + 705 0094 800D lsrs r0, r0, #22 + 131:Core/Src/main.c **** digits[3] = (adc_process.avg / 1000000) % 10 + '0'; + 706 .loc 1 131 48 view .LVU205 + 707 0096 A3FB00C1 umull ip, r1, r3, r0 + 708 009a C908 lsrs r1, r1, #3 + 709 009c 01EB8101 add r1, r1, r1, lsl #2 + 710 00a0 4FEA410C lsl ip, r1, #1 + 711 00a4 A0EB0C01 sub r1, r0, ip + 131:Core/Src/main.c **** digits[3] = (adc_process.avg / 1000000) % 10 + '0'; + 712 .loc 1 131 53 view .LVU206 + 713 00a8 3031 adds r1, r1, #48 + 131:Core/Src/main.c **** digits[3] = (adc_process.avg / 1000000) % 10 + '0'; + 714 .loc 1 131 17 view .LVU207 + 715 00aa 8DF80610 strb r1, [sp, #6] + 132:Core/Src/main.c **** digits[4] = (adc_process.avg / 100000) % 10 + '0'; + 716 .loc 1 132 7 is_stmt 1 view .LVU208 + 132:Core/Src/main.c **** digits[4] = (adc_process.avg / 100000) % 10 + '0'; + 717 .loc 1 132 36 is_stmt 0 view .LVU209 + 718 00ae 4948 ldr r0, .L32+32 + 719 00b0 A0FB0210 umull r1, r0, r0, r2 + 720 00b4 800C lsrs r0, r0, #18 + 132:Core/Src/main.c **** digits[4] = (adc_process.avg / 100000) % 10 + '0'; + 721 .loc 1 132 47 view .LVU210 + 722 00b6 A3FB00C1 umull ip, r1, r3, r0 + 723 00ba C908 lsrs r1, r1, #3 + 724 00bc 01EB8101 add r1, r1, r1, lsl #2 + 725 00c0 4FEA410C lsl ip, r1, #1 + 726 00c4 A0EB0C01 sub r1, r0, ip + 132:Core/Src/main.c **** digits[4] = (adc_process.avg / 100000) % 10 + '0'; + 727 .loc 1 132 52 view .LVU211 + 728 00c8 3031 adds r1, r1, #48 + ARM GAS /tmp/ccYDS01w.s page 39 + + + 132:Core/Src/main.c **** digits[4] = (adc_process.avg / 100000) % 10 + '0'; + 729 .loc 1 132 17 view .LVU212 + 730 00ca 8DF80710 strb r1, [sp, #7] + 133:Core/Src/main.c **** digits[5] = (adc_process.avg / 10000) % 10 + '0'; + 731 .loc 1 133 7 is_stmt 1 view .LVU213 + 133:Core/Src/main.c **** digits[5] = (adc_process.avg / 10000) % 10 + '0'; + 732 .loc 1 133 36 is_stmt 0 view .LVU214 + 733 00ce 5009 lsrs r0, r2, #5 + 734 00d0 4149 ldr r1, .L32+36 + 735 00d2 A1FB0010 umull r1, r0, r1, r0 + 736 00d6 C009 lsrs r0, r0, #7 + 133:Core/Src/main.c **** digits[5] = (adc_process.avg / 10000) % 10 + '0'; + 737 .loc 1 133 46 view .LVU215 + 738 00d8 A3FB00C1 umull ip, r1, r3, r0 + 739 00dc C908 lsrs r1, r1, #3 + 740 00de 01EB8101 add r1, r1, r1, lsl #2 + 741 00e2 4FEA410C lsl ip, r1, #1 + 742 00e6 A0EB0C01 sub r1, r0, ip + 133:Core/Src/main.c **** digits[5] = (adc_process.avg / 10000) % 10 + '0'; + 743 .loc 1 133 51 view .LVU216 + 744 00ea 3031 adds r1, r1, #48 + 133:Core/Src/main.c **** digits[5] = (adc_process.avg / 10000) % 10 + '0'; + 745 .loc 1 133 17 view .LVU217 + 746 00ec 8DF80810 strb r1, [sp, #8] + 134:Core/Src/main.c **** digits[6] = (adc_process.avg / 1000) % 10 + '0'; + 747 .loc 1 134 7 is_stmt 1 view .LVU218 + 134:Core/Src/main.c **** digits[6] = (adc_process.avg / 1000) % 10 + '0'; + 748 .loc 1 134 36 is_stmt 0 view .LVU219 + 749 00f0 3A48 ldr r0, .L32+40 + 750 00f2 A0FB0210 umull r1, r0, r0, r2 + 751 00f6 400B lsrs r0, r0, #13 + 134:Core/Src/main.c **** digits[6] = (adc_process.avg / 1000) % 10 + '0'; + 752 .loc 1 134 45 view .LVU220 + 753 00f8 A3FB00C1 umull ip, r1, r3, r0 + 754 00fc C908 lsrs r1, r1, #3 + 755 00fe 01EB8101 add r1, r1, r1, lsl #2 + 756 0102 4FEA410C lsl ip, r1, #1 + 757 0106 A0EB0C01 sub r1, r0, ip + 134:Core/Src/main.c **** digits[6] = (adc_process.avg / 1000) % 10 + '0'; + 758 .loc 1 134 50 view .LVU221 + 759 010a 3031 adds r1, r1, #48 + 134:Core/Src/main.c **** digits[6] = (adc_process.avg / 1000) % 10 + '0'; + 760 .loc 1 134 17 view .LVU222 + 761 010c 8DF80910 strb r1, [sp, #9] + 135:Core/Src/main.c **** digits[7] = (adc_process.avg / 100) % 10 + '0'; + 762 .loc 1 135 7 is_stmt 1 view .LVU223 + 135:Core/Src/main.c **** digits[7] = (adc_process.avg / 100) % 10 + '0'; + 763 .loc 1 135 36 is_stmt 0 view .LVU224 + 764 0110 3348 ldr r0, .L32+44 + 765 0112 A0FB0210 umull r1, r0, r0, r2 + 766 0116 8009 lsrs r0, r0, #6 + 135:Core/Src/main.c **** digits[7] = (adc_process.avg / 100) % 10 + '0'; + 767 .loc 1 135 44 view .LVU225 + 768 0118 A3FB00C1 umull ip, r1, r3, r0 + 769 011c C908 lsrs r1, r1, #3 + 770 011e 01EB8101 add r1, r1, r1, lsl #2 + 771 0122 4FEA410C lsl ip, r1, #1 + ARM GAS /tmp/ccYDS01w.s page 40 + + + 772 0126 A0EB0C01 sub r1, r0, ip + 135:Core/Src/main.c **** digits[7] = (adc_process.avg / 100) % 10 + '0'; + 773 .loc 1 135 49 view .LVU226 + 774 012a 3031 adds r1, r1, #48 + 135:Core/Src/main.c **** digits[7] = (adc_process.avg / 100) % 10 + '0'; + 775 .loc 1 135 17 view .LVU227 + 776 012c 8DF80A10 strb r1, [sp, #10] + 136:Core/Src/main.c **** digits[8] = (adc_process.avg / 10) % 10 + '0'; + 777 .loc 1 136 7 is_stmt 1 view .LVU228 + 136:Core/Src/main.c **** digits[8] = (adc_process.avg / 10) % 10 + '0'; + 778 .loc 1 136 36 is_stmt 0 view .LVU229 + 779 0130 2C48 ldr r0, .L32+48 + 780 0132 A0FB0210 umull r1, r0, r0, r2 + 781 0136 4009 lsrs r0, r0, #5 + 136:Core/Src/main.c **** digits[8] = (adc_process.avg / 10) % 10 + '0'; + 782 .loc 1 136 43 view .LVU230 + 783 0138 A3FB00C1 umull ip, r1, r3, r0 + 784 013c C908 lsrs r1, r1, #3 + 785 013e 01EB8101 add r1, r1, r1, lsl #2 + 786 0142 4FEA410C lsl ip, r1, #1 + 787 0146 A0EB0C01 sub r1, r0, ip + 136:Core/Src/main.c **** digits[8] = (adc_process.avg / 10) % 10 + '0'; + 788 .loc 1 136 48 view .LVU231 + 789 014a 3031 adds r1, r1, #48 + 136:Core/Src/main.c **** digits[8] = (adc_process.avg / 10) % 10 + '0'; + 790 .loc 1 136 17 view .LVU232 + 791 014c 8DF80B10 strb r1, [sp, #11] + 137:Core/Src/main.c **** digits[9] = (adc_process.avg / 1) % 10 + '0'; + 792 .loc 1 137 7 is_stmt 1 view .LVU233 + 137:Core/Src/main.c **** digits[9] = (adc_process.avg / 1) % 10 + '0'; + 793 .loc 1 137 36 is_stmt 0 view .LVU234 + 794 0150 A3FB0201 umull r0, r1, r3, r2 + 795 0154 C908 lsrs r1, r1, #3 + 137:Core/Src/main.c **** digits[9] = (adc_process.avg / 1) % 10 + '0'; + 796 .loc 1 137 42 view .LVU235 + 797 0156 A3FB0103 umull r0, r3, r3, r1 + 798 015a DB08 lsrs r3, r3, #3 + 799 015c 03EB8303 add r3, r3, r3, lsl #2 + 800 0160 5800 lsls r0, r3, #1 + 801 0162 0B1A subs r3, r1, r0 + 137:Core/Src/main.c **** digits[9] = (adc_process.avg / 1) % 10 + '0'; + 802 .loc 1 137 47 view .LVU236 + 803 0164 3033 adds r3, r3, #48 + 137:Core/Src/main.c **** digits[9] = (adc_process.avg / 1) % 10 + '0'; + 804 .loc 1 137 17 view .LVU237 + 805 0166 8DF80C30 strb r3, [sp, #12] + 138:Core/Src/main.c **** + 806 .loc 1 138 7 is_stmt 1 view .LVU238 + 138:Core/Src/main.c **** + 807 .loc 1 138 41 is_stmt 0 view .LVU239 + 808 016a 01EB8101 add r1, r1, r1, lsl #2 + 809 016e 4B00 lsls r3, r1, #1 + 810 0170 D31A subs r3, r2, r3 + 138:Core/Src/main.c **** + 811 .loc 1 138 46 view .LVU240 + 812 0172 3033 adds r3, r3, #48 + 138:Core/Src/main.c **** + ARM GAS /tmp/ccYDS01w.s page 41 + + + 813 .loc 1 138 17 view .LVU241 + 814 0174 8DF80D30 strb r3, [sp, #13] + 140:Core/Src/main.c **** CDC_Transmit_FS((uint8_t *)digits, 10); + 815 .loc 1 140 7 is_stmt 1 view .LVU242 + 816 0178 1821 movs r1, #24 + 817 017a 1B48 ldr r0, .L32+52 + 818 017c FFF7FEFF bl CDC_Transmit_FS + 819 .LVL23: + 141:Core/Src/main.c **** CDC_Transmit_FS((uint8_t *)"\r\n", 2); + 820 .loc 1 141 7 view .LVU243 + 821 0180 0A21 movs r1, #10 + 822 0182 01A8 add r0, sp, #4 + 823 0184 FFF7FEFF bl CDC_Transmit_FS + 824 .LVL24: + 142:Core/Src/main.c **** + 825 .loc 1 142 7 view .LVU244 + 826 0188 0221 movs r1, #2 + 827 018a 1848 ldr r0, .L32+56 + 828 018c FFF7FEFF bl CDC_Transmit_FS + 829 .LVL25: + 830 .L28: + 831 .LBE15: + 145:Core/Src/main.c **** + 832 .loc 1 145 5 view .LVU245 + 833 0190 1321 movs r1, #19 + 834 0192 1748 ldr r0, .L32+60 + 835 0194 FFF7FEFF bl CDC_Transmit_FS + 836 .LVL26: + 837 .LBE14: + 118:Core/Src/main.c **** { + 838 .loc 1 118 9 view .LVU246 + 839 .L29: + 118:Core/Src/main.c **** { + 840 .loc 1 118 3 view .LVU247 + 841 .LBB16: + 120:Core/Src/main.c **** HAL_Delay(100); + 842 .loc 1 120 5 view .LVU248 + 843 0198 4FF48041 mov r1, #16384 + 844 019c 0548 ldr r0, .L32 + 845 019e FFF7FEFF bl HAL_GPIO_TogglePin + 846 .LVL27: + 121:Core/Src/main.c **** + 847 .loc 1 121 5 view .LVU249 + 848 01a2 6420 movs r0, #100 + 849 01a4 FFF7FEFF bl HAL_Delay + 850 .LVL28: + 123:Core/Src/main.c **** adc_process.avg = adc_process.sum / adc_process.N; + 851 .loc 1 123 5 view .LVU250 + 123:Core/Src/main.c **** adc_process.avg = adc_process.sum / adc_process.N; + 852 .loc 1 123 20 is_stmt 0 view .LVU251 + 853 01a8 054B ldr r3, .L32+12 + 854 01aa 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 123:Core/Src/main.c **** adc_process.avg = adc_process.sum / adc_process.N; + 855 .loc 1 123 8 view .LVU252 + 856 01ac 022B cmp r3, #2 + 857 01ae 3FF446AF beq .L31 + 858 01b2 EDE7 b .L28 + ARM GAS /tmp/ccYDS01w.s page 42 + + + 859 .L33: + 860 .align 2 + 861 .L32: + 862 01b4 00040240 .word 1073873920 + 863 01b8 00000000 .word ADC1_buff_circular + 864 01bc 00000000 .word hadc1 + 865 01c0 00000000 .word adc_process + 866 01c4 834B0400 .word 281475 + 867 01c8 CDCCCCCC .word -858993459 + 868 01cc 893BE655 .word 1441151881 + 869 01d0 6BCA5F6B .word 1801439851 + 870 01d4 83DE1B43 .word 1125899907 + 871 01d8 C55A7C0A .word 175921861 + 872 01dc 5917B7D1 .word -776530087 + 873 01e0 D34D6210 .word 274877907 + 874 01e4 1F85EB51 .word 1374389535 + 875 01e8 00000000 .word .LC0 + 876 01ec 1C000000 .word .LC1 + 877 01f0 20000000 .word .LC2 + 878 .LBE16: + 879 .cfi_endproc + 880 .LFE243: + 882 .global ADC1_buff_circular + 883 .section .bss.ADC1_buff_circular,"aw",%nobits + 884 .align 2 + 887 ADC1_buff_circular: + 888 0000 00000000 .space 200 + 888 00000000 + 888 00000000 + 888 00000000 + 888 00000000 + 889 .global adc_process + 890 .section .bss.adc_process,"aw",%nobits + 891 .align 2 + 894 adc_process: + 895 0000 00000000 .space 16 + 895 00000000 + 895 00000000 + 895 00000000 + 896 .global hdma_adc1 + 897 .section .bss.hdma_adc1,"aw",%nobits + 898 .align 2 + 901 hdma_adc1: + 902 0000 00000000 .space 96 + 902 00000000 + 902 00000000 + 902 00000000 + 902 00000000 + 903 .global hadc1 + 904 .section .bss.hadc1,"aw",%nobits + 905 .align 2 + 908 hadc1: + 909 0000 00000000 .space 72 + 909 00000000 + 909 00000000 + 909 00000000 + 909 00000000 + ARM GAS /tmp/ccYDS01w.s page 43 + + + 910 .text + 911 .Letext0: + 912 .file 3 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h" + 913 .file 4 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 914 .file 5 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" + 915 .file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h" + 916 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h" + 917 .file 8 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h" + 918 .file 9 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h" + 919 .file 10 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h" + 920 .file 11 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h" + 921 .file 12 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h" + 922 .file 13 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h" + 923 .file 14 "USB_DEVICE/App/usb_device.h" + 924 .file 15 "" + ARM GAS /tmp/ccYDS01w.s page 44 DEFINED SYMBOLS *ABS*:00000000 main.c - /tmp/cchXeloq.s:21 .text.MX_GPIO_Init:00000000 $t - /tmp/cchXeloq.s:26 .text.MX_GPIO_Init:00000000 MX_GPIO_Init - /tmp/cchXeloq.s:187 .text.MX_GPIO_Init:000000c0 $d - /tmp/cchXeloq.s:194 .text.MX_DMA_Init:00000000 $t - /tmp/cchXeloq.s:199 .text.MX_DMA_Init:00000000 MX_DMA_Init - /tmp/cchXeloq.s:248 .text.MX_DMA_Init:00000030 $d - /tmp/cchXeloq.s:253 .text.Error_Handler:00000000 $t - /tmp/cchXeloq.s:259 .text.Error_Handler:00000000 Error_Handler - /tmp/cchXeloq.s:291 .text.MX_ADC1_Init:00000000 $t - /tmp/cchXeloq.s:296 .text.MX_ADC1_Init:00000000 MX_ADC1_Init - /tmp/cchXeloq.s:404 .text.MX_ADC1_Init:00000068 $d - /tmp/cchXeloq.s:671 .bss.hadc1:00000000 hadc1 - /tmp/cchXeloq.s:410 .text.SystemClock_Config:00000000 $t - /tmp/cchXeloq.s:416 .text.SystemClock_Config:00000000 SystemClock_Config - /tmp/cchXeloq.s:564 .text.SystemClock_Config:000000a4 $d - /tmp/cchXeloq.s:570 .rodata.main.str1.4:00000000 $d - /tmp/cchXeloq.s:574 .text.main:00000000 $t - /tmp/cchXeloq.s:580 .text.main:00000000 main - /tmp/cchXeloq.s:645 .text.main:00000048 $d - /tmp/cchXeloq.s:657 .bss.ADC1_buff_circular:00000000 ADC1_buff_circular - /tmp/cchXeloq.s:654 .bss.ADC1_buff_circular:00000000 $d - /tmp/cchXeloq.s:664 .bss.hdma_adc1:00000000 hdma_adc1 - /tmp/cchXeloq.s:661 .bss.hdma_adc1:00000000 $d - /tmp/cchXeloq.s:668 .bss.hadc1:00000000 $d + /tmp/ccYDS01w.s:21 .text.MX_GPIO_Init:00000000 $t + /tmp/ccYDS01w.s:26 .text.MX_GPIO_Init:00000000 MX_GPIO_Init + /tmp/ccYDS01w.s:187 .text.MX_GPIO_Init:000000c0 $d + /tmp/ccYDS01w.s:194 .text.MX_DMA_Init:00000000 $t + /tmp/ccYDS01w.s:199 .text.MX_DMA_Init:00000000 MX_DMA_Init + /tmp/ccYDS01w.s:248 .text.MX_DMA_Init:00000030 $d + /tmp/ccYDS01w.s:253 .text.Error_Handler:00000000 $t + /tmp/ccYDS01w.s:259 .text.Error_Handler:00000000 Error_Handler + /tmp/ccYDS01w.s:291 .text.MX_ADC1_Init:00000000 $t + /tmp/ccYDS01w.s:296 .text.MX_ADC1_Init:00000000 MX_ADC1_Init + /tmp/ccYDS01w.s:404 .text.MX_ADC1_Init:00000068 $d + /tmp/ccYDS01w.s:908 .bss.hadc1:00000000 hadc1 + /tmp/ccYDS01w.s:410 .text.SystemClock_Config:00000000 $t + /tmp/ccYDS01w.s:416 .text.SystemClock_Config:00000000 SystemClock_Config + /tmp/ccYDS01w.s:564 .text.SystemClock_Config:000000a4 $d + /tmp/ccYDS01w.s:570 .rodata.main.str1.4:00000000 $d + /tmp/ccYDS01w.s:580 .text.main:00000000 $t + /tmp/ccYDS01w.s:586 .text.main:00000000 main + /tmp/ccYDS01w.s:862 .text.main:000001b4 $d + /tmp/ccYDS01w.s:887 .bss.ADC1_buff_circular:00000000 ADC1_buff_circular + /tmp/ccYDS01w.s:894 .bss.adc_process:00000000 adc_process + /tmp/ccYDS01w.s:884 .bss.ADC1_buff_circular:00000000 $d + /tmp/ccYDS01w.s:891 .bss.adc_process:00000000 $d + /tmp/ccYDS01w.s:901 .bss.hdma_adc1:00000000 hdma_adc1 + /tmp/ccYDS01w.s:898 .bss.hdma_adc1:00000000 $d + /tmp/ccYDS01w.s:905 .bss.hadc1:00000000 $d UNDEFINED SYMBOLS HAL_GPIO_WritePin @@ -2206,6 +2581,6 @@ HAL_RCC_ClockConfig HAL_Init MX_USB_DEVICE_Init HAL_ADC_Start_DMA +CDC_Transmit_FS HAL_GPIO_TogglePin HAL_Delay -CDC_Transmit_FS diff --git a/build/main.o b/build/main.o index 476dddc2c1e2d052219128167b09453f73605976..ab6dfdd627d77c0e1905787b6a2ac593cfad95f2 100644 GIT binary patch literal 20912 zcmb7s34EK?mGAu)$=W_gj!oh$1Ua^|5!nDV1gNL!Xt%CH1VfwsfYg*WBVh0+O~^bIXjnE$!oxw351 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