ARM GAS  /tmp/ccUsVHhJ.s 			page 1


   1              		.cpu cortex-m4
   2              		.arch armv7e-m
   3              		.fpu fpv4-sp-d16
   4              		.eabi_attribute 27, 1
   5              		.eabi_attribute 28, 1
   6              		.eabi_attribute 20, 1
   7              		.eabi_attribute 21, 1
   8              		.eabi_attribute 23, 3
   9              		.eabi_attribute 24, 1
  10              		.eabi_attribute 25, 1
  11              		.eabi_attribute 26, 1
  12              		.eabi_attribute 30, 1
  13              		.eabi_attribute 34, 1
  14              		.eabi_attribute 18, 4
  15              		.file	"main.c"
  16              		.text
  17              	.Ltext0:
  18              		.cfi_sections	.debug_frame
  19              		.file 1 "Core/Src/main.c"
  20              		.section	.text.MX_GPIO_Init,"ax",%progbits
  21              		.align	1
  22              		.syntax unified
  23              		.thumb
  24              		.thumb_func
  26              	MX_GPIO_Init:
  27              	.LFB247:
   1:Core/Src/main.c **** /* USER CODE BEGIN Header */
   2:Core/Src/main.c **** /**
   3:Core/Src/main.c ****   ******************************************************************************
   4:Core/Src/main.c ****   * @file           : main.c
   5:Core/Src/main.c ****   * @brief          : Main program body
   6:Core/Src/main.c ****   ******************************************************************************
   7:Core/Src/main.c ****   * @attention
   8:Core/Src/main.c ****   *
   9:Core/Src/main.c ****   * Copyright (c) 2025 STMicroelectronics.
  10:Core/Src/main.c ****   * All rights reserved.
  11:Core/Src/main.c ****   *
  12:Core/Src/main.c ****   * This software is licensed under terms that can be found in the LICENSE file
  13:Core/Src/main.c ****   * in the root directory of this software component.
  14:Core/Src/main.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
  15:Core/Src/main.c ****   *
  16:Core/Src/main.c ****   ******************************************************************************
  17:Core/Src/main.c ****   */
  18:Core/Src/main.c **** /* USER CODE END Header */
  19:Core/Src/main.c **** /* Includes ------------------------------------------------------------------*/
  20:Core/Src/main.c **** #include "main.h"
  21:Core/Src/main.c **** #include "usb_device.h"
  22:Core/Src/main.c **** #include "usbd_cdc_if.h"
  23:Core/Src/main.c **** 
  24:Core/Src/main.c **** /* Private includes ----------------------------------------------------------*/
  25:Core/Src/main.c **** /* USER CODE BEGIN Includes */
  26:Core/Src/main.c **** 
  27:Core/Src/main.c **** /* USER CODE END Includes */
  28:Core/Src/main.c **** 
  29:Core/Src/main.c **** /* Private typedef -----------------------------------------------------------*/
  30:Core/Src/main.c **** /* USER CODE BEGIN PTD */
  31:Core/Src/main.c **** 
ARM GAS  /tmp/ccUsVHhJ.s 			page 2


  32:Core/Src/main.c **** /* USER CODE END PTD */
  33:Core/Src/main.c **** 
  34:Core/Src/main.c **** /* Private define ------------------------------------------------------------*/
  35:Core/Src/main.c **** /* USER CODE BEGIN PD */
  36:Core/Src/main.c **** 
  37:Core/Src/main.c **** /* USER CODE END PD */
  38:Core/Src/main.c **** 
  39:Core/Src/main.c **** /* Private macro -------------------------------------------------------------*/
  40:Core/Src/main.c **** /* USER CODE BEGIN PM */
  41:Core/Src/main.c **** 
  42:Core/Src/main.c **** /* USER CODE END PM */
  43:Core/Src/main.c **** 
  44:Core/Src/main.c **** /* Private variables ---------------------------------------------------------*/
  45:Core/Src/main.c **** ADC_HandleTypeDef hadc1;
  46:Core/Src/main.c **** DMA_HandleTypeDef hdma_adc1;
  47:Core/Src/main.c **** 
  48:Core/Src/main.c **** /* USER CODE BEGIN PV */
  49:Core/Src/main.c **** 
  50:Core/Src/main.c **** /* USER CODE END PV */
  51:Core/Src/main.c **** 
  52:Core/Src/main.c **** /* Private function prototypes -----------------------------------------------*/
  53:Core/Src/main.c **** void SystemClock_Config(void);
  54:Core/Src/main.c **** static void MX_GPIO_Init(void);
  55:Core/Src/main.c **** static void MX_DMA_Init(void);
  56:Core/Src/main.c **** static void MX_ADC1_Init(void);
  57:Core/Src/main.c **** /* USER CODE BEGIN PFP */
  58:Core/Src/main.c **** 
  59:Core/Src/main.c **** /* USER CODE END PFP */
  60:Core/Src/main.c **** 
  61:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/
  62:Core/Src/main.c **** /* USER CODE BEGIN 0 */
  63:Core/Src/main.c **** /* ADC_proc/ADC_proc_shadow/Sweep_state definitions */
  64:Core/Src/main.c **** volatile struct ADC_proc_typedef ADC_proc, ADC_proc_shadow;
  65:Core/Src/main.c **** volatile struct Sweep_state_typedef Sweep_state;
  66:Core/Src/main.c **** volatile uint32_t curr_step_start_N = 0;
  67:Core/Src/main.c **** 
  68:Core/Src/main.c **** /* ADC1 circular DMA buffer definition */
  69:Core/Src/main.c **** uint16_t ADC1_buff_circular[ADC_BUFF_SIZE];
  70:Core/Src/main.c **** char ADC_msg[] = "curr_step   ??????  ??????????\r\n";
  71:Core/Src/main.c **** #define ADC_msg_len 32
  72:Core/Src/main.c **** #define ADC_msg_val_pos 20
  73:Core/Src/main.c **** #define ADC_msg_step_pos 12
  74:Core/Src/main.c **** /* USER CODE END 0 */
  75:Core/Src/main.c **** 
  76:Core/Src/main.c **** /**
  77:Core/Src/main.c ****   * @brief  The application entry point.
  78:Core/Src/main.c ****   * @retval int
  79:Core/Src/main.c ****   */
  80:Core/Src/main.c **** int main(void)
  81:Core/Src/main.c **** {
  82:Core/Src/main.c **** 
  83:Core/Src/main.c ****   /* USER CODE BEGIN 1 */
  84:Core/Src/main.c **** 
  85:Core/Src/main.c ****   /* USER CODE END 1 */
  86:Core/Src/main.c **** 
  87:Core/Src/main.c ****   /* MCU Configuration--------------------------------------------------------*/
  88:Core/Src/main.c **** 
ARM GAS  /tmp/ccUsVHhJ.s 			page 3


  89:Core/Src/main.c ****   /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  90:Core/Src/main.c ****   HAL_Init();
  91:Core/Src/main.c **** 
  92:Core/Src/main.c ****   /* USER CODE BEGIN Init */
  93:Core/Src/main.c **** 
  94:Core/Src/main.c ****   /* USER CODE END Init */
  95:Core/Src/main.c **** 
  96:Core/Src/main.c ****   /* Configure the system clock */
  97:Core/Src/main.c ****   SystemClock_Config();
  98:Core/Src/main.c **** 
  99:Core/Src/main.c ****   /* USER CODE BEGIN SysInit */
 100:Core/Src/main.c **** 
 101:Core/Src/main.c ****   /* USER CODE END SysInit */
 102:Core/Src/main.c **** 
 103:Core/Src/main.c ****   /* Initialize all configured peripherals */
 104:Core/Src/main.c ****   MX_GPIO_Init();
 105:Core/Src/main.c ****   MX_DMA_Init();
 106:Core/Src/main.c ****   MX_ADC1_Init();
 107:Core/Src/main.c ****   MX_USB_DEVICE_Init();
 108:Core/Src/main.c ****   /* USER CODE BEGIN 2 */
 109:Core/Src/main.c ****   HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_SET);
 110:Core/Src/main.c ****   HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADC1_buff_circular, ADC_BUFF_SIZE);
 111:Core/Src/main.c ****   
 112:Core/Src/main.c ****   ADC_proc_shadow.status = 0; // ADC started
 113:Core/Src/main.c ****   ADC_proc_shadow.N = 0;
 114:Core/Src/main.c ****   ADC_proc_shadow.sum = 0;
 115:Core/Src/main.c ****   ADC_proc_shadow.avg = 0;
 116:Core/Src/main.c **** 
 117:Core/Src/main.c ****   ADC_proc.status = 0; // ADC started
 118:Core/Src/main.c ****   ADC_proc.N = 0;
 119:Core/Src/main.c ****   ADC_proc.sum = 0;
 120:Core/Src/main.c ****   ADC_proc.avg = 0;
 121:Core/Src/main.c **** 
 122:Core/Src/main.c ****   uint32_t curr_points_N_max = 100;
 123:Core/Src/main.c ****   uint32_t curr_points_N =0;
 124:Core/Src/main.c **** 
 125:Core/Src/main.c ****   /* USER CODE END 2 */
 126:Core/Src/main.c **** 
 127:Core/Src/main.c ****   /* Infinite loop */
 128:Core/Src/main.c ****   /* USER CODE BEGIN WHILE */
 129:Core/Src/main.c ****   while (1)
 130:Core/Src/main.c ****   {
 131:Core/Src/main.c ****     //HAL_GPIO_TogglePin(LED_RED_GPIO_Port, LED_RED_Pin);
 132:Core/Src/main.c ****     //HAL_Delay(100);
 133:Core/Src/main.c **** 
 134:Core/Src/main.c ****     if (ADC_proc_shadow.status == 2) {
 135:Core/Src/main.c ****       ADC_proc_shadow.avg = ADC_proc_shadow.sum / ADC_proc_shadow.N;
 136:Core/Src/main.c ****       ADC_proc_shadow.status = 1; // reset for next accumulation
 137:Core/Src/main.c ****       ADC_proc_shadow.sum = 0;
 138:Core/Src/main.c ****       ADC_proc_shadow.N = 0;
 139:Core/Src/main.c ****       
 140:Core/Src/main.c ****       
 141:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 0] = (ADC_proc_shadow.avg / 10000000000) % 10 + '0';
 142:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 1] = (ADC_proc_shadow.avg / 1000000000) % 10 +  '0';
 143:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 2] = (ADC_proc_shadow.avg / 10000000) % 10 + '0';
 144:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 3] = (ADC_proc_shadow.avg / 1000000) % 10 + '0';
 145:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 4] = (ADC_proc_shadow.avg / 100000) % 10 + '0';
ARM GAS  /tmp/ccUsVHhJ.s 			page 4


 146:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 5] = (ADC_proc_shadow.avg / 10000) % 10 + '0';
 147:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 6] = (ADC_proc_shadow.avg / 1000) % 10 + '0';
 148:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 7] = (ADC_proc_shadow.avg / 100) % 10 + '0';
 149:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 8] = (ADC_proc_shadow.avg / 10) % 10 + '0';
 150:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 9] = (ADC_proc_shadow.avg / 1) % 10 + '0';
 151:Core/Src/main.c **** 
 152:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 0] = (Sweep_state.curr_step_N / 100000) % 10 + '0';
 153:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 1] = (Sweep_state.curr_step_N / 10000) % 10 + '0';
 154:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 2] = (Sweep_state.curr_step_N / 1000) % 10 + '0';
 155:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 3] = (Sweep_state.curr_step_N / 100) % 10 + '0';
 156:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 4] = (Sweep_state.curr_step_N / 10) % 10 + '0';
 157:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 5] = (Sweep_state.curr_step_N / 1) % 10 + '0';
 158:Core/Src/main.c ****       
 159:Core/Src/main.c **** 
 160:Core/Src/main.c ****       CDC_Transmit_FS((uint8_t *)ADC_msg, ADC_msg_len);
 161:Core/Src/main.c ****       //HAL_GPIO_TogglePin(LED_RED_GPIO_Port, LED_RED_Pin);
 162:Core/Src/main.c ****       
 163:Core/Src/main.c ****       if (Sweep_state.curr_step_N > 1000){
 164:Core/Src/main.c ****         Sweep_state.curr_step_N = 0;
 165:Core/Src/main.c ****         HAL_GPIO_TogglePin(LED_RED_GPIO_Port, LED_RED_Pin);
 166:Core/Src/main.c ****         HAL_DelayUS(10);
 167:Core/Src/main.c ****         CDC_Transmit_FS((uint8_t *)"Sweep_start\n\r", 14);
 168:Core/Src/main.c ****       }
 169:Core/Src/main.c **** 
 170:Core/Src/main.c ****     }
 171:Core/Src/main.c ****     //CDC_Transmit_FS((uint8_t *)"Hello from STM32!\r\n", 19);
 172:Core/Src/main.c ****     
 173:Core/Src/main.c ****     /* USER CODE END WHILE */
 174:Core/Src/main.c **** 
 175:Core/Src/main.c ****     /* USER CODE BEGIN 3 */
 176:Core/Src/main.c ****   }
 177:Core/Src/main.c ****   /* USER CODE END 3 */
 178:Core/Src/main.c **** }
 179:Core/Src/main.c **** 
 180:Core/Src/main.c **** /**
 181:Core/Src/main.c ****   * @brief System Clock Configuration
 182:Core/Src/main.c ****   * @retval None
 183:Core/Src/main.c ****   */
 184:Core/Src/main.c **** void SystemClock_Config(void)
 185:Core/Src/main.c **** {
 186:Core/Src/main.c ****   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 187:Core/Src/main.c ****   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 188:Core/Src/main.c **** 
 189:Core/Src/main.c ****   /** Configure the main internal regulator output voltage
 190:Core/Src/main.c ****   */
 191:Core/Src/main.c ****   __HAL_RCC_PWR_CLK_ENABLE();
 192:Core/Src/main.c ****   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 193:Core/Src/main.c **** 
 194:Core/Src/main.c ****   /** Initializes the RCC Oscillators according to the specified parameters
 195:Core/Src/main.c ****   * in the RCC_OscInitTypeDef structure.
 196:Core/Src/main.c ****   */
 197:Core/Src/main.c ****   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
 198:Core/Src/main.c ****   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
 199:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 200:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
 201:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLM = 8;
 202:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLN = 336;
ARM GAS  /tmp/ccUsVHhJ.s 			page 5


 203:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
 204:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLQ = 7;
 205:Core/Src/main.c ****   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 206:Core/Src/main.c ****   {
 207:Core/Src/main.c ****     Error_Handler();
 208:Core/Src/main.c ****   }
 209:Core/Src/main.c **** 
 210:Core/Src/main.c ****   /** Initializes the CPU, AHB and APB buses clocks
 211:Core/Src/main.c ****   */
 212:Core/Src/main.c ****   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 213:Core/Src/main.c ****                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
 214:Core/Src/main.c ****   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 215:Core/Src/main.c ****   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 216:Core/Src/main.c ****   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
 217:Core/Src/main.c ****   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
 218:Core/Src/main.c **** 
 219:Core/Src/main.c ****   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
 220:Core/Src/main.c ****   {
 221:Core/Src/main.c ****     Error_Handler();
 222:Core/Src/main.c ****   }
 223:Core/Src/main.c **** }
 224:Core/Src/main.c **** 
 225:Core/Src/main.c **** /**
 226:Core/Src/main.c ****   * @brief ADC1 Initialization Function
 227:Core/Src/main.c ****   * @param None
 228:Core/Src/main.c ****   * @retval None
 229:Core/Src/main.c ****   */
 230:Core/Src/main.c **** static void MX_ADC1_Init(void)
 231:Core/Src/main.c **** {
 232:Core/Src/main.c **** 
 233:Core/Src/main.c ****   /* USER CODE BEGIN ADC1_Init 0 */
 234:Core/Src/main.c **** 
 235:Core/Src/main.c ****   /* USER CODE END ADC1_Init 0 */
 236:Core/Src/main.c **** 
 237:Core/Src/main.c ****   ADC_ChannelConfTypeDef sConfig = {0};
 238:Core/Src/main.c **** 
 239:Core/Src/main.c ****   /* USER CODE BEGIN ADC1_Init 1 */
 240:Core/Src/main.c **** 
 241:Core/Src/main.c ****   /* USER CODE END ADC1_Init 1 */
 242:Core/Src/main.c **** 
 243:Core/Src/main.c ****   /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of con
 244:Core/Src/main.c ****   */
 245:Core/Src/main.c ****   hadc1.Instance = ADC1;
 246:Core/Src/main.c ****   hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
 247:Core/Src/main.c ****   hadc1.Init.Resolution = ADC_RESOLUTION_12B;
 248:Core/Src/main.c ****   hadc1.Init.ScanConvMode = DISABLE;
 249:Core/Src/main.c ****   hadc1.Init.ContinuousConvMode = DISABLE;
 250:Core/Src/main.c ****   hadc1.Init.DiscontinuousConvMode = DISABLE;
 251:Core/Src/main.c ****   hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
 252:Core/Src/main.c ****   hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_Ext_IT11;
 253:Core/Src/main.c ****   hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
 254:Core/Src/main.c ****   hadc1.Init.NbrOfConversion = 1;
 255:Core/Src/main.c ****   hadc1.Init.DMAContinuousRequests = ENABLE;
 256:Core/Src/main.c ****   hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
 257:Core/Src/main.c ****   if (HAL_ADC_Init(&hadc1) != HAL_OK)
 258:Core/Src/main.c ****   {
 259:Core/Src/main.c ****     Error_Handler();
ARM GAS  /tmp/ccUsVHhJ.s 			page 6


 260:Core/Src/main.c ****   }
 261:Core/Src/main.c **** 
 262:Core/Src/main.c ****   /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it
 263:Core/Src/main.c ****   */
 264:Core/Src/main.c ****   sConfig.Channel = ADC_CHANNEL_3;
 265:Core/Src/main.c ****   sConfig.Rank = 1;
 266:Core/Src/main.c ****   sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
 267:Core/Src/main.c ****   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 268:Core/Src/main.c ****   {
 269:Core/Src/main.c ****     Error_Handler();
 270:Core/Src/main.c ****   }
 271:Core/Src/main.c ****   /* USER CODE BEGIN ADC1_Init 2 */
 272:Core/Src/main.c **** 
 273:Core/Src/main.c ****   /* USER CODE END ADC1_Init 2 */
 274:Core/Src/main.c **** 
 275:Core/Src/main.c **** }
 276:Core/Src/main.c **** 
 277:Core/Src/main.c **** /**
 278:Core/Src/main.c ****   * Enable DMA controller clock
 279:Core/Src/main.c ****   */
 280:Core/Src/main.c **** static void MX_DMA_Init(void)
 281:Core/Src/main.c **** {
 282:Core/Src/main.c **** 
 283:Core/Src/main.c ****   /* DMA controller clock enable */
 284:Core/Src/main.c ****   __HAL_RCC_DMA2_CLK_ENABLE();
 285:Core/Src/main.c **** 
 286:Core/Src/main.c ****   /* DMA interrupt init */
 287:Core/Src/main.c ****   /* DMA2_Stream0_IRQn interrupt configuration */
 288:Core/Src/main.c ****   HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 0, 0);
 289:Core/Src/main.c ****   HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn);
 290:Core/Src/main.c **** 
 291:Core/Src/main.c **** }
 292:Core/Src/main.c **** 
 293:Core/Src/main.c **** /**
 294:Core/Src/main.c ****   * @brief GPIO Initialization Function
 295:Core/Src/main.c ****   * @param None
 296:Core/Src/main.c ****   * @retval None
 297:Core/Src/main.c ****   */
 298:Core/Src/main.c **** static void MX_GPIO_Init(void)
 299:Core/Src/main.c **** {
  28              		.loc 1 299 1 view -0
  29              		.cfi_startproc
  30              		@ args = 0, pretend = 0, frame = 40
  31              		@ frame_needed = 0, uses_anonymous_args = 0
  32 0000 2DE9F043 		push	{r4, r5, r6, r7, r8, r9, lr}
  33              	.LCFI0:
  34              		.cfi_def_cfa_offset 28
  35              		.cfi_offset 4, -28
  36              		.cfi_offset 5, -24
  37              		.cfi_offset 6, -20
  38              		.cfi_offset 7, -16
  39              		.cfi_offset 8, -12
  40              		.cfi_offset 9, -8
  41              		.cfi_offset 14, -4
  42 0004 8BB0     		sub	sp, sp, #44
  43              	.LCFI1:
  44              		.cfi_def_cfa_offset 72
ARM GAS  /tmp/ccUsVHhJ.s 			page 7


 300:Core/Src/main.c ****   GPIO_InitTypeDef GPIO_InitStruct = {0};
  45              		.loc 1 300 3 view .LVU1
  46              		.loc 1 300 20 is_stmt 0 view .LVU2
  47 0006 0024     		movs	r4, #0
  48 0008 0594     		str	r4, [sp, #20]
  49 000a 0694     		str	r4, [sp, #24]
  50 000c 0794     		str	r4, [sp, #28]
  51 000e 0894     		str	r4, [sp, #32]
  52 0010 0994     		str	r4, [sp, #36]
 301:Core/Src/main.c ****   /* USER CODE BEGIN MX_GPIO_Init_1 */
 302:Core/Src/main.c **** 
 303:Core/Src/main.c ****   /* USER CODE END MX_GPIO_Init_1 */
 304:Core/Src/main.c **** 
 305:Core/Src/main.c ****   /* GPIO Ports Clock Enable */
 306:Core/Src/main.c ****   __HAL_RCC_GPIOH_CLK_ENABLE();
  53              		.loc 1 306 3 is_stmt 1 view .LVU3
  54              	.LBB4:
  55              		.loc 1 306 3 view .LVU4
  56 0012 0094     		str	r4, [sp]
  57              		.loc 1 306 3 view .LVU5
  58 0014 3D4B     		ldr	r3, .L3
  59 0016 1A6B     		ldr	r2, [r3, #48]
  60 0018 42F08002 		orr	r2, r2, #128
  61 001c 1A63     		str	r2, [r3, #48]
  62              		.loc 1 306 3 view .LVU6
  63 001e 1A6B     		ldr	r2, [r3, #48]
  64 0020 02F08002 		and	r2, r2, #128
  65 0024 0092     		str	r2, [sp]
  66              		.loc 1 306 3 view .LVU7
  67 0026 009A     		ldr	r2, [sp]
  68              	.LBE4:
  69              		.loc 1 306 3 view .LVU8
 307:Core/Src/main.c ****   __HAL_RCC_GPIOC_CLK_ENABLE();
  70              		.loc 1 307 3 view .LVU9
  71              	.LBB5:
  72              		.loc 1 307 3 view .LVU10
  73 0028 0194     		str	r4, [sp, #4]
  74              		.loc 1 307 3 view .LVU11
  75 002a 1A6B     		ldr	r2, [r3, #48]
  76 002c 42F00402 		orr	r2, r2, #4
  77 0030 1A63     		str	r2, [r3, #48]
  78              		.loc 1 307 3 view .LVU12
  79 0032 1A6B     		ldr	r2, [r3, #48]
  80 0034 02F00402 		and	r2, r2, #4
  81 0038 0192     		str	r2, [sp, #4]
  82              		.loc 1 307 3 view .LVU13
  83 003a 019A     		ldr	r2, [sp, #4]
  84              	.LBE5:
  85              		.loc 1 307 3 view .LVU14
 308:Core/Src/main.c ****   __HAL_RCC_GPIOA_CLK_ENABLE();
  86              		.loc 1 308 3 view .LVU15
  87              	.LBB6:
  88              		.loc 1 308 3 view .LVU16
  89 003c 0294     		str	r4, [sp, #8]
  90              		.loc 1 308 3 view .LVU17
  91 003e 1A6B     		ldr	r2, [r3, #48]
  92 0040 42F00102 		orr	r2, r2, #1
ARM GAS  /tmp/ccUsVHhJ.s 			page 8


  93 0044 1A63     		str	r2, [r3, #48]
  94              		.loc 1 308 3 view .LVU18
  95 0046 1A6B     		ldr	r2, [r3, #48]
  96 0048 02F00102 		and	r2, r2, #1
  97 004c 0292     		str	r2, [sp, #8]
  98              		.loc 1 308 3 view .LVU19
  99 004e 029A     		ldr	r2, [sp, #8]
 100              	.LBE6:
 101              		.loc 1 308 3 view .LVU20
 309:Core/Src/main.c ****   __HAL_RCC_GPIOF_CLK_ENABLE();
 102              		.loc 1 309 3 view .LVU21
 103              	.LBB7:
 104              		.loc 1 309 3 view .LVU22
 105 0050 0394     		str	r4, [sp, #12]
 106              		.loc 1 309 3 view .LVU23
 107 0052 1A6B     		ldr	r2, [r3, #48]
 108 0054 42F02002 		orr	r2, r2, #32
 109 0058 1A63     		str	r2, [r3, #48]
 110              		.loc 1 309 3 view .LVU24
 111 005a 1A6B     		ldr	r2, [r3, #48]
 112 005c 02F02002 		and	r2, r2, #32
 113 0060 0392     		str	r2, [sp, #12]
 114              		.loc 1 309 3 view .LVU25
 115 0062 039A     		ldr	r2, [sp, #12]
 116              	.LBE7:
 117              		.loc 1 309 3 view .LVU26
 310:Core/Src/main.c ****   __HAL_RCC_GPIOB_CLK_ENABLE();
 118              		.loc 1 310 3 view .LVU27
 119              	.LBB8:
 120              		.loc 1 310 3 view .LVU28
 121 0064 0494     		str	r4, [sp, #16]
 122              		.loc 1 310 3 view .LVU29
 123 0066 1A6B     		ldr	r2, [r3, #48]
 124 0068 42F00202 		orr	r2, r2, #2
 125 006c 1A63     		str	r2, [r3, #48]
 126              		.loc 1 310 3 view .LVU30
 127 006e 1B6B     		ldr	r3, [r3, #48]
 128 0070 03F00203 		and	r3, r3, #2
 129 0074 0493     		str	r3, [sp, #16]
 130              		.loc 1 310 3 view .LVU31
 131 0076 049B     		ldr	r3, [sp, #16]
 132              	.LBE8:
 133              		.loc 1 310 3 view .LVU32
 311:Core/Src/main.c **** 
 312:Core/Src/main.c ****   /*Configure GPIO pin Output Level */
 313:Core/Src/main.c ****   HAL_GPIO_WritePin(LED_RED_GPIO_Port, LED_RED_Pin, GPIO_PIN_RESET);
 134              		.loc 1 313 3 view .LVU33
 135 0078 254D     		ldr	r5, .L3+4
 136 007a 2246     		mov	r2, r4
 137 007c 4FF48041 		mov	r1, #16384
 138 0080 2846     		mov	r0, r5
 139 0082 FFF7FEFF 		bl	HAL_GPIO_WritePin
 140              	.LVL0:
 314:Core/Src/main.c **** 
 315:Core/Src/main.c ****   /*Configure GPIO pin Output Level */
 316:Core/Src/main.c ****   HAL_GPIO_WritePin(LED_BLUE_GPIO_Port, LED_BLUE_Pin, GPIO_PIN_SET);
 141              		.loc 1 316 3 view .LVU34
ARM GAS  /tmp/ccUsVHhJ.s 			page 9


 142 0086 0122     		movs	r2, #1
 143 0088 8021     		movs	r1, #128
 144 008a 2846     		mov	r0, r5
 145 008c FFF7FEFF 		bl	HAL_GPIO_WritePin
 146              	.LVL1:
 317:Core/Src/main.c **** 
 318:Core/Src/main.c ****   /*Configure GPIO pin : CURR_STEP_START_TRG_Pin */
 319:Core/Src/main.c ****   GPIO_InitStruct.Pin = CURR_STEP_START_TRG_Pin;
 147              		.loc 1 319 3 view .LVU35
 148              		.loc 1 319 23 is_stmt 0 view .LVU36
 149 0090 0127     		movs	r7, #1
 150 0092 0597     		str	r7, [sp, #20]
 320:Core/Src/main.c ****   GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
 151              		.loc 1 320 3 is_stmt 1 view .LVU37
 152              		.loc 1 320 24 is_stmt 0 view .LVU38
 153 0094 4FF44413 		mov	r3, #3211264
 154 0098 0693     		str	r3, [sp, #24]
 321:Core/Src/main.c ****   GPIO_InitStruct.Pull = GPIO_PULLDOWN;
 155              		.loc 1 321 3 is_stmt 1 view .LVU39
 156              		.loc 1 321 24 is_stmt 0 view .LVU40
 157 009a 0226     		movs	r6, #2
 158 009c 0796     		str	r6, [sp, #28]
 322:Core/Src/main.c ****   HAL_GPIO_Init(CURR_STEP_START_TRG_GPIO_Port, &GPIO_InitStruct);
 159              		.loc 1 322 3 is_stmt 1 view .LVU41
 160 009e DFF87890 		ldr	r9, .L3+12
 161 00a2 05A9     		add	r1, sp, #20
 162 00a4 4846     		mov	r0, r9
 163 00a6 FFF7FEFF 		bl	HAL_GPIO_Init
 164              	.LVL2:
 323:Core/Src/main.c **** 
 324:Core/Src/main.c ****   /*Configure GPIO pin : SWEEP_CYCLE_START_TRG_Pin */
 325:Core/Src/main.c ****   GPIO_InitStruct.Pin = SWEEP_CYCLE_START_TRG_Pin;
 165              		.loc 1 325 3 view .LVU42
 166              		.loc 1 325 23 is_stmt 0 view .LVU43
 167 00aa 0596     		str	r6, [sp, #20]
 326:Core/Src/main.c ****   GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
 168              		.loc 1 326 3 is_stmt 1 view .LVU44
 169              		.loc 1 326 24 is_stmt 0 view .LVU45
 170 00ac 4FF48818 		mov	r8, #1114112
 171 00b0 CDF81880 		str	r8, [sp, #24]
 327:Core/Src/main.c ****   GPIO_InitStruct.Pull = GPIO_PULLDOWN;
 172              		.loc 1 327 3 is_stmt 1 view .LVU46
 173              		.loc 1 327 24 is_stmt 0 view .LVU47
 174 00b4 0796     		str	r6, [sp, #28]
 328:Core/Src/main.c ****   HAL_GPIO_Init(SWEEP_CYCLE_START_TRG_GPIO_Port, &GPIO_InitStruct);
 175              		.loc 1 328 3 is_stmt 1 view .LVU48
 176 00b6 05A9     		add	r1, sp, #20
 177 00b8 4846     		mov	r0, r9
 178 00ba FFF7FEFF 		bl	HAL_GPIO_Init
 179              	.LVL3:
 329:Core/Src/main.c **** 
 330:Core/Src/main.c ****   /*Configure GPIO pin : PF11 */
 331:Core/Src/main.c ****   GPIO_InitStruct.Pin = GPIO_PIN_11;
 180              		.loc 1 331 3 view .LVU49
 181              		.loc 1 331 23 is_stmt 0 view .LVU50
 182 00be 4FF40063 		mov	r3, #2048
 183 00c2 0593     		str	r3, [sp, #20]
ARM GAS  /tmp/ccUsVHhJ.s 			page 10


 332:Core/Src/main.c ****   GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
 184              		.loc 1 332 3 is_stmt 1 view .LVU51
 185              		.loc 1 332 24 is_stmt 0 view .LVU52
 186 00c4 CDF81880 		str	r8, [sp, #24]
 333:Core/Src/main.c ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
 187              		.loc 1 333 3 is_stmt 1 view .LVU53
 188              		.loc 1 333 24 is_stmt 0 view .LVU54
 189 00c8 0794     		str	r4, [sp, #28]
 334:Core/Src/main.c ****   HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
 190              		.loc 1 334 3 is_stmt 1 view .LVU55
 191 00ca 05A9     		add	r1, sp, #20
 192 00cc 1148     		ldr	r0, .L3+8
 193 00ce FFF7FEFF 		bl	HAL_GPIO_Init
 194              	.LVL4:
 335:Core/Src/main.c **** 
 336:Core/Src/main.c ****   /*Configure GPIO pins : LED_RED_Pin LED_BLUE_Pin */
 337:Core/Src/main.c ****   GPIO_InitStruct.Pin = LED_RED_Pin|LED_BLUE_Pin;
 195              		.loc 1 337 3 view .LVU56
 196              		.loc 1 337 23 is_stmt 0 view .LVU57
 197 00d2 4FF48143 		mov	r3, #16512
 198 00d6 0593     		str	r3, [sp, #20]
 338:Core/Src/main.c ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 199              		.loc 1 338 3 is_stmt 1 view .LVU58
 200              		.loc 1 338 24 is_stmt 0 view .LVU59
 201 00d8 0697     		str	r7, [sp, #24]
 339:Core/Src/main.c ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
 202              		.loc 1 339 3 is_stmt 1 view .LVU60
 203              		.loc 1 339 24 is_stmt 0 view .LVU61
 204 00da 0794     		str	r4, [sp, #28]
 340:Core/Src/main.c ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 205              		.loc 1 340 3 is_stmt 1 view .LVU62
 206              		.loc 1 340 25 is_stmt 0 view .LVU63
 207 00dc 0894     		str	r4, [sp, #32]
 341:Core/Src/main.c ****   HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 208              		.loc 1 341 3 is_stmt 1 view .LVU64
 209 00de 05A9     		add	r1, sp, #20
 210 00e0 2846     		mov	r0, r5
 211 00e2 FFF7FEFF 		bl	HAL_GPIO_Init
 212              	.LVL5:
 342:Core/Src/main.c **** 
 343:Core/Src/main.c ****   /* EXTI interrupt init*/
 344:Core/Src/main.c ****   HAL_NVIC_SetPriority(EXTI0_IRQn, 0, 0);
 213              		.loc 1 344 3 view .LVU65
 214 00e6 2246     		mov	r2, r4
 215 00e8 2146     		mov	r1, r4
 216 00ea 0620     		movs	r0, #6
 217 00ec FFF7FEFF 		bl	HAL_NVIC_SetPriority
 218              	.LVL6:
 345:Core/Src/main.c ****   HAL_NVIC_EnableIRQ(EXTI0_IRQn);
 219              		.loc 1 345 3 view .LVU66
 220 00f0 0620     		movs	r0, #6
 221 00f2 FFF7FEFF 		bl	HAL_NVIC_EnableIRQ
 222              	.LVL7:
 346:Core/Src/main.c **** 
 347:Core/Src/main.c ****   HAL_NVIC_SetPriority(EXTI3_IRQn, 0, 0);
 223              		.loc 1 347 3 view .LVU67
 224 00f6 2246     		mov	r2, r4
ARM GAS  /tmp/ccUsVHhJ.s 			page 11


 225 00f8 2146     		mov	r1, r4
 226 00fa 0920     		movs	r0, #9
 227 00fc FFF7FEFF 		bl	HAL_NVIC_SetPriority
 228              	.LVL8:
 348:Core/Src/main.c ****   HAL_NVIC_EnableIRQ(EXTI3_IRQn);
 229              		.loc 1 348 3 view .LVU68
 230 0100 0920     		movs	r0, #9
 231 0102 FFF7FEFF 		bl	HAL_NVIC_EnableIRQ
 232              	.LVL9:
 349:Core/Src/main.c **** 
 350:Core/Src/main.c ****   /* USER CODE BEGIN MX_GPIO_Init_2 */
 351:Core/Src/main.c **** 
 352:Core/Src/main.c ****   /* USER CODE END MX_GPIO_Init_2 */
 353:Core/Src/main.c **** }
 233              		.loc 1 353 1 is_stmt 0 view .LVU69
 234 0106 0BB0     		add	sp, sp, #44
 235              	.LCFI2:
 236              		.cfi_def_cfa_offset 28
 237              		@ sp needed
 238 0108 BDE8F083 		pop	{r4, r5, r6, r7, r8, r9, pc}
 239              	.L4:
 240              		.align	2
 241              	.L3:
 242 010c 00380240 		.word	1073887232
 243 0110 00040240 		.word	1073873920
 244 0114 00140240 		.word	1073878016
 245 0118 00080240 		.word	1073874944
 246              		.cfi_endproc
 247              	.LFE247:
 249              		.section	.text.MX_DMA_Init,"ax",%progbits
 250              		.align	1
 251              		.syntax unified
 252              		.thumb
 253              		.thumb_func
 255              	MX_DMA_Init:
 256              	.LFB246:
 281:Core/Src/main.c **** 
 257              		.loc 1 281 1 is_stmt 1 view -0
 258              		.cfi_startproc
 259              		@ args = 0, pretend = 0, frame = 8
 260              		@ frame_needed = 0, uses_anonymous_args = 0
 261 0000 00B5     		push	{lr}
 262              	.LCFI3:
 263              		.cfi_def_cfa_offset 4
 264              		.cfi_offset 14, -4
 265 0002 83B0     		sub	sp, sp, #12
 266              	.LCFI4:
 267              		.cfi_def_cfa_offset 16
 284:Core/Src/main.c **** 
 268              		.loc 1 284 3 view .LVU71
 269              	.LBB9:
 284:Core/Src/main.c **** 
 270              		.loc 1 284 3 view .LVU72
 271 0004 0021     		movs	r1, #0
 272 0006 0191     		str	r1, [sp, #4]
 284:Core/Src/main.c **** 
 273              		.loc 1 284 3 view .LVU73
ARM GAS  /tmp/ccUsVHhJ.s 			page 12


 274 0008 094B     		ldr	r3, .L7
 275 000a 1A6B     		ldr	r2, [r3, #48]
 276 000c 42F48002 		orr	r2, r2, #4194304
 277 0010 1A63     		str	r2, [r3, #48]
 284:Core/Src/main.c **** 
 278              		.loc 1 284 3 view .LVU74
 279 0012 1B6B     		ldr	r3, [r3, #48]
 280 0014 03F48003 		and	r3, r3, #4194304
 281 0018 0193     		str	r3, [sp, #4]
 284:Core/Src/main.c **** 
 282              		.loc 1 284 3 view .LVU75
 283 001a 019B     		ldr	r3, [sp, #4]
 284              	.LBE9:
 284:Core/Src/main.c **** 
 285              		.loc 1 284 3 view .LVU76
 288:Core/Src/main.c ****   HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn);
 286              		.loc 1 288 3 view .LVU77
 287 001c 0A46     		mov	r2, r1
 288 001e 3820     		movs	r0, #56
 289 0020 FFF7FEFF 		bl	HAL_NVIC_SetPriority
 290              	.LVL10:
 289:Core/Src/main.c **** 
 291              		.loc 1 289 3 view .LVU78
 292 0024 3820     		movs	r0, #56
 293 0026 FFF7FEFF 		bl	HAL_NVIC_EnableIRQ
 294              	.LVL11:
 291:Core/Src/main.c **** 
 295              		.loc 1 291 1 is_stmt 0 view .LVU79
 296 002a 03B0     		add	sp, sp, #12
 297              	.LCFI5:
 298              		.cfi_def_cfa_offset 4
 299              		@ sp needed
 300 002c 5DF804FB 		ldr	pc, [sp], #4
 301              	.L8:
 302              		.align	2
 303              	.L7:
 304 0030 00380240 		.word	1073887232
 305              		.cfi_endproc
 306              	.LFE246:
 308              		.section	.text.Error_Handler,"ax",%progbits
 309              		.align	1
 310              		.global	Error_Handler
 311              		.syntax unified
 312              		.thumb
 313              		.thumb_func
 315              	Error_Handler:
 316              	.LFB248:
 354:Core/Src/main.c **** 
 355:Core/Src/main.c **** /* USER CODE BEGIN 4 */
 356:Core/Src/main.c **** 
 357:Core/Src/main.c **** /* USER CODE END 4 */
 358:Core/Src/main.c **** 
 359:Core/Src/main.c **** /**
 360:Core/Src/main.c ****   * @brief  This function is executed in case of error occurrence.
 361:Core/Src/main.c ****   * @retval None
 362:Core/Src/main.c ****   */
 363:Core/Src/main.c **** void Error_Handler(void)
ARM GAS  /tmp/ccUsVHhJ.s 			page 13


 364:Core/Src/main.c **** {
 317              		.loc 1 364 1 is_stmt 1 view -0
 318              		.cfi_startproc
 319              		@ Volatile: function does not return.
 320              		@ args = 0, pretend = 0, frame = 0
 321              		@ frame_needed = 0, uses_anonymous_args = 0
 322              		@ link register save eliminated.
 365:Core/Src/main.c ****   /* USER CODE BEGIN Error_Handler_Debug */
 366:Core/Src/main.c ****   /* User can add his own implementation to report the HAL error return state */
 367:Core/Src/main.c ****   __disable_irq();
 323              		.loc 1 367 3 view .LVU81
 324              	.LBB10:
 325              	.LBI10:
 326              		.file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.4.1
   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     27. May 2021
   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
ARM GAS  /tmp/ccUsVHhJ.s 			page 14


  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE
  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
ARM GAS  /tmp/ccUsVHhJ.s 			page 15


 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __COMPILER_BARRIER
 117:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 119:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* #########################  Startup and Lowlevel Init  ######################## */
 121:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START
 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Initializes data and bss sections
 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details This default implementations initialized all data and additional bss
 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            sections relying on .copy.table and .zero.table specified properly
 128:Drivers/CMSIS/Include/cmsis_gcc.h ****            in the used linker script.
 129:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 130:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
 132:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 133:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern void _start(void) __NO_RETURN;
 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 135:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
 136:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t const* src;
 137:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
 138:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
 139:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __copy_table_t;
 140:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 141:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
 142:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
 143:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
 144:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __zero_table_t;
 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 146:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_start__;
 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_end__;
 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_start__;
 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_end__;
 150:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 151:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
 152:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 153:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = pTable->src[i];
 154:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 156:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 157:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
ARM GAS  /tmp/ccUsVHhJ.s 			page 16


 158:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 159:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = 0u;
 160:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
 161:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 162:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   _start();
 164:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 165:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START           __cmsis_start
 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 168:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP
 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP              __StackTop
 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 172:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT
 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT             __StackLimit
 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 176:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE            __Vectors
 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 180:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(".vectors")))
 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 184:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 185:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
 186:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_SEAL
 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_SEAL              __StackSeal
 188:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 189:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 190:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_SIZE
 191:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __TZ_STACK_SEAL_SIZE      8U
 192:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 193:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 194:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_VALUE
 195:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL
 196:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 197:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 199:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
 200:Drivers/CMSIS/Include/cmsis_gcc.h ****   *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
 201:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 202:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 203:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 205:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
 206:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
 207:Drivers/CMSIS/Include/cmsis_gcc.h ****   Access to dedicated instructions
 208:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
 209:Drivers/CMSIS/Include/cmsis_gcc.h **** */
 210:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 211:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
 212:Drivers/CMSIS/Include/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
 213:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
 214:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
ARM GAS  /tmp/ccUsVHhJ.s 			page 17


 215:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
 216:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
 217:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
 218:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 219:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
 220:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
 221:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
 222:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 223:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 224:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 225:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   No Operation
 226:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
 227:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 228:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
 229:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 230:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 231:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Interrupt
 232:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
 233:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 234:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi":::"memory")
 235:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 237:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 238:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Event
 239:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
 240:Drivers/CMSIS/Include/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
 241:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 242:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe":::"memory")
 243:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 244:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 245:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 246:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Send Event
 247:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
 248:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 249:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 251:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 252:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 253:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
 254:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
 255:Drivers/CMSIS/Include/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
 256:Drivers/CMSIS/Include/cmsis_gcc.h ****            after the instruction has been completed.
 257:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 258:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
 259:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 260:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
 261:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 262:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 263:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 264:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 265:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
 266:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
 267:Drivers/CMSIS/Include/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
 268:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 269:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
 270:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 271:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
ARM GAS  /tmp/ccUsVHhJ.s 			page 18


 272:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 273:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 274:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 275:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 276:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Memory Barrier
 277:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
 278:Drivers/CMSIS/Include/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
 279:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 280:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
 281:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 282:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
 283:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 284:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 285:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 286:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 287:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (32 bit)
 288:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785
 289:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 290:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
 291:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 292:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
 293:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 294:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
 295:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_bswap32(value);
 296:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 297:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 298:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 299:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 300:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
 301:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 302:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 303:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 304:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 305:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 306:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
 307:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 
 308:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 309:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
 310:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 311:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
 312:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 313:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 314:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 315:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 316:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
 317:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 318:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 319:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 320:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 321:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
 322:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam
 323:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 324:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
 325:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 326:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
 327:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 328:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
ARM GAS  /tmp/ccUsVHhJ.s 			page 19


 329:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (int16_t)__builtin_bswap16(value);
 330:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 331:Drivers/CMSIS/Include/cmsis_gcc.h ****   int16_t result;
 332:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 333:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 334:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
 335:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 336:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 337:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 338:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 339:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 340:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Rotate Right in unsigned value (32 bit)
 341:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
 342:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    op1  Value to rotate
 343:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    op2  Number of Bits to rotate
 344:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Rotated value
 345:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 346:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
 347:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 348:Drivers/CMSIS/Include/cmsis_gcc.h ****   op2 %= 32U;
 349:Drivers/CMSIS/Include/cmsis_gcc.h ****   if (op2 == 0U)
 350:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
 351:Drivers/CMSIS/Include/cmsis_gcc.h ****     return op1;
 352:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 353:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (op1 >> op2) | (op1 << (32U - op2));
 354:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 355:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 356:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 357:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 358:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Breakpoint
 359:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Causes the processor to enter Debug state.
 360:Drivers/CMSIS/Include/cmsis_gcc.h ****            Debug tools can use this to investigate system state when the instruction at a particula
 361:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  is ignored by the processor.
 362:Drivers/CMSIS/Include/cmsis_gcc.h ****                  If required, a debugger can use it to store additional information about the break
 363:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 364:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
 365:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 366:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 367:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 368:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse bit order of value
 369:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the bit order of the given value.
 370:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 371:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
 372:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 373:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
 374:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 375:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 377:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 378:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 379:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
 380:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
 381:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 382:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
 383:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 384:Drivers/CMSIS/Include/cmsis_gcc.h ****   result = value;                      /* r will be reversed bits of v; first get LSB of v */
 385:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (value >>= 1U; value != 0U; value >>= 1U)
ARM GAS  /tmp/ccUsVHhJ.s 			page 20


 386:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
 387:Drivers/CMSIS/Include/cmsis_gcc.h ****     result <<= 1U;
 388:Drivers/CMSIS/Include/cmsis_gcc.h ****     result |= value & 1U;
 389:Drivers/CMSIS/Include/cmsis_gcc.h ****     s--;
 390:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 391:Drivers/CMSIS/Include/cmsis_gcc.h ****   result <<= s;                        /* shift when v's highest bits are zero */
 392:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 393:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
 394:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 395:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 396:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 397:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 398:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Count leading zeros
 399:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Counts the number of leading zeros of a data value.
 400:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to count the leading zeros
 401:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return             number of leading zeros in value
 402:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 403:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
 404:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 405:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
 406:Drivers/CMSIS/Include/cmsis_gcc.h ****      __builtin_clz(0) is undefined behaviour, so handle this case specially.
 407:Drivers/CMSIS/Include/cmsis_gcc.h ****      This guarantees ARM-compatible results if happening to compile on a non-ARM
 408:Drivers/CMSIS/Include/cmsis_gcc.h ****      target, and ensures the compiler doesn't decide to activate any
 409:Drivers/CMSIS/Include/cmsis_gcc.h ****      optimisations using the logic "value was passed to __builtin_clz, so it
 410:Drivers/CMSIS/Include/cmsis_gcc.h ****      is non-zero".
 411:Drivers/CMSIS/Include/cmsis_gcc.h ****      ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
 412:Drivers/CMSIS/Include/cmsis_gcc.h ****      single CLZ instruction.
 413:Drivers/CMSIS/Include/cmsis_gcc.h ****    */
 414:Drivers/CMSIS/Include/cmsis_gcc.h ****   if (value == 0U)
 415:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
 416:Drivers/CMSIS/Include/cmsis_gcc.h ****     return 32U;
 417:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 418:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_clz(value);
 419:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 420:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 421:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 422:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 423:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 424:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 425:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
 426:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 427:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   LDR Exclusive (8 bit)
 428:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 8 bit value.
 429:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 430:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 431:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 432:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
 433:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 434:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
 435:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 436:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 437:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
 438:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 439:Drivers/CMSIS/Include/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 440:Drivers/CMSIS/Include/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 441:Drivers/CMSIS/Include/cmsis_gcc.h ****     */
 442:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
ARM GAS  /tmp/ccUsVHhJ.s 			page 21


 443:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 444:Drivers/CMSIS/Include/cmsis_gcc.h ****    return ((uint8_t) result);    /* Add explicit type cast here */
 445:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 446:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 447:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 448:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 449:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   LDR Exclusive (16 bit)
 450:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 16 bit values.
 451:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 452:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 453:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 454:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
 455:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 456:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
 457:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 458:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 459:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
 460:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 461:Drivers/CMSIS/Include/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 462:Drivers/CMSIS/Include/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 463:Drivers/CMSIS/Include/cmsis_gcc.h ****     */
 464:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
 465:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 466:Drivers/CMSIS/Include/cmsis_gcc.h ****    return ((uint16_t) result);    /* Add explicit type cast here */
 467:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 469:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 470:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 471:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   LDR Exclusive (32 bit)
 472:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 32 bit values.
 473:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 474:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 475:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
 477:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 478:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
 479:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 480:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 481:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
 482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 483:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 485:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 486:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   STR Exclusive (8 bit)
 487:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 8 bit values.
 488:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
 489:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 490:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          0  Function succeeded
 491:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          1  Function failed
 492:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
 494:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 495:Drivers/CMSIS/Include/cmsis_gcc.h ****    uint32_t result;
 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 497:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
 498:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
 499:Drivers/CMSIS/Include/cmsis_gcc.h **** }
ARM GAS  /tmp/ccUsVHhJ.s 			page 22


 500:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 501:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 502:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 503:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   STR Exclusive (16 bit)
 504:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 16 bit values.
 505:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
 506:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 507:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          0  Function succeeded
 508:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          1  Function failed
 509:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 510:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
 511:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 512:Drivers/CMSIS/Include/cmsis_gcc.h ****    uint32_t result;
 513:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 514:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
 515:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
 516:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 517:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 518:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 519:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 520:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   STR Exclusive (32 bit)
 521:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 32 bit values.
 522:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
 523:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 524:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          0  Function succeeded
 525:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          1  Function failed
 526:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
 528:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 529:Drivers/CMSIS/Include/cmsis_gcc.h ****    uint32_t result;
 530:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 531:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 532:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
 533:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 534:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 536:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 537:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Remove the exclusive lock
 538:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Removes the exclusive lock which is created by LDREX.
 539:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 540:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __CLREX(void)
 541:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 542:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("clrex" ::: "memory");
 543:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 544:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 545:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 546:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 547:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 548:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
 549:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 550:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 551:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 552:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 553:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
 554:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 555:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Signed Saturate
 556:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Saturates a signed value.
ARM GAS  /tmp/ccUsVHhJ.s 			page 23


 557:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  ARG1  Value to be saturated
 558:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  ARG2  Bit position to saturate to (1..32)
 559:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return             Saturated value
 560:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 561:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SSAT(ARG1, ARG2) \
 562:Drivers/CMSIS/Include/cmsis_gcc.h **** __extension__ \
 563:Drivers/CMSIS/Include/cmsis_gcc.h **** ({                          \
 564:Drivers/CMSIS/Include/cmsis_gcc.h ****   int32_t __RES, __ARG1 = (ARG1); \
 565:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
 566:Drivers/CMSIS/Include/cmsis_gcc.h ****   __RES; \
 567:Drivers/CMSIS/Include/cmsis_gcc.h ****  })
 568:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 569:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 570:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 571:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Unsigned Saturate
 572:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Saturates an unsigned value.
 573:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  ARG1  Value to be saturated
 574:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  ARG2  Bit position to saturate to (0..31)
 575:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return             Saturated value
 576:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 577:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USAT(ARG1, ARG2) \
 578:Drivers/CMSIS/Include/cmsis_gcc.h **** __extension__ \
 579:Drivers/CMSIS/Include/cmsis_gcc.h **** ({                          \
 580:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t __RES, __ARG1 = (ARG1); \
 581:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
 582:Drivers/CMSIS/Include/cmsis_gcc.h ****   __RES; \
 583:Drivers/CMSIS/Include/cmsis_gcc.h ****  })
 584:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 585:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 586:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 587:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Rotate Right with Extend (32 bit)
 588:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Moves each bit of a bitstring right by one bit.
 589:Drivers/CMSIS/Include/cmsis_gcc.h ****            The carry input is shifted in at the left end of the bitstring.
 590:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to rotate
 591:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Rotated value
 592:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 593:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
 594:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 595:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 596:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 597:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 598:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 599:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 600:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 601:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 602:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 603:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   LDRT Unprivileged (8 bit)
 604:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a Unprivileged LDRT instruction for 8 bit value.
 605:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 606:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 607:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 608:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
 609:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 610:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
 611:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 612:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 613:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
ARM GAS  /tmp/ccUsVHhJ.s 			page 24


 614:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 615:Drivers/CMSIS/Include/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 616:Drivers/CMSIS/Include/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 617:Drivers/CMSIS/Include/cmsis_gcc.h ****     */
 618:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 620:Drivers/CMSIS/Include/cmsis_gcc.h ****    return ((uint8_t) result);    /* Add explicit type cast here */
 621:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 622:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 623:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 624:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 625:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   LDRT Unprivileged (16 bit)
 626:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a Unprivileged LDRT instruction for 16 bit values.
 627:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 628:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 629:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 630:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
 631:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 632:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
 633:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 634:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 635:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
 636:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 637:Drivers/CMSIS/Include/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 638:Drivers/CMSIS/Include/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 639:Drivers/CMSIS/Include/cmsis_gcc.h ****     */
 640:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
 641:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 642:Drivers/CMSIS/Include/cmsis_gcc.h ****    return ((uint16_t) result);    /* Add explicit type cast here */
 643:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 644:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 645:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 646:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 647:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   LDRT Unprivileged (32 bit)
 648:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a Unprivileged LDRT instruction for 32 bit values.
 649:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 650:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 651:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 652:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
 653:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 654:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
 655:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 656:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
 657:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
 658:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 659:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 660:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 661:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 662:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   STRT Unprivileged (8 bit)
 663:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a Unprivileged STRT instruction for 8 bit values.
 664:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
 665:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 666:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 667:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
 668:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 669:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
 670:Drivers/CMSIS/Include/cmsis_gcc.h **** }
ARM GAS  /tmp/ccUsVHhJ.s 			page 25


 671:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 672:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 673:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 674:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   STRT Unprivileged (16 bit)
 675:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a Unprivileged STRT instruction for 16 bit values.
 676:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
 677:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 678:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
 680:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 681:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
 682:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 683:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 684:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 685:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 686:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   STRT Unprivileged (32 bit)
 687:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a Unprivileged STRT instruction for 32 bit values.
 688:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
 689:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 690:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 691:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
 692:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 693:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
 694:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 695:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 696:Drivers/CMSIS/Include/cmsis_gcc.h **** #else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 697:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 698:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
 699:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 700:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 701:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Signed Saturate
 702:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Saturates a signed value.
 703:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to be saturated
 704:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    sat  Bit position to saturate to (1..32)
 705:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return             Saturated value
 706:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 707:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
 708:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 709:Drivers/CMSIS/Include/cmsis_gcc.h ****   if ((sat >= 1U) && (sat <= 32U))
 710:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
 711:Drivers/CMSIS/Include/cmsis_gcc.h ****     const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
 712:Drivers/CMSIS/Include/cmsis_gcc.h ****     const int32_t min = -1 - max ;
 713:Drivers/CMSIS/Include/cmsis_gcc.h ****     if (val > max)
 714:Drivers/CMSIS/Include/cmsis_gcc.h ****     {
 715:Drivers/CMSIS/Include/cmsis_gcc.h ****       return max;
 716:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
 717:Drivers/CMSIS/Include/cmsis_gcc.h ****     else if (val < min)
 718:Drivers/CMSIS/Include/cmsis_gcc.h ****     {
 719:Drivers/CMSIS/Include/cmsis_gcc.h ****       return min;
 720:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
 721:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 722:Drivers/CMSIS/Include/cmsis_gcc.h ****   return val;
 723:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 724:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 725:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 726:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Unsigned Saturate
 727:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Saturates an unsigned value.
ARM GAS  /tmp/ccUsVHhJ.s 			page 26


 728:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to be saturated
 729:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    sat  Bit position to saturate to (0..31)
 730:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return             Saturated value
 731:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
 733:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 734:Drivers/CMSIS/Include/cmsis_gcc.h ****   if (sat <= 31U)
 735:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
 736:Drivers/CMSIS/Include/cmsis_gcc.h ****     const uint32_t max = ((1U << sat) - 1U);
 737:Drivers/CMSIS/Include/cmsis_gcc.h ****     if (val > (int32_t)max)
 738:Drivers/CMSIS/Include/cmsis_gcc.h ****     {
 739:Drivers/CMSIS/Include/cmsis_gcc.h ****       return max;
 740:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
 741:Drivers/CMSIS/Include/cmsis_gcc.h ****     else if (val < 0)
 742:Drivers/CMSIS/Include/cmsis_gcc.h ****     {
 743:Drivers/CMSIS/Include/cmsis_gcc.h ****       return 0U;
 744:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
 745:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 746:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (uint32_t)val;
 747:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 748:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 749:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 750:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 751:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
 752:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 753:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 754:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 755:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
 756:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 757:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Load-Acquire (8 bit)
 758:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a LDAB instruction for 8 bit value.
 759:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 760:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 761:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 762:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
 763:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 764:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
 765:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 766:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 767:Drivers/CMSIS/Include/cmsis_gcc.h ****    return ((uint8_t) result);
 768:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 769:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 770:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 771:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 772:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Load-Acquire (16 bit)
 773:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a LDAH instruction for 16 bit values.
 774:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 775:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 776:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 777:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
 778:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 779:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
 780:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 781:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 782:Drivers/CMSIS/Include/cmsis_gcc.h ****    return ((uint16_t) result);
 783:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 784:Drivers/CMSIS/Include/cmsis_gcc.h **** 
ARM GAS  /tmp/ccUsVHhJ.s 			page 27


 785:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 786:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 787:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Load-Acquire (32 bit)
 788:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a LDA instruction for 32 bit values.
 789:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 790:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 791:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
 793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 794:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
 795:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 796:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 797:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
 798:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 799:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 800:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 801:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 802:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Store-Release (8 bit)
 803:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a STLB instruction for 8 bit values.
 804:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
 805:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 806:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 807:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
 808:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 809:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 810:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 811:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 812:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 814:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Store-Release (16 bit)
 815:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a STLH instruction for 16 bit values.
 816:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
 817:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 818:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 819:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
 820:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 821:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 822:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 823:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 824:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 825:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 826:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Store-Release (32 bit)
 827:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a STL instruction for 32 bit values.
 828:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
 829:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 830:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 831:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
 832:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 833:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 834:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 835:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 836:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 837:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 838:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Load-Acquire Exclusive (8 bit)
 839:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a LDAB exclusive instruction for 8 bit value.
 840:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 841:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
ARM GAS  /tmp/ccUsVHhJ.s 			page 28


 842:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 843:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
 844:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 845:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
 846:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 847:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 848:Drivers/CMSIS/Include/cmsis_gcc.h ****    return ((uint8_t) result);
 849:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 850:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 851:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 852:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 853:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Load-Acquire Exclusive (16 bit)
 854:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a LDAH exclusive instruction for 16 bit values.
 855:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 856:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 857:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 858:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
 859:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 860:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
 861:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 862:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 863:Drivers/CMSIS/Include/cmsis_gcc.h ****    return ((uint16_t) result);
 864:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 865:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 866:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 867:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 868:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Load-Acquire Exclusive (32 bit)
 869:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a LDA exclusive instruction for 32 bit values.
 870:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 871:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 872:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 873:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
 874:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 875:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
 876:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 877:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 878:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
 879:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 880:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 881:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 882:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 883:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Store-Release Exclusive (8 bit)
 884:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a STLB exclusive instruction for 8 bit values.
 885:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
 886:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 887:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          0  Function succeeded
 888:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          1  Function failed
 889:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
 891:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 892:Drivers/CMSIS/Include/cmsis_gcc.h ****    uint32_t result;
 893:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 894:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem
 895:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
 896:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 897:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 898:Drivers/CMSIS/Include/cmsis_gcc.h **** 
ARM GAS  /tmp/ccUsVHhJ.s 			page 29


 899:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 900:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Store-Release Exclusive (16 bit)
 901:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a STLH exclusive instruction for 16 bit values.
 902:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
 903:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 904:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          0  Function succeeded
 905:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          1  Function failed
 906:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
 908:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 909:Drivers/CMSIS/Include/cmsis_gcc.h ****    uint32_t result;
 910:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 911:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem
 912:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
 913:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 914:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 915:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 916:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 917:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Store-Release Exclusive (32 bit)
 918:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a STL exclusive instruction for 32 bit values.
 919:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
 920:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 921:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          0  Function succeeded
 922:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          1  Function failed
 923:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 924:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
 925:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 926:Drivers/CMSIS/Include/cmsis_gcc.h ****    uint32_t result;
 927:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 928:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memo
 929:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
 930:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 931:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 932:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 933:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
 934:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 935:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 936:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 937:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 938:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
 939:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
 940:Drivers/CMSIS/Include/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
 941:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
 942:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 943:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 944:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 945:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
 946:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
 947:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 948:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 949:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
 950:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 951:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
 952:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 953:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 954:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 955:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
ARM GAS  /tmp/ccUsVHhJ.s 			page 30


 956:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
 957:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
 958:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 959:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 960:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
 327              		.loc 2 960 27 view .LVU82
 328              	.LBB11:
 961:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 962:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
 329              		.loc 2 962 3 view .LVU83
 330              		.syntax unified
 331              	@ 962 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 332 0000 72B6     		cpsid i
 333              	@ 0 "" 2
 334              		.thumb
 335              		.syntax unified
 336              	.L10:
 337              	.LBE11:
 338              	.LBE10:
 368:Core/Src/main.c ****   while (1)
 339              		.loc 1 368 3 view .LVU84
 369:Core/Src/main.c ****   {
 370:Core/Src/main.c ****   }
 340              		.loc 1 370 3 view .LVU85
 368:Core/Src/main.c ****   while (1)
 341              		.loc 1 368 9 view .LVU86
 342 0002 FEE7     		b	.L10
 343              		.cfi_endproc
 344              	.LFE248:
 346              		.section	.text.MX_ADC1_Init,"ax",%progbits
 347              		.align	1
 348              		.syntax unified
 349              		.thumb
 350              		.thumb_func
 352              	MX_ADC1_Init:
 353              	.LFB245:
 231:Core/Src/main.c **** 
 354              		.loc 1 231 1 view -0
 355              		.cfi_startproc
 356              		@ args = 0, pretend = 0, frame = 16
 357              		@ frame_needed = 0, uses_anonymous_args = 0
 358 0000 00B5     		push	{lr}
 359              	.LCFI6:
 360              		.cfi_def_cfa_offset 4
 361              		.cfi_offset 14, -4
 362 0002 85B0     		sub	sp, sp, #20
 363              	.LCFI7:
 364              		.cfi_def_cfa_offset 24
 237:Core/Src/main.c **** 
 365              		.loc 1 237 3 view .LVU88
 237:Core/Src/main.c **** 
 366              		.loc 1 237 26 is_stmt 0 view .LVU89
 367 0004 0023     		movs	r3, #0
 368 0006 0093     		str	r3, [sp]
 369 0008 0193     		str	r3, [sp, #4]
 370 000a 0293     		str	r3, [sp, #8]
 371 000c 0393     		str	r3, [sp, #12]
ARM GAS  /tmp/ccUsVHhJ.s 			page 31


 245:Core/Src/main.c ****   hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
 372              		.loc 1 245 3 is_stmt 1 view .LVU90
 245:Core/Src/main.c ****   hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
 373              		.loc 1 245 18 is_stmt 0 view .LVU91
 374 000e 1648     		ldr	r0, .L17
 375 0010 164A     		ldr	r2, .L17+4
 376 0012 0260     		str	r2, [r0]
 246:Core/Src/main.c ****   hadc1.Init.Resolution = ADC_RESOLUTION_12B;
 377              		.loc 1 246 3 is_stmt 1 view .LVU92
 246:Core/Src/main.c ****   hadc1.Init.Resolution = ADC_RESOLUTION_12B;
 378              		.loc 1 246 29 is_stmt 0 view .LVU93
 379 0014 4FF48032 		mov	r2, #65536
 380 0018 4260     		str	r2, [r0, #4]
 247:Core/Src/main.c ****   hadc1.Init.ScanConvMode = DISABLE;
 381              		.loc 1 247 3 is_stmt 1 view .LVU94
 247:Core/Src/main.c ****   hadc1.Init.ScanConvMode = DISABLE;
 382              		.loc 1 247 25 is_stmt 0 view .LVU95
 383 001a 8360     		str	r3, [r0, #8]
 248:Core/Src/main.c ****   hadc1.Init.ContinuousConvMode = DISABLE;
 384              		.loc 1 248 3 is_stmt 1 view .LVU96
 248:Core/Src/main.c ****   hadc1.Init.ContinuousConvMode = DISABLE;
 385              		.loc 1 248 27 is_stmt 0 view .LVU97
 386 001c 0361     		str	r3, [r0, #16]
 249:Core/Src/main.c ****   hadc1.Init.DiscontinuousConvMode = DISABLE;
 387              		.loc 1 249 3 is_stmt 1 view .LVU98
 249:Core/Src/main.c ****   hadc1.Init.DiscontinuousConvMode = DISABLE;
 388              		.loc 1 249 33 is_stmt 0 view .LVU99
 389 001e 0376     		strb	r3, [r0, #24]
 250:Core/Src/main.c ****   hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
 390              		.loc 1 250 3 is_stmt 1 view .LVU100
 250:Core/Src/main.c ****   hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
 391              		.loc 1 250 36 is_stmt 0 view .LVU101
 392 0020 80F82030 		strb	r3, [r0, #32]
 251:Core/Src/main.c ****   hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_Ext_IT11;
 393              		.loc 1 251 3 is_stmt 1 view .LVU102
 251:Core/Src/main.c ****   hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_Ext_IT11;
 394              		.loc 1 251 35 is_stmt 0 view .LVU103
 395 0024 4FF08052 		mov	r2, #268435456
 396 0028 C262     		str	r2, [r0, #44]
 252:Core/Src/main.c ****   hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
 397              		.loc 1 252 3 is_stmt 1 view .LVU104
 252:Core/Src/main.c ****   hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
 398              		.loc 1 252 31 is_stmt 0 view .LVU105
 399 002a 4FF07062 		mov	r2, #251658240
 400 002e 8262     		str	r2, [r0, #40]
 253:Core/Src/main.c ****   hadc1.Init.NbrOfConversion = 1;
 401              		.loc 1 253 3 is_stmt 1 view .LVU106
 253:Core/Src/main.c ****   hadc1.Init.NbrOfConversion = 1;
 402              		.loc 1 253 24 is_stmt 0 view .LVU107
 403 0030 C360     		str	r3, [r0, #12]
 254:Core/Src/main.c ****   hadc1.Init.DMAContinuousRequests = ENABLE;
 404              		.loc 1 254 3 is_stmt 1 view .LVU108
 254:Core/Src/main.c ****   hadc1.Init.DMAContinuousRequests = ENABLE;
 405              		.loc 1 254 30 is_stmt 0 view .LVU109
 406 0032 0123     		movs	r3, #1
 407 0034 C361     		str	r3, [r0, #28]
 255:Core/Src/main.c ****   hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
ARM GAS  /tmp/ccUsVHhJ.s 			page 32


 408              		.loc 1 255 3 is_stmt 1 view .LVU110
 255:Core/Src/main.c ****   hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
 409              		.loc 1 255 36 is_stmt 0 view .LVU111
 410 0036 80F83030 		strb	r3, [r0, #48]
 256:Core/Src/main.c ****   if (HAL_ADC_Init(&hadc1) != HAL_OK)
 411              		.loc 1 256 3 is_stmt 1 view .LVU112
 256:Core/Src/main.c ****   if (HAL_ADC_Init(&hadc1) != HAL_OK)
 412              		.loc 1 256 27 is_stmt 0 view .LVU113
 413 003a 4361     		str	r3, [r0, #20]
 257:Core/Src/main.c ****   {
 414              		.loc 1 257 3 is_stmt 1 view .LVU114
 257:Core/Src/main.c ****   {
 415              		.loc 1 257 7 is_stmt 0 view .LVU115
 416 003c FFF7FEFF 		bl	HAL_ADC_Init
 417              	.LVL12:
 257:Core/Src/main.c ****   {
 418              		.loc 1 257 6 discriminator 1 view .LVU116
 419 0040 68B9     		cbnz	r0, .L15
 264:Core/Src/main.c ****   sConfig.Rank = 1;
 420              		.loc 1 264 3 is_stmt 1 view .LVU117
 264:Core/Src/main.c ****   sConfig.Rank = 1;
 421              		.loc 1 264 19 is_stmt 0 view .LVU118
 422 0042 0323     		movs	r3, #3
 423 0044 0093     		str	r3, [sp]
 265:Core/Src/main.c ****   sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
 424              		.loc 1 265 3 is_stmt 1 view .LVU119
 265:Core/Src/main.c ****   sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
 425              		.loc 1 265 16 is_stmt 0 view .LVU120
 426 0046 0123     		movs	r3, #1
 427 0048 0193     		str	r3, [sp, #4]
 266:Core/Src/main.c ****   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 428              		.loc 1 266 3 is_stmt 1 view .LVU121
 266:Core/Src/main.c ****   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 429              		.loc 1 266 24 is_stmt 0 view .LVU122
 430 004a 0023     		movs	r3, #0
 431 004c 0293     		str	r3, [sp, #8]
 267:Core/Src/main.c ****   {
 432              		.loc 1 267 3 is_stmt 1 view .LVU123
 267:Core/Src/main.c ****   {
 433              		.loc 1 267 7 is_stmt 0 view .LVU124
 434 004e 6946     		mov	r1, sp
 435 0050 0548     		ldr	r0, .L17
 436 0052 FFF7FEFF 		bl	HAL_ADC_ConfigChannel
 437              	.LVL13:
 267:Core/Src/main.c ****   {
 438              		.loc 1 267 6 discriminator 1 view .LVU125
 439 0056 20B9     		cbnz	r0, .L16
 275:Core/Src/main.c **** 
 440              		.loc 1 275 1 view .LVU126
 441 0058 05B0     		add	sp, sp, #20
 442              	.LCFI8:
 443              		.cfi_remember_state
 444              		.cfi_def_cfa_offset 4
 445              		@ sp needed
 446 005a 5DF804FB 		ldr	pc, [sp], #4
 447              	.L15:
 448              	.LCFI9:
ARM GAS  /tmp/ccUsVHhJ.s 			page 33


 449              		.cfi_restore_state
 259:Core/Src/main.c ****   }
 450              		.loc 1 259 5 is_stmt 1 view .LVU127
 451 005e FFF7FEFF 		bl	Error_Handler
 452              	.LVL14:
 453              	.L16:
 269:Core/Src/main.c ****   }
 454              		.loc 1 269 5 view .LVU128
 455 0062 FFF7FEFF 		bl	Error_Handler
 456              	.LVL15:
 457              	.L18:
 458 0066 00BF     		.align	2
 459              	.L17:
 460 0068 00000000 		.word	hadc1
 461 006c 00200140 		.word	1073815552
 462              		.cfi_endproc
 463              	.LFE245:
 465              		.section	.text.SystemClock_Config,"ax",%progbits
 466              		.align	1
 467              		.global	SystemClock_Config
 468              		.syntax unified
 469              		.thumb
 470              		.thumb_func
 472              	SystemClock_Config:
 473              	.LFB244:
 185:Core/Src/main.c ****   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 474              		.loc 1 185 1 view -0
 475              		.cfi_startproc
 476              		@ args = 0, pretend = 0, frame = 80
 477              		@ frame_needed = 0, uses_anonymous_args = 0
 478 0000 00B5     		push	{lr}
 479              	.LCFI10:
 480              		.cfi_def_cfa_offset 4
 481              		.cfi_offset 14, -4
 482 0002 95B0     		sub	sp, sp, #84
 483              	.LCFI11:
 484              		.cfi_def_cfa_offset 88
 186:Core/Src/main.c ****   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 485              		.loc 1 186 3 view .LVU130
 186:Core/Src/main.c ****   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 486              		.loc 1 186 22 is_stmt 0 view .LVU131
 487 0004 3022     		movs	r2, #48
 488 0006 0021     		movs	r1, #0
 489 0008 08A8     		add	r0, sp, #32
 490 000a FFF7FEFF 		bl	memset
 491              	.LVL16:
 187:Core/Src/main.c **** 
 492              		.loc 1 187 3 is_stmt 1 view .LVU132
 187:Core/Src/main.c **** 
 493              		.loc 1 187 22 is_stmt 0 view .LVU133
 494 000e 0023     		movs	r3, #0
 495 0010 0393     		str	r3, [sp, #12]
 496 0012 0493     		str	r3, [sp, #16]
 497 0014 0593     		str	r3, [sp, #20]
 498 0016 0693     		str	r3, [sp, #24]
 499 0018 0793     		str	r3, [sp, #28]
 191:Core/Src/main.c ****   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
ARM GAS  /tmp/ccUsVHhJ.s 			page 34


 500              		.loc 1 191 3 is_stmt 1 view .LVU134
 501              	.LBB12:
 191:Core/Src/main.c ****   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 502              		.loc 1 191 3 view .LVU135
 503 001a 0193     		str	r3, [sp, #4]
 191:Core/Src/main.c ****   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 504              		.loc 1 191 3 view .LVU136
 505 001c 214A     		ldr	r2, .L25
 506 001e 116C     		ldr	r1, [r2, #64]
 507 0020 41F08051 		orr	r1, r1, #268435456
 508 0024 1164     		str	r1, [r2, #64]
 191:Core/Src/main.c ****   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 509              		.loc 1 191 3 view .LVU137
 510 0026 126C     		ldr	r2, [r2, #64]
 511 0028 02F08052 		and	r2, r2, #268435456
 512 002c 0192     		str	r2, [sp, #4]
 191:Core/Src/main.c ****   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 513              		.loc 1 191 3 view .LVU138
 514 002e 019A     		ldr	r2, [sp, #4]
 515              	.LBE12:
 191:Core/Src/main.c ****   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 516              		.loc 1 191 3 view .LVU139
 192:Core/Src/main.c **** 
 517              		.loc 1 192 3 view .LVU140
 518              	.LBB13:
 192:Core/Src/main.c **** 
 519              		.loc 1 192 3 view .LVU141
 520 0030 0293     		str	r3, [sp, #8]
 192:Core/Src/main.c **** 
 521              		.loc 1 192 3 view .LVU142
 522 0032 1D4B     		ldr	r3, .L25+4
 523 0034 1A68     		ldr	r2, [r3]
 524 0036 42F44042 		orr	r2, r2, #49152
 525 003a 1A60     		str	r2, [r3]
 192:Core/Src/main.c **** 
 526              		.loc 1 192 3 view .LVU143
 527 003c 1B68     		ldr	r3, [r3]
 528 003e 03F44043 		and	r3, r3, #49152
 529 0042 0293     		str	r3, [sp, #8]
 192:Core/Src/main.c **** 
 530              		.loc 1 192 3 view .LVU144
 531 0044 029B     		ldr	r3, [sp, #8]
 532              	.LBE13:
 192:Core/Src/main.c **** 
 533              		.loc 1 192 3 view .LVU145
 197:Core/Src/main.c ****   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
 534              		.loc 1 197 3 view .LVU146
 197:Core/Src/main.c ****   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
 535              		.loc 1 197 36 is_stmt 0 view .LVU147
 536 0046 0123     		movs	r3, #1
 537 0048 0893     		str	r3, [sp, #32]
 198:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 538              		.loc 1 198 3 is_stmt 1 view .LVU148
 198:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 539              		.loc 1 198 30 is_stmt 0 view .LVU149
 540 004a 4FF48033 		mov	r3, #65536
 541 004e 0993     		str	r3, [sp, #36]
ARM GAS  /tmp/ccUsVHhJ.s 			page 35


 199:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
 542              		.loc 1 199 3 is_stmt 1 view .LVU150
 199:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
 543              		.loc 1 199 34 is_stmt 0 view .LVU151
 544 0050 0223     		movs	r3, #2
 545 0052 0E93     		str	r3, [sp, #56]
 200:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLM = 8;
 546              		.loc 1 200 3 is_stmt 1 view .LVU152
 200:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLM = 8;
 547              		.loc 1 200 35 is_stmt 0 view .LVU153
 548 0054 4FF48002 		mov	r2, #4194304
 549 0058 0F92     		str	r2, [sp, #60]
 201:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLN = 336;
 550              		.loc 1 201 3 is_stmt 1 view .LVU154
 201:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLN = 336;
 551              		.loc 1 201 30 is_stmt 0 view .LVU155
 552 005a 0822     		movs	r2, #8
 553 005c 1092     		str	r2, [sp, #64]
 202:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
 554              		.loc 1 202 3 is_stmt 1 view .LVU156
 202:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
 555              		.loc 1 202 30 is_stmt 0 view .LVU157
 556 005e 4FF4A872 		mov	r2, #336
 557 0062 1192     		str	r2, [sp, #68]
 203:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLQ = 7;
 558              		.loc 1 203 3 is_stmt 1 view .LVU158
 203:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLQ = 7;
 559              		.loc 1 203 30 is_stmt 0 view .LVU159
 560 0064 1293     		str	r3, [sp, #72]
 204:Core/Src/main.c ****   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 561              		.loc 1 204 3 is_stmt 1 view .LVU160
 204:Core/Src/main.c ****   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 562              		.loc 1 204 30 is_stmt 0 view .LVU161
 563 0066 0723     		movs	r3, #7
 564 0068 1393     		str	r3, [sp, #76]
 205:Core/Src/main.c ****   {
 565              		.loc 1 205 3 is_stmt 1 view .LVU162
 205:Core/Src/main.c ****   {
 566              		.loc 1 205 7 is_stmt 0 view .LVU163
 567 006a 08A8     		add	r0, sp, #32
 568 006c FFF7FEFF 		bl	HAL_RCC_OscConfig
 569              	.LVL17:
 205:Core/Src/main.c ****   {
 570              		.loc 1 205 6 discriminator 1 view .LVU164
 571 0070 98B9     		cbnz	r0, .L23
 212:Core/Src/main.c ****                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
 572              		.loc 1 212 3 is_stmt 1 view .LVU165
 212:Core/Src/main.c ****                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
 573              		.loc 1 212 31 is_stmt 0 view .LVU166
 574 0072 0F23     		movs	r3, #15
 575 0074 0393     		str	r3, [sp, #12]
 214:Core/Src/main.c ****   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 576              		.loc 1 214 3 is_stmt 1 view .LVU167
 214:Core/Src/main.c ****   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 577              		.loc 1 214 34 is_stmt 0 view .LVU168
 578 0076 0223     		movs	r3, #2
 579 0078 0493     		str	r3, [sp, #16]
ARM GAS  /tmp/ccUsVHhJ.s 			page 36


 215:Core/Src/main.c ****   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
 580              		.loc 1 215 3 is_stmt 1 view .LVU169
 215:Core/Src/main.c ****   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
 581              		.loc 1 215 35 is_stmt 0 view .LVU170
 582 007a 0023     		movs	r3, #0
 583 007c 0593     		str	r3, [sp, #20]
 216:Core/Src/main.c ****   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
 584              		.loc 1 216 3 is_stmt 1 view .LVU171
 216:Core/Src/main.c ****   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
 585              		.loc 1 216 36 is_stmt 0 view .LVU172
 586 007e 4FF4A053 		mov	r3, #5120
 587 0082 0693     		str	r3, [sp, #24]
 217:Core/Src/main.c **** 
 588              		.loc 1 217 3 is_stmt 1 view .LVU173
 217:Core/Src/main.c **** 
 589              		.loc 1 217 36 is_stmt 0 view .LVU174
 590 0084 4FF48053 		mov	r3, #4096
 591 0088 0793     		str	r3, [sp, #28]
 219:Core/Src/main.c ****   {
 592              		.loc 1 219 3 is_stmt 1 view .LVU175
 219:Core/Src/main.c ****   {
 593              		.loc 1 219 7 is_stmt 0 view .LVU176
 594 008a 0521     		movs	r1, #5
 595 008c 03A8     		add	r0, sp, #12
 596 008e FFF7FEFF 		bl	HAL_RCC_ClockConfig
 597              	.LVL18:
 219:Core/Src/main.c ****   {
 598              		.loc 1 219 6 discriminator 1 view .LVU177
 599 0092 20B9     		cbnz	r0, .L24
 223:Core/Src/main.c **** 
 600              		.loc 1 223 1 view .LVU178
 601 0094 15B0     		add	sp, sp, #84
 602              	.LCFI12:
 603              		.cfi_remember_state
 604              		.cfi_def_cfa_offset 4
 605              		@ sp needed
 606 0096 5DF804FB 		ldr	pc, [sp], #4
 607              	.L23:
 608              	.LCFI13:
 609              		.cfi_restore_state
 207:Core/Src/main.c ****   }
 610              		.loc 1 207 5 is_stmt 1 view .LVU179
 611 009a FFF7FEFF 		bl	Error_Handler
 612              	.LVL19:
 613              	.L24:
 221:Core/Src/main.c ****   }
 614              		.loc 1 221 5 view .LVU180
 615 009e FFF7FEFF 		bl	Error_Handler
 616              	.LVL20:
 617              	.L26:
 618 00a2 00BF     		.align	2
 619              	.L25:
 620 00a4 00380240 		.word	1073887232
 621 00a8 00700040 		.word	1073770496
 622              		.cfi_endproc
 623              	.LFE244:
 625              		.global	__aeabi_ldivmod
ARM GAS  /tmp/ccUsVHhJ.s 			page 37


 626              		.section	.rodata.main.str1.4,"aMS",%progbits,1
 627              		.align	2
 628              	.LC0:
 629 0000 53776565 		.ascii	"Sweep_start\012\015\000"
 629      705F7374 
 629      6172740A 
 629      0D00
 630              		.section	.text.main,"ax",%progbits
 631              		.align	1
 632              		.global	main
 633              		.syntax unified
 634              		.thumb
 635              		.thumb_func
 637              	main:
 638              	.LFB243:
  81:Core/Src/main.c **** 
 639              		.loc 1 81 1 view -0
 640              		.cfi_startproc
 641              		@ args = 0, pretend = 0, frame = 0
 642              		@ frame_needed = 0, uses_anonymous_args = 0
 643 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
 644              	.LCFI14:
 645              		.cfi_def_cfa_offset 24
 646              		.cfi_offset 3, -24
 647              		.cfi_offset 4, -20
 648              		.cfi_offset 5, -16
 649              		.cfi_offset 6, -12
 650              		.cfi_offset 7, -8
 651              		.cfi_offset 14, -4
  90:Core/Src/main.c **** 
 652              		.loc 1 90 3 view .LVU182
 653 0002 FFF7FEFF 		bl	HAL_Init
 654              	.LVL21:
  97:Core/Src/main.c **** 
 655              		.loc 1 97 3 view .LVU183
 656 0006 FFF7FEFF 		bl	SystemClock_Config
 657              	.LVL22:
 104:Core/Src/main.c ****   MX_DMA_Init();
 658              		.loc 1 104 3 view .LVU184
 659 000a FFF7FEFF 		bl	MX_GPIO_Init
 660              	.LVL23:
 105:Core/Src/main.c ****   MX_ADC1_Init();
 661              		.loc 1 105 3 view .LVU185
 662 000e FFF7FEFF 		bl	MX_DMA_Init
 663              	.LVL24:
 106:Core/Src/main.c ****   MX_USB_DEVICE_Init();
 664              		.loc 1 106 3 view .LVU186
 665 0012 FFF7FEFF 		bl	MX_ADC1_Init
 666              	.LVL25:
 107:Core/Src/main.c ****   /* USER CODE BEGIN 2 */
 667              		.loc 1 107 3 view .LVU187
 668 0016 FFF7FEFF 		bl	MX_USB_DEVICE_Init
 669              	.LVL26:
 109:Core/Src/main.c ****   HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADC1_buff_circular, ADC_BUFF_SIZE);
 670              		.loc 1 109 3 view .LVU188
 671 001a 0122     		movs	r2, #1
 672 001c 8021     		movs	r1, #128
ARM GAS  /tmp/ccUsVHhJ.s 			page 38


 673 001e A048     		ldr	r0, .L33+8
 674 0020 FFF7FEFF 		bl	HAL_GPIO_WritePin
 675              	.LVL27:
 110:Core/Src/main.c ****   
 676              		.loc 1 110 3 view .LVU189
 677 0024 6422     		movs	r2, #100
 678 0026 9F49     		ldr	r1, .L33+12
 679 0028 9F48     		ldr	r0, .L33+16
 680 002a FFF7FEFF 		bl	HAL_ADC_Start_DMA
 681              	.LVL28:
 112:Core/Src/main.c ****   ADC_proc_shadow.N = 0;
 682              		.loc 1 112 3 view .LVU190
 112:Core/Src/main.c ****   ADC_proc_shadow.N = 0;
 683              		.loc 1 112 26 is_stmt 0 view .LVU191
 684 002e 9F4A     		ldr	r2, .L33+20
 685 0030 0023     		movs	r3, #0
 686 0032 1370     		strb	r3, [r2]
 113:Core/Src/main.c ****   ADC_proc_shadow.sum = 0;
 687              		.loc 1 113 3 is_stmt 1 view .LVU192
 113:Core/Src/main.c ****   ADC_proc_shadow.sum = 0;
 688              		.loc 1 113 21 is_stmt 0 view .LVU193
 689 0034 D360     		str	r3, [r2, #12]
 114:Core/Src/main.c ****   ADC_proc_shadow.avg = 0;
 690              		.loc 1 114 3 is_stmt 1 view .LVU194
 114:Core/Src/main.c ****   ADC_proc_shadow.avg = 0;
 691              		.loc 1 114 23 is_stmt 0 view .LVU195
 692 0036 5360     		str	r3, [r2, #4]
 115:Core/Src/main.c **** 
 693              		.loc 1 115 3 is_stmt 1 view .LVU196
 115:Core/Src/main.c **** 
 694              		.loc 1 115 23 is_stmt 0 view .LVU197
 695 0038 9360     		str	r3, [r2, #8]
 117:Core/Src/main.c ****   ADC_proc.N = 0;
 696              		.loc 1 117 3 is_stmt 1 view .LVU198
 117:Core/Src/main.c ****   ADC_proc.N = 0;
 697              		.loc 1 117 19 is_stmt 0 view .LVU199
 698 003a 9D4A     		ldr	r2, .L33+24
 699 003c 1370     		strb	r3, [r2]
 118:Core/Src/main.c ****   ADC_proc.sum = 0;
 700              		.loc 1 118 3 is_stmt 1 view .LVU200
 118:Core/Src/main.c ****   ADC_proc.sum = 0;
 701              		.loc 1 118 14 is_stmt 0 view .LVU201
 702 003e D360     		str	r3, [r2, #12]
 119:Core/Src/main.c ****   ADC_proc.avg = 0;
 703              		.loc 1 119 3 is_stmt 1 view .LVU202
 119:Core/Src/main.c ****   ADC_proc.avg = 0;
 704              		.loc 1 119 16 is_stmt 0 view .LVU203
 705 0040 5360     		str	r3, [r2, #4]
 120:Core/Src/main.c **** 
 706              		.loc 1 120 3 is_stmt 1 view .LVU204
 120:Core/Src/main.c **** 
 707              		.loc 1 120 16 is_stmt 0 view .LVU205
 708 0042 9360     		str	r3, [r2, #8]
 122:Core/Src/main.c ****   uint32_t curr_points_N =0;
 709              		.loc 1 122 3 is_stmt 1 view .LVU206
 710              	.LVL29:
 123:Core/Src/main.c **** 
ARM GAS  /tmp/ccUsVHhJ.s 			page 39


 711              		.loc 1 123 3 view .LVU207
 712              	.L28:
 129:Core/Src/main.c ****   {
 713              		.loc 1 129 3 view .LVU208
 134:Core/Src/main.c ****       ADC_proc_shadow.avg = ADC_proc_shadow.sum / ADC_proc_shadow.N;
 714              		.loc 1 134 5 view .LVU209
 134:Core/Src/main.c ****       ADC_proc_shadow.avg = ADC_proc_shadow.sum / ADC_proc_shadow.N;
 715              		.loc 1 134 24 is_stmt 0 view .LVU210
 716 0044 994B     		ldr	r3, .L33+20
 717 0046 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
 718 0048 DBB2     		uxtb	r3, r3
 134:Core/Src/main.c ****       ADC_proc_shadow.avg = ADC_proc_shadow.sum / ADC_proc_shadow.N;
 719              		.loc 1 134 8 view .LVU211
 720 004a 022B     		cmp	r3, #2
 721 004c FAD1     		bne	.L28
 135:Core/Src/main.c ****       ADC_proc_shadow.status = 1; // reset for next accumulation
 722              		.loc 1 135 7 is_stmt 1 view .LVU212
 135:Core/Src/main.c ****       ADC_proc_shadow.status = 1; // reset for next accumulation
 723              		.loc 1 135 44 is_stmt 0 view .LVU213
 724 004e 974B     		ldr	r3, .L33+20
 725 0050 5A68     		ldr	r2, [r3, #4]
 135:Core/Src/main.c ****       ADC_proc_shadow.status = 1; // reset for next accumulation
 726              		.loc 1 135 66 view .LVU214
 727 0052 D968     		ldr	r1, [r3, #12]
 135:Core/Src/main.c ****       ADC_proc_shadow.status = 1; // reset for next accumulation
 728              		.loc 1 135 49 view .LVU215
 729 0054 B2FBF1F2 		udiv	r2, r2, r1
 135:Core/Src/main.c ****       ADC_proc_shadow.status = 1; // reset for next accumulation
 730              		.loc 1 135 27 view .LVU216
 731 0058 9A60     		str	r2, [r3, #8]
 136:Core/Src/main.c ****       ADC_proc_shadow.sum = 0;
 732              		.loc 1 136 7 is_stmt 1 view .LVU217
 136:Core/Src/main.c ****       ADC_proc_shadow.sum = 0;
 733              		.loc 1 136 30 is_stmt 0 view .LVU218
 734 005a 0122     		movs	r2, #1
 735 005c 1A70     		strb	r2, [r3]
 137:Core/Src/main.c ****       ADC_proc_shadow.N = 0;
 736              		.loc 1 137 7 is_stmt 1 view .LVU219
 137:Core/Src/main.c ****       ADC_proc_shadow.N = 0;
 737              		.loc 1 137 27 is_stmt 0 view .LVU220
 738 005e 0021     		movs	r1, #0
 739 0060 5960     		str	r1, [r3, #4]
 138:Core/Src/main.c ****       
 740              		.loc 1 138 7 is_stmt 1 view .LVU221
 138:Core/Src/main.c ****       
 741              		.loc 1 138 25 is_stmt 0 view .LVU222
 742 0062 D960     		str	r1, [r3, #12]
 141:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 1] = (ADC_proc_shadow.avg / 1000000000) % 10 +  '0';
 743              		.loc 1 141 7 is_stmt 1 view .LVU223
 141:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 1] = (ADC_proc_shadow.avg / 1000000000) % 10 +  '0';
 744              		.loc 1 141 54 is_stmt 0 view .LVU224
 745 0064 9868     		ldr	r0, [r3, #8]
 141:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 1] = (ADC_proc_shadow.avg / 1000000000) % 10 +  '0';
 746              		.loc 1 141 59 view .LVU225
 747 0066 8CA3     		adr	r3, .L33
 748 0068 D3E90023 		ldrd	r2, [r3]
 749 006c FFF7FEFF 		bl	__aeabi_ldivmod
ARM GAS  /tmp/ccUsVHhJ.s 			page 40


 750              	.LVL30:
 751 0070 8446     		mov	ip, r0
 141:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 1] = (ADC_proc_shadow.avg / 1000000000) % 10 +  '0';
 752              		.loc 1 141 74 view .LVU226
 753 0072 CC17     		asrs	r4, r1, #31
 754 0074 04F00302 		and	r2, r4, #3
 755 0078 20F07043 		bic	r3, r0, #-268435456
 756 007c 000F     		lsrs	r0, r0, #28
 757 007e 40EA0110 		orr	r0, r0, r1, lsl #4
 758 0082 20F07040 		bic	r0, r0, #-268435456
 759 0086 0344     		add	r3, r3, r0
 760 0088 03EB1163 		add	r3, r3, r1, lsr #24
 761 008c 1344     		add	r3, r3, r2
 762 008e 894A     		ldr	r2, .L33+28
 763 0090 A2FB0305 		umull	r0, r5, r2, r3
 764 0094 25F00300 		bic	r0, r5, #3
 765 0098 00EB9500 		add	r0, r0, r5, lsr #2
 766 009c 1B1A     		subs	r3, r3, r0
 767 009e 24F00304 		bic	r4, r4, #3
 768 00a2 2344     		add	r3, r3, r4
 769 00a4 BCEB0300 		subs	r0, ip, r3
 770 00a8 61EBE371 		sbc	r1, r1, r3, asr #31
 771 00ac 4FF0CC33 		mov	r3, #-858993460
 772 00b0 00FB03F3 		mul	r3, r0, r3
 773 00b4 02FB0133 		mla	r3, r2, r1, r3
 774 00b8 A0FB0202 		umull	r0, r2, r0, r2
 775 00bc 1A44     		add	r2, r2, r3
 776 00be D30F     		lsrs	r3, r2, #31
 777 00c0 1B18     		adds	r3, r3, r0
 778 00c2 42F10002 		adc	r2, r2, #0
 779 00c6 5B08     		lsrs	r3, r3, #1
 780 00c8 43EAC273 		orr	r3, r3, r2, lsl #31
 781 00cc 03EB8303 		add	r3, r3, r3, lsl #2
 782 00d0 ACEB430C 		sub	ip, ip, r3, lsl #1
 141:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 1] = (ADC_proc_shadow.avg / 1000000000) % 10 +  '0';
 783              		.loc 1 141 79 view .LVU227
 784 00d4 0CF1300C 		add	ip, ip, #48
 141:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 1] = (ADC_proc_shadow.avg / 1000000000) % 10 +  '0';
 785              		.loc 1 141 36 view .LVU228
 786 00d8 7748     		ldr	r0, .L33+32
 787 00da 80F814C0 		strb	ip, [r0, #20]
 142:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 2] = (ADC_proc_shadow.avg / 10000000) % 10 + '0';
 788              		.loc 1 142 7 is_stmt 1 view .LVU229
 142:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 2] = (ADC_proc_shadow.avg / 10000000) % 10 + '0';
 789              		.loc 1 142 54 is_stmt 0 view .LVU230
 790 00de 734C     		ldr	r4, .L33+20
 791 00e0 A268     		ldr	r2, [r4, #8]
 142:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 2] = (ADC_proc_shadow.avg / 10000000) % 10 + '0';
 792              		.loc 1 142 59 view .LVU231
 793 00e2 520A     		lsrs	r2, r2, #9
 794 00e4 754B     		ldr	r3, .L33+36
 795 00e6 A3FB0232 		umull	r3, r2, r3, r2
 142:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 2] = (ADC_proc_shadow.avg / 10000000) % 10 + '0';
 796              		.loc 1 142 73 view .LVU232
 797 00ea 724B     		ldr	r3, .L33+28
 798 00ec D209     		lsrs	r2, r2, #7
 142:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 2] = (ADC_proc_shadow.avg / 10000000) % 10 + '0';
ARM GAS  /tmp/ccUsVHhJ.s 			page 41


 799              		.loc 1 142 78 view .LVU233
 800 00ee 3032     		adds	r2, r2, #48
 142:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 2] = (ADC_proc_shadow.avg / 10000000) % 10 + '0';
 801              		.loc 1 142 36 view .LVU234
 802 00f0 4275     		strb	r2, [r0, #21]
 143:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 3] = (ADC_proc_shadow.avg / 1000000) % 10 + '0';
 803              		.loc 1 143 7 is_stmt 1 view .LVU235
 143:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 3] = (ADC_proc_shadow.avg / 1000000) % 10 + '0';
 804              		.loc 1 143 54 is_stmt 0 view .LVU236
 805 00f2 A168     		ldr	r1, [r4, #8]
 143:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 3] = (ADC_proc_shadow.avg / 1000000) % 10 + '0';
 806              		.loc 1 143 59 view .LVU237
 807 00f4 724A     		ldr	r2, .L33+40
 808 00f6 A2FB0121 		umull	r2, r1, r2, r1
 809 00fa 890D     		lsrs	r1, r1, #22
 143:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 3] = (ADC_proc_shadow.avg / 1000000) % 10 + '0';
 810              		.loc 1 143 71 view .LVU238
 811 00fc A3FB0152 		umull	r5, r2, r3, r1
 812 0100 D208     		lsrs	r2, r2, #3
 813 0102 02EB8202 		add	r2, r2, r2, lsl #2
 814 0106 A1EB4202 		sub	r2, r1, r2, lsl #1
 143:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 3] = (ADC_proc_shadow.avg / 1000000) % 10 + '0';
 815              		.loc 1 143 76 view .LVU239
 816 010a 3032     		adds	r2, r2, #48
 143:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 3] = (ADC_proc_shadow.avg / 1000000) % 10 + '0';
 817              		.loc 1 143 36 view .LVU240
 818 010c 8275     		strb	r2, [r0, #22]
 144:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 4] = (ADC_proc_shadow.avg / 100000) % 10 + '0';
 819              		.loc 1 144 7 is_stmt 1 view .LVU241
 144:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 4] = (ADC_proc_shadow.avg / 100000) % 10 + '0';
 820              		.loc 1 144 54 is_stmt 0 view .LVU242
 821 010e A168     		ldr	r1, [r4, #8]
 144:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 4] = (ADC_proc_shadow.avg / 100000) % 10 + '0';
 822              		.loc 1 144 59 view .LVU243
 823 0110 6C4A     		ldr	r2, .L33+44
 824 0112 A2FB0121 		umull	r2, r1, r2, r1
 825 0116 890C     		lsrs	r1, r1, #18
 144:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 4] = (ADC_proc_shadow.avg / 100000) % 10 + '0';
 826              		.loc 1 144 70 view .LVU244
 827 0118 A3FB0152 		umull	r5, r2, r3, r1
 828 011c D208     		lsrs	r2, r2, #3
 829 011e 02EB8202 		add	r2, r2, r2, lsl #2
 830 0122 A1EB4202 		sub	r2, r1, r2, lsl #1
 144:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 4] = (ADC_proc_shadow.avg / 100000) % 10 + '0';
 831              		.loc 1 144 75 view .LVU245
 832 0126 3032     		adds	r2, r2, #48
 144:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 4] = (ADC_proc_shadow.avg / 100000) % 10 + '0';
 833              		.loc 1 144 36 view .LVU246
 834 0128 C275     		strb	r2, [r0, #23]
 145:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 5] = (ADC_proc_shadow.avg / 10000) % 10 + '0';
 835              		.loc 1 145 7 is_stmt 1 view .LVU247
 145:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 5] = (ADC_proc_shadow.avg / 10000) % 10 + '0';
 836              		.loc 1 145 54 is_stmt 0 view .LVU248
 837 012a A168     		ldr	r1, [r4, #8]
 145:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 5] = (ADC_proc_shadow.avg / 10000) % 10 + '0';
 838              		.loc 1 145 59 view .LVU249
 839 012c 4909     		lsrs	r1, r1, #5
ARM GAS  /tmp/ccUsVHhJ.s 			page 42


 840 012e 664F     		ldr	r7, .L33+48
 841 0130 A7FB0121 		umull	r2, r1, r7, r1
 842 0134 C909     		lsrs	r1, r1, #7
 145:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 5] = (ADC_proc_shadow.avg / 10000) % 10 + '0';
 843              		.loc 1 145 69 view .LVU250
 844 0136 A3FB0152 		umull	r5, r2, r3, r1
 845 013a D208     		lsrs	r2, r2, #3
 846 013c 02EB8202 		add	r2, r2, r2, lsl #2
 847 0140 A1EB4202 		sub	r2, r1, r2, lsl #1
 145:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 5] = (ADC_proc_shadow.avg / 10000) % 10 + '0';
 848              		.loc 1 145 74 view .LVU251
 849 0144 3032     		adds	r2, r2, #48
 145:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 5] = (ADC_proc_shadow.avg / 10000) % 10 + '0';
 850              		.loc 1 145 36 view .LVU252
 851 0146 0276     		strb	r2, [r0, #24]
 146:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 6] = (ADC_proc_shadow.avg / 1000) % 10 + '0';
 852              		.loc 1 146 7 is_stmt 1 view .LVU253
 146:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 6] = (ADC_proc_shadow.avg / 1000) % 10 + '0';
 853              		.loc 1 146 54 is_stmt 0 view .LVU254
 854 0148 A168     		ldr	r1, [r4, #8]
 146:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 6] = (ADC_proc_shadow.avg / 1000) % 10 + '0';
 855              		.loc 1 146 59 view .LVU255
 856 014a 604E     		ldr	r6, .L33+52
 857 014c A6FB0121 		umull	r2, r1, r6, r1
 858 0150 490B     		lsrs	r1, r1, #13
 146:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 6] = (ADC_proc_shadow.avg / 1000) % 10 + '0';
 859              		.loc 1 146 68 view .LVU256
 860 0152 A3FB0152 		umull	r5, r2, r3, r1
 861 0156 D208     		lsrs	r2, r2, #3
 862 0158 02EB8202 		add	r2, r2, r2, lsl #2
 863 015c A1EB4202 		sub	r2, r1, r2, lsl #1
 146:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 6] = (ADC_proc_shadow.avg / 1000) % 10 + '0';
 864              		.loc 1 146 73 view .LVU257
 865 0160 3032     		adds	r2, r2, #48
 146:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 6] = (ADC_proc_shadow.avg / 1000) % 10 + '0';
 866              		.loc 1 146 36 view .LVU258
 867 0162 4276     		strb	r2, [r0, #25]
 147:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 7] = (ADC_proc_shadow.avg / 100) % 10 + '0';
 868              		.loc 1 147 7 is_stmt 1 view .LVU259
 147:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 7] = (ADC_proc_shadow.avg / 100) % 10 + '0';
 869              		.loc 1 147 54 is_stmt 0 view .LVU260
 870 0164 A168     		ldr	r1, [r4, #8]
 147:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 7] = (ADC_proc_shadow.avg / 100) % 10 + '0';
 871              		.loc 1 147 59 view .LVU261
 872 0166 5A4D     		ldr	r5, .L33+56
 873 0168 A5FB0121 		umull	r2, r1, r5, r1
 874 016c 8909     		lsrs	r1, r1, #6
 147:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 7] = (ADC_proc_shadow.avg / 100) % 10 + '0';
 875              		.loc 1 147 67 view .LVU262
 876 016e A3FB01C2 		umull	ip, r2, r3, r1
 877 0172 D208     		lsrs	r2, r2, #3
 878 0174 02EB8202 		add	r2, r2, r2, lsl #2
 879 0178 A1EB4202 		sub	r2, r1, r2, lsl #1
 147:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 7] = (ADC_proc_shadow.avg / 100) % 10 + '0';
 880              		.loc 1 147 72 view .LVU263
 881 017c 3032     		adds	r2, r2, #48
 147:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 7] = (ADC_proc_shadow.avg / 100) % 10 + '0';
ARM GAS  /tmp/ccUsVHhJ.s 			page 43


 882              		.loc 1 147 36 view .LVU264
 883 017e 8276     		strb	r2, [r0, #26]
 148:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 8] = (ADC_proc_shadow.avg / 10) % 10 + '0';
 884              		.loc 1 148 7 is_stmt 1 view .LVU265
 148:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 8] = (ADC_proc_shadow.avg / 10) % 10 + '0';
 885              		.loc 1 148 54 is_stmt 0 view .LVU266
 886 0180 A268     		ldr	r2, [r4, #8]
 148:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 8] = (ADC_proc_shadow.avg / 10) % 10 + '0';
 887              		.loc 1 148 59 view .LVU267
 888 0182 5449     		ldr	r1, .L33+60
 889 0184 A1FB022C 		umull	r2, ip, r1, r2
 890 0188 4FEA5C1C 		lsr	ip, ip, #5
 148:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 8] = (ADC_proc_shadow.avg / 10) % 10 + '0';
 891              		.loc 1 148 66 view .LVU268
 892 018c A3FB0CE2 		umull	lr, r2, r3, ip
 893 0190 D208     		lsrs	r2, r2, #3
 894 0192 02EB8202 		add	r2, r2, r2, lsl #2
 895 0196 ACEB4202 		sub	r2, ip, r2, lsl #1
 148:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 8] = (ADC_proc_shadow.avg / 10) % 10 + '0';
 896              		.loc 1 148 71 view .LVU269
 897 019a 3032     		adds	r2, r2, #48
 148:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 8] = (ADC_proc_shadow.avg / 10) % 10 + '0';
 898              		.loc 1 148 36 view .LVU270
 899 019c C276     		strb	r2, [r0, #27]
 149:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 9] = (ADC_proc_shadow.avg / 1) % 10 + '0';
 900              		.loc 1 149 7 is_stmt 1 view .LVU271
 149:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 9] = (ADC_proc_shadow.avg / 1) % 10 + '0';
 901              		.loc 1 149 54 is_stmt 0 view .LVU272
 902 019e A268     		ldr	r2, [r4, #8]
 149:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 9] = (ADC_proc_shadow.avg / 1) % 10 + '0';
 903              		.loc 1 149 59 view .LVU273
 904 01a0 A3FB022C 		umull	r2, ip, r3, r2
 905 01a4 4FEADC0C 		lsr	ip, ip, #3
 149:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 9] = (ADC_proc_shadow.avg / 1) % 10 + '0';
 906              		.loc 1 149 65 view .LVU274
 907 01a8 A3FB0CE2 		umull	lr, r2, r3, ip
 908 01ac D208     		lsrs	r2, r2, #3
 909 01ae 02EB8202 		add	r2, r2, r2, lsl #2
 910 01b2 ACEB4202 		sub	r2, ip, r2, lsl #1
 149:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 9] = (ADC_proc_shadow.avg / 1) % 10 + '0';
 911              		.loc 1 149 70 view .LVU275
 912 01b6 3032     		adds	r2, r2, #48
 149:Core/Src/main.c ****       ADC_msg[ADC_msg_val_pos + 9] = (ADC_proc_shadow.avg / 1) % 10 + '0';
 913              		.loc 1 149 36 view .LVU276
 914 01b8 0277     		strb	r2, [r0, #28]
 150:Core/Src/main.c **** 
 915              		.loc 1 150 7 is_stmt 1 view .LVU277
 150:Core/Src/main.c **** 
 916              		.loc 1 150 54 is_stmt 0 view .LVU278
 917 01ba A468     		ldr	r4, [r4, #8]
 150:Core/Src/main.c **** 
 918              		.loc 1 150 64 view .LVU279
 919 01bc A3FB04C2 		umull	ip, r2, r3, r4
 920 01c0 D208     		lsrs	r2, r2, #3
 921 01c2 02EB8202 		add	r2, r2, r2, lsl #2
 922 01c6 A4EB4202 		sub	r2, r4, r2, lsl #1
 150:Core/Src/main.c **** 
ARM GAS  /tmp/ccUsVHhJ.s 			page 44


 923              		.loc 1 150 69 view .LVU280
 924 01ca 3032     		adds	r2, r2, #48
 150:Core/Src/main.c **** 
 925              		.loc 1 150 36 view .LVU281
 926 01cc 4277     		strb	r2, [r0, #29]
 152:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 1] = (Sweep_state.curr_step_N / 10000) % 10 + '0';
 927              		.loc 1 152 7 is_stmt 1 view .LVU282
 152:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 1] = (Sweep_state.curr_step_N / 10000) % 10 + '0';
 928              		.loc 1 152 51 is_stmt 0 view .LVU283
 929 01ce 424C     		ldr	r4, .L33+64
 930 01d0 2268     		ldr	r2, [r4]
 152:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 1] = (Sweep_state.curr_step_N / 10000) % 10 + '0';
 931              		.loc 1 152 64 view .LVU284
 932 01d2 5209     		lsrs	r2, r2, #5
 933 01d4 A7FB0272 		umull	r7, r2, r7, r2
 934 01d8 D709     		lsrs	r7, r2, #7
 152:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 1] = (Sweep_state.curr_step_N / 10000) % 10 + '0';
 935              		.loc 1 152 74 view .LVU285
 936 01da A3FB07C2 		umull	ip, r2, r3, r7
 937 01de D208     		lsrs	r2, r2, #3
 938 01e0 02EB8202 		add	r2, r2, r2, lsl #2
 939 01e4 A7EB4202 		sub	r2, r7, r2, lsl #1
 152:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 1] = (Sweep_state.curr_step_N / 10000) % 10 + '0';
 940              		.loc 1 152 79 view .LVU286
 941 01e8 3032     		adds	r2, r2, #48
 152:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 1] = (Sweep_state.curr_step_N / 10000) % 10 + '0';
 942              		.loc 1 152 37 view .LVU287
 943 01ea 0273     		strb	r2, [r0, #12]
 153:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 2] = (Sweep_state.curr_step_N / 1000) % 10 + '0';
 944              		.loc 1 153 7 is_stmt 1 view .LVU288
 153:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 2] = (Sweep_state.curr_step_N / 1000) % 10 + '0';
 945              		.loc 1 153 51 is_stmt 0 view .LVU289
 946 01ec 2268     		ldr	r2, [r4]
 153:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 2] = (Sweep_state.curr_step_N / 1000) % 10 + '0';
 947              		.loc 1 153 64 view .LVU290
 948 01ee A6FB0262 		umull	r6, r2, r6, r2
 949 01f2 560B     		lsrs	r6, r2, #13
 153:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 2] = (Sweep_state.curr_step_N / 1000) % 10 + '0';
 950              		.loc 1 153 73 view .LVU291
 951 01f4 A3FB0672 		umull	r7, r2, r3, r6
 952 01f8 D208     		lsrs	r2, r2, #3
 953 01fa 02EB8202 		add	r2, r2, r2, lsl #2
 954 01fe A6EB4202 		sub	r2, r6, r2, lsl #1
 153:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 2] = (Sweep_state.curr_step_N / 1000) % 10 + '0';
 955              		.loc 1 153 78 view .LVU292
 956 0202 3032     		adds	r2, r2, #48
 153:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 2] = (Sweep_state.curr_step_N / 1000) % 10 + '0';
 957              		.loc 1 153 37 view .LVU293
 958 0204 4273     		strb	r2, [r0, #13]
 154:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 3] = (Sweep_state.curr_step_N / 100) % 10 + '0';
 959              		.loc 1 154 7 is_stmt 1 view .LVU294
 154:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 3] = (Sweep_state.curr_step_N / 100) % 10 + '0';
 960              		.loc 1 154 51 is_stmt 0 view .LVU295
 961 0206 2268     		ldr	r2, [r4]
 154:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 3] = (Sweep_state.curr_step_N / 100) % 10 + '0';
 962              		.loc 1 154 64 view .LVU296
 963 0208 A5FB0252 		umull	r5, r2, r5, r2
ARM GAS  /tmp/ccUsVHhJ.s 			page 45


 964 020c 9509     		lsrs	r5, r2, #6
 154:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 3] = (Sweep_state.curr_step_N / 100) % 10 + '0';
 965              		.loc 1 154 72 view .LVU297
 966 020e A3FB0562 		umull	r6, r2, r3, r5
 967 0212 D208     		lsrs	r2, r2, #3
 968 0214 02EB8202 		add	r2, r2, r2, lsl #2
 969 0218 A5EB4202 		sub	r2, r5, r2, lsl #1
 154:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 3] = (Sweep_state.curr_step_N / 100) % 10 + '0';
 970              		.loc 1 154 77 view .LVU298
 971 021c 3032     		adds	r2, r2, #48
 154:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 3] = (Sweep_state.curr_step_N / 100) % 10 + '0';
 972              		.loc 1 154 37 view .LVU299
 973 021e 8273     		strb	r2, [r0, #14]
 155:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 4] = (Sweep_state.curr_step_N / 10) % 10 + '0';
 974              		.loc 1 155 7 is_stmt 1 view .LVU300
 155:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 4] = (Sweep_state.curr_step_N / 10) % 10 + '0';
 975              		.loc 1 155 51 is_stmt 0 view .LVU301
 976 0220 2268     		ldr	r2, [r4]
 155:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 4] = (Sweep_state.curr_step_N / 10) % 10 + '0';
 977              		.loc 1 155 64 view .LVU302
 978 0222 A1FB0212 		umull	r1, r2, r1, r2
 979 0226 5109     		lsrs	r1, r2, #5
 155:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 4] = (Sweep_state.curr_step_N / 10) % 10 + '0';
 980              		.loc 1 155 71 view .LVU303
 981 0228 A3FB0152 		umull	r5, r2, r3, r1
 982 022c D208     		lsrs	r2, r2, #3
 983 022e 02EB8202 		add	r2, r2, r2, lsl #2
 984 0232 A1EB4202 		sub	r2, r1, r2, lsl #1
 155:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 4] = (Sweep_state.curr_step_N / 10) % 10 + '0';
 985              		.loc 1 155 76 view .LVU304
 986 0236 3032     		adds	r2, r2, #48
 155:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 4] = (Sweep_state.curr_step_N / 10) % 10 + '0';
 987              		.loc 1 155 37 view .LVU305
 988 0238 C273     		strb	r2, [r0, #15]
 156:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 5] = (Sweep_state.curr_step_N / 1) % 10 + '0';
 989              		.loc 1 156 7 is_stmt 1 view .LVU306
 156:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 5] = (Sweep_state.curr_step_N / 1) % 10 + '0';
 990              		.loc 1 156 51 is_stmt 0 view .LVU307
 991 023a 2168     		ldr	r1, [r4]
 156:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 5] = (Sweep_state.curr_step_N / 1) % 10 + '0';
 992              		.loc 1 156 64 view .LVU308
 993 023c A3FB0121 		umull	r2, r1, r3, r1
 994 0240 C908     		lsrs	r1, r1, #3
 156:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 5] = (Sweep_state.curr_step_N / 1) % 10 + '0';
 995              		.loc 1 156 70 view .LVU309
 996 0242 A3FB0152 		umull	r5, r2, r3, r1
 997 0246 D208     		lsrs	r2, r2, #3
 998 0248 02EB8202 		add	r2, r2, r2, lsl #2
 999 024c A1EB4202 		sub	r2, r1, r2, lsl #1
 156:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 5] = (Sweep_state.curr_step_N / 1) % 10 + '0';
 1000              		.loc 1 156 75 view .LVU310
 1001 0250 3032     		adds	r2, r2, #48
 156:Core/Src/main.c ****       ADC_msg[ADC_msg_step_pos + 5] = (Sweep_state.curr_step_N / 1) % 10 + '0';
 1002              		.loc 1 156 37 view .LVU311
 1003 0252 0274     		strb	r2, [r0, #16]
 157:Core/Src/main.c ****       
 1004              		.loc 1 157 7 is_stmt 1 view .LVU312
ARM GAS  /tmp/ccUsVHhJ.s 			page 46


 157:Core/Src/main.c ****       
 1005              		.loc 1 157 51 is_stmt 0 view .LVU313
 1006 0254 2268     		ldr	r2, [r4]
 157:Core/Src/main.c ****       
 1007              		.loc 1 157 69 view .LVU314
 1008 0256 A3FB0213 		umull	r1, r3, r3, r2
 1009 025a DB08     		lsrs	r3, r3, #3
 1010 025c 03EB8303 		add	r3, r3, r3, lsl #2
 1011 0260 A2EB4303 		sub	r3, r2, r3, lsl #1
 157:Core/Src/main.c ****       
 1012              		.loc 1 157 74 view .LVU315
 1013 0264 3033     		adds	r3, r3, #48
 157:Core/Src/main.c ****       
 1014              		.loc 1 157 37 view .LVU316
 1015 0266 4374     		strb	r3, [r0, #17]
 160:Core/Src/main.c ****       //HAL_GPIO_TogglePin(LED_RED_GPIO_Port, LED_RED_Pin);
 1016              		.loc 1 160 7 is_stmt 1 view .LVU317
 1017 0268 2021     		movs	r1, #32
 1018 026a FFF7FEFF 		bl	CDC_Transmit_FS
 1019              	.LVL31:
 163:Core/Src/main.c ****         Sweep_state.curr_step_N = 0;
 1020              		.loc 1 163 7 view .LVU318
 163:Core/Src/main.c ****         Sweep_state.curr_step_N = 0;
 1021              		.loc 1 163 22 is_stmt 0 view .LVU319
 1022 026e 2368     		ldr	r3, [r4]
 163:Core/Src/main.c ****         Sweep_state.curr_step_N = 0;
 1023              		.loc 1 163 10 view .LVU320
 1024 0270 B3F57A7F 		cmp	r3, #1000
 1025 0274 7FF6E6AE 		bls	.L28
 1026              	.LBB14:
 164:Core/Src/main.c ****         HAL_GPIO_TogglePin(LED_RED_GPIO_Port, LED_RED_Pin);
 1027              		.loc 1 164 9 is_stmt 1 view .LVU321
 164:Core/Src/main.c ****         HAL_GPIO_TogglePin(LED_RED_GPIO_Port, LED_RED_Pin);
 1028              		.loc 1 164 33 is_stmt 0 view .LVU322
 1029 0278 0022     		movs	r2, #0
 1030 027a 2260     		str	r2, [r4]
 165:Core/Src/main.c ****         HAL_DelayUS(10);
 1031              		.loc 1 165 9 is_stmt 1 view .LVU323
 1032 027c 4FF48041 		mov	r1, #16384
 1033 0280 0748     		ldr	r0, .L33+8
 1034 0282 FFF7FEFF 		bl	HAL_GPIO_TogglePin
 1035              	.LVL32:
 166:Core/Src/main.c ****         CDC_Transmit_FS((uint8_t *)"Sweep_start\n\r", 14);
 1036              		.loc 1 166 9 view .LVU324
 1037 0286 0A20     		movs	r0, #10
 1038 0288 FFF7FEFF 		bl	HAL_DelayUS
 1039              	.LVL33:
 167:Core/Src/main.c ****       }
 1040              		.loc 1 167 9 view .LVU325
 1041 028c 0E21     		movs	r1, #14
 1042 028e 1348     		ldr	r0, .L33+68
 1043 0290 FFF7FEFF 		bl	CDC_Transmit_FS
 1044              	.LVL34:
 1045 0294 D6E6     		b	.L28
 1046              	.L34:
 1047 0296 00BF     		.align	3
 1048              	.L33:
ARM GAS  /tmp/ccUsVHhJ.s 			page 47


 1049 0298 00E40B54 		.word	1410065408
 1050 029c 02000000 		.word	2
 1051 02a0 00040240 		.word	1073873920
 1052 02a4 00000000 		.word	ADC1_buff_circular
 1053 02a8 00000000 		.word	hadc1
 1054 02ac 00000000 		.word	ADC_proc_shadow
 1055 02b0 00000000 		.word	ADC_proc
 1056 02b4 CDCCCCCC 		.word	-858993459
 1057 02b8 00000000 		.word	ADC_msg
 1058 02bc 834B0400 		.word	281475
 1059 02c0 6BCA5F6B 		.word	1801439851
 1060 02c4 83DE1B43 		.word	1125899907
 1061 02c8 C55A7C0A 		.word	175921861
 1062 02cc 5917B7D1 		.word	-776530087
 1063 02d0 D34D6210 		.word	274877907
 1064 02d4 1F85EB51 		.word	1374389535
 1065 02d8 00000000 		.word	Sweep_state
 1066 02dc 00000000 		.word	.LC0
 1067              	.LBE14:
 1068              		.cfi_endproc
 1069              	.LFE243:
 1071              		.global	ADC_msg
 1072              		.section	.data.ADC_msg,"aw"
 1073              		.align	2
 1076              	ADC_msg:
 1077 0000 63757272 		.ascii	"curr_step   ??????  ??????????\015\012\000"
 1077      5F737465 
 1077      70202020 
 1077      3F3F3F3F 
 1077      3F3F2020 
 1078              		.global	ADC1_buff_circular
 1079              		.section	.bss.ADC1_buff_circular,"aw",%nobits
 1080              		.align	2
 1083              	ADC1_buff_circular:
 1084 0000 00000000 		.space	200
 1084      00000000 
 1084      00000000 
 1084      00000000 
 1084      00000000 
 1085              		.global	curr_step_start_N
 1086              		.section	.bss.curr_step_start_N,"aw",%nobits
 1087              		.align	2
 1090              	curr_step_start_N:
 1091 0000 00000000 		.space	4
 1092              		.global	Sweep_state
 1093              		.section	.bss.Sweep_state,"aw",%nobits
 1094              		.align	2
 1097              	Sweep_state:
 1098 0000 00000000 		.space	12
 1098      00000000 
 1098      00000000 
 1099              		.global	ADC_proc_shadow
 1100              		.section	.bss.ADC_proc_shadow,"aw",%nobits
 1101              		.align	2
 1104              	ADC_proc_shadow:
 1105 0000 00000000 		.space	16
 1105      00000000 
ARM GAS  /tmp/ccUsVHhJ.s 			page 48


 1105      00000000 
 1105      00000000 
 1106              		.global	ADC_proc
 1107              		.section	.bss.ADC_proc,"aw",%nobits
 1108              		.align	2
 1111              	ADC_proc:
 1112 0000 00000000 		.space	16
 1112      00000000 
 1112      00000000 
 1112      00000000 
 1113              		.global	hdma_adc1
 1114              		.section	.bss.hdma_adc1,"aw",%nobits
 1115              		.align	2
 1118              	hdma_adc1:
 1119 0000 00000000 		.space	96
 1119      00000000 
 1119      00000000 
 1119      00000000 
 1119      00000000 
 1120              		.global	hadc1
 1121              		.section	.bss.hadc1,"aw",%nobits
 1122              		.align	2
 1125              	hadc1:
 1126 0000 00000000 		.space	72
 1126      00000000 
 1126      00000000 
 1126      00000000 
 1126      00000000 
 1127              		.text
 1128              	.Letext0:
 1129              		.file 3 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h"
 1130              		.file 4 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h"
 1131              		.file 5 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
 1132              		.file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h"
 1133              		.file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h"
 1134              		.file 8 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h"
 1135              		.file 9 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h"
 1136              		.file 10 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h"
 1137              		.file 11 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h"
 1138              		.file 12 "Core/Inc/main.h"
 1139              		.file 13 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h"
 1140              		.file 14 "USB_DEVICE/App/usbd_cdc_if.h"
 1141              		.file 15 "USB_DEVICE/App/usb_device.h"
 1142              		.file 16 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h"
 1143              		.file 17 "<built-in>"
ARM GAS  /tmp/ccUsVHhJ.s 			page 49


DEFINED SYMBOLS
                            *ABS*:00000000 main.c
     /tmp/ccUsVHhJ.s:21     .text.MX_GPIO_Init:00000000 $t
     /tmp/ccUsVHhJ.s:26     .text.MX_GPIO_Init:00000000 MX_GPIO_Init
     /tmp/ccUsVHhJ.s:242    .text.MX_GPIO_Init:0000010c $d
     /tmp/ccUsVHhJ.s:250    .text.MX_DMA_Init:00000000 $t
     /tmp/ccUsVHhJ.s:255    .text.MX_DMA_Init:00000000 MX_DMA_Init
     /tmp/ccUsVHhJ.s:304    .text.MX_DMA_Init:00000030 $d
     /tmp/ccUsVHhJ.s:309    .text.Error_Handler:00000000 $t
     /tmp/ccUsVHhJ.s:315    .text.Error_Handler:00000000 Error_Handler
     /tmp/ccUsVHhJ.s:347    .text.MX_ADC1_Init:00000000 $t
     /tmp/ccUsVHhJ.s:352    .text.MX_ADC1_Init:00000000 MX_ADC1_Init
     /tmp/ccUsVHhJ.s:460    .text.MX_ADC1_Init:00000068 $d
     /tmp/ccUsVHhJ.s:1125   .bss.hadc1:00000000 hadc1
     /tmp/ccUsVHhJ.s:466    .text.SystemClock_Config:00000000 $t
     /tmp/ccUsVHhJ.s:472    .text.SystemClock_Config:00000000 SystemClock_Config
     /tmp/ccUsVHhJ.s:620    .text.SystemClock_Config:000000a4 $d
     /tmp/ccUsVHhJ.s:627    .rodata.main.str1.4:00000000 $d
     /tmp/ccUsVHhJ.s:631    .text.main:00000000 $t
     /tmp/ccUsVHhJ.s:637    .text.main:00000000 main
     /tmp/ccUsVHhJ.s:1049   .text.main:00000298 $d
     /tmp/ccUsVHhJ.s:1083   .bss.ADC1_buff_circular:00000000 ADC1_buff_circular
     /tmp/ccUsVHhJ.s:1104   .bss.ADC_proc_shadow:00000000 ADC_proc_shadow
     /tmp/ccUsVHhJ.s:1111   .bss.ADC_proc:00000000 ADC_proc
     /tmp/ccUsVHhJ.s:1076   .data.ADC_msg:00000000 ADC_msg
     /tmp/ccUsVHhJ.s:1097   .bss.Sweep_state:00000000 Sweep_state
     /tmp/ccUsVHhJ.s:1073   .data.ADC_msg:00000000 $d
     /tmp/ccUsVHhJ.s:1080   .bss.ADC1_buff_circular:00000000 $d
     /tmp/ccUsVHhJ.s:1090   .bss.curr_step_start_N:00000000 curr_step_start_N
     /tmp/ccUsVHhJ.s:1087   .bss.curr_step_start_N:00000000 $d
     /tmp/ccUsVHhJ.s:1094   .bss.Sweep_state:00000000 $d
     /tmp/ccUsVHhJ.s:1101   .bss.ADC_proc_shadow:00000000 $d
     /tmp/ccUsVHhJ.s:1108   .bss.ADC_proc:00000000 $d
     /tmp/ccUsVHhJ.s:1118   .bss.hdma_adc1:00000000 hdma_adc1
     /tmp/ccUsVHhJ.s:1115   .bss.hdma_adc1:00000000 $d
     /tmp/ccUsVHhJ.s:1122   .bss.hadc1:00000000 $d

UNDEFINED SYMBOLS
HAL_GPIO_WritePin
HAL_GPIO_Init
HAL_NVIC_SetPriority
HAL_NVIC_EnableIRQ
HAL_ADC_Init
HAL_ADC_ConfigChannel
memset
HAL_RCC_OscConfig
HAL_RCC_ClockConfig
__aeabi_ldivmod
HAL_Init
MX_USB_DEVICE_Init
HAL_ADC_Start_DMA
CDC_Transmit_FS
HAL_GPIO_TogglePin
HAL_DelayUS
