ARM GAS  /tmp/ccfiAGGE.s 			page 1


   1              		.cpu cortex-m4
   2              		.arch armv7e-m
   3              		.fpu fpv4-sp-d16
   4              		.eabi_attribute 27, 1
   5              		.eabi_attribute 28, 1
   6              		.eabi_attribute 20, 1
   7              		.eabi_attribute 21, 1
   8              		.eabi_attribute 23, 3
   9              		.eabi_attribute 24, 1
  10              		.eabi_attribute 25, 1
  11              		.eabi_attribute 26, 1
  12              		.eabi_attribute 30, 1
  13              		.eabi_attribute 34, 1
  14              		.eabi_attribute 18, 4
  15              		.file	"stm32f4xx_hal_cortex.c"
  16              		.text
  17              	.Ltext0:
  18              		.cfi_sections	.debug_frame
  19              		.file 1 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c"
  20              		.section	.text.__NVIC_EnableIRQ,"ax",%progbits
  21              		.align	1
  22              		.syntax unified
  23              		.thumb
  24              		.thumb_func
  26              	__NVIC_EnableIRQ:
  27              	.LVL0:
  28              	.LFB108:
  29              		.file 2 "Drivers/CMSIS/Include/core_cm4.h"
   1:Drivers/CMSIS/Include/core_cm4.h **** /**************************************************************************//**
   2:Drivers/CMSIS/Include/core_cm4.h ****  * @file     core_cm4.h
   3:Drivers/CMSIS/Include/core_cm4.h ****  * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
   4:Drivers/CMSIS/Include/core_cm4.h ****  * @version  V5.1.2
   5:Drivers/CMSIS/Include/core_cm4.h ****  * @date     04. June 2021
   6:Drivers/CMSIS/Include/core_cm4.h ****  ******************************************************************************/
   7:Drivers/CMSIS/Include/core_cm4.h **** /*
   8:Drivers/CMSIS/Include/core_cm4.h ****  * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
   9:Drivers/CMSIS/Include/core_cm4.h ****  *
  10:Drivers/CMSIS/Include/core_cm4.h ****  * SPDX-License-Identifier: Apache-2.0
  11:Drivers/CMSIS/Include/core_cm4.h ****  *
  12:Drivers/CMSIS/Include/core_cm4.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
  13:Drivers/CMSIS/Include/core_cm4.h ****  * not use this file except in compliance with the License.
  14:Drivers/CMSIS/Include/core_cm4.h ****  * You may obtain a copy of the License at
  15:Drivers/CMSIS/Include/core_cm4.h ****  *
  16:Drivers/CMSIS/Include/core_cm4.h ****  * www.apache.org/licenses/LICENSE-2.0
  17:Drivers/CMSIS/Include/core_cm4.h ****  *
  18:Drivers/CMSIS/Include/core_cm4.h ****  * Unless required by applicable law or agreed to in writing, software
  19:Drivers/CMSIS/Include/core_cm4.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20:Drivers/CMSIS/Include/core_cm4.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21:Drivers/CMSIS/Include/core_cm4.h ****  * See the License for the specific language governing permissions and
  22:Drivers/CMSIS/Include/core_cm4.h ****  * limitations under the License.
  23:Drivers/CMSIS/Include/core_cm4.h ****  */
  24:Drivers/CMSIS/Include/core_cm4.h **** 
  25:Drivers/CMSIS/Include/core_cm4.h **** #if   defined ( __ICCARM__ )
  26:Drivers/CMSIS/Include/core_cm4.h ****   #pragma system_include         /* treat file as system include file for MISRA check */
  27:Drivers/CMSIS/Include/core_cm4.h **** #elif defined (__clang__)
  28:Drivers/CMSIS/Include/core_cm4.h ****   #pragma clang system_header   /* treat file as system include file */
  29:Drivers/CMSIS/Include/core_cm4.h **** #endif
ARM GAS  /tmp/ccfiAGGE.s 			page 2


  30:Drivers/CMSIS/Include/core_cm4.h **** 
  31:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CORE_CM4_H_GENERIC
  32:Drivers/CMSIS/Include/core_cm4.h **** #define __CORE_CM4_H_GENERIC
  33:Drivers/CMSIS/Include/core_cm4.h **** 
  34:Drivers/CMSIS/Include/core_cm4.h **** #include <stdint.h>
  35:Drivers/CMSIS/Include/core_cm4.h **** 
  36:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus
  37:Drivers/CMSIS/Include/core_cm4.h ****  extern "C" {
  38:Drivers/CMSIS/Include/core_cm4.h **** #endif
  39:Drivers/CMSIS/Include/core_cm4.h **** 
  40:Drivers/CMSIS/Include/core_cm4.h **** /**
  41:Drivers/CMSIS/Include/core_cm4.h ****   \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
  42:Drivers/CMSIS/Include/core_cm4.h ****   CMSIS violates the following MISRA-C:2004 rules:
  43:Drivers/CMSIS/Include/core_cm4.h **** 
  44:Drivers/CMSIS/Include/core_cm4.h ****    \li Required Rule 8.5, object/function definition in header file.<br>
  45:Drivers/CMSIS/Include/core_cm4.h ****      Function definitions in header files are used to allow 'inlining'.
  46:Drivers/CMSIS/Include/core_cm4.h **** 
  47:Drivers/CMSIS/Include/core_cm4.h ****    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
  48:Drivers/CMSIS/Include/core_cm4.h ****      Unions are used for effective representation of core registers.
  49:Drivers/CMSIS/Include/core_cm4.h **** 
  50:Drivers/CMSIS/Include/core_cm4.h ****    \li Advisory Rule 19.7, Function-like macro defined.<br>
  51:Drivers/CMSIS/Include/core_cm4.h ****      Function-like macros are used to allow more efficient code.
  52:Drivers/CMSIS/Include/core_cm4.h ****  */
  53:Drivers/CMSIS/Include/core_cm4.h **** 
  54:Drivers/CMSIS/Include/core_cm4.h **** 
  55:Drivers/CMSIS/Include/core_cm4.h **** /*******************************************************************************
  56:Drivers/CMSIS/Include/core_cm4.h ****  *                 CMSIS definitions
  57:Drivers/CMSIS/Include/core_cm4.h ****  ******************************************************************************/
  58:Drivers/CMSIS/Include/core_cm4.h **** /**
  59:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup Cortex_M4
  60:Drivers/CMSIS/Include/core_cm4.h ****   @{
  61:Drivers/CMSIS/Include/core_cm4.h ****  */
  62:Drivers/CMSIS/Include/core_cm4.h **** 
  63:Drivers/CMSIS/Include/core_cm4.h **** #include "cmsis_version.h"
  64:Drivers/CMSIS/Include/core_cm4.h **** 
  65:Drivers/CMSIS/Include/core_cm4.h **** /* CMSIS CM4 definitions */
  66:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] C
  67:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  C
  68:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
  69:Drivers/CMSIS/Include/core_cm4.h ****                                     __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL
  70:Drivers/CMSIS/Include/core_cm4.h **** 
  71:Drivers/CMSIS/Include/core_cm4.h **** #define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
  72:Drivers/CMSIS/Include/core_cm4.h **** 
  73:Drivers/CMSIS/Include/core_cm4.h **** /** __FPU_USED indicates whether an FPU is used or not.
  74:Drivers/CMSIS/Include/core_cm4.h ****     For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun
  75:Drivers/CMSIS/Include/core_cm4.h **** */
  76:Drivers/CMSIS/Include/core_cm4.h **** #if defined ( __CC_ARM )
  77:Drivers/CMSIS/Include/core_cm4.h ****   #if defined __TARGET_FPU_VFP
  78:Drivers/CMSIS/Include/core_cm4.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
  79:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       1U
  80:Drivers/CMSIS/Include/core_cm4.h ****     #else
  81:Drivers/CMSIS/Include/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
  82:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       0U
  83:Drivers/CMSIS/Include/core_cm4.h ****     #endif
  84:Drivers/CMSIS/Include/core_cm4.h ****   #else
  85:Drivers/CMSIS/Include/core_cm4.h ****     #define __FPU_USED         0U
  86:Drivers/CMSIS/Include/core_cm4.h ****   #endif
ARM GAS  /tmp/ccfiAGGE.s 			page 3


  87:Drivers/CMSIS/Include/core_cm4.h **** 
  88:Drivers/CMSIS/Include/core_cm4.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  89:Drivers/CMSIS/Include/core_cm4.h ****   #if defined __ARM_FP
  90:Drivers/CMSIS/Include/core_cm4.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
  91:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       1U
  92:Drivers/CMSIS/Include/core_cm4.h ****     #else
  93:Drivers/CMSIS/Include/core_cm4.h ****       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN
  94:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       0U
  95:Drivers/CMSIS/Include/core_cm4.h ****     #endif
  96:Drivers/CMSIS/Include/core_cm4.h ****   #else
  97:Drivers/CMSIS/Include/core_cm4.h ****     #define __FPU_USED         0U
  98:Drivers/CMSIS/Include/core_cm4.h ****   #endif
  99:Drivers/CMSIS/Include/core_cm4.h **** 
 100:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __GNUC__ )
 101:Drivers/CMSIS/Include/core_cm4.h ****   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
 102:Drivers/CMSIS/Include/core_cm4.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
 103:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       1U
 104:Drivers/CMSIS/Include/core_cm4.h ****     #else
 105:Drivers/CMSIS/Include/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 106:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       0U
 107:Drivers/CMSIS/Include/core_cm4.h ****     #endif
 108:Drivers/CMSIS/Include/core_cm4.h ****   #else
 109:Drivers/CMSIS/Include/core_cm4.h ****     #define __FPU_USED         0U
 110:Drivers/CMSIS/Include/core_cm4.h ****   #endif
 111:Drivers/CMSIS/Include/core_cm4.h **** 
 112:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __ICCARM__ )
 113:Drivers/CMSIS/Include/core_cm4.h ****   #if defined __ARMVFP__
 114:Drivers/CMSIS/Include/core_cm4.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
 115:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       1U
 116:Drivers/CMSIS/Include/core_cm4.h ****     #else
 117:Drivers/CMSIS/Include/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 118:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       0U
 119:Drivers/CMSIS/Include/core_cm4.h ****     #endif
 120:Drivers/CMSIS/Include/core_cm4.h ****   #else
 121:Drivers/CMSIS/Include/core_cm4.h ****     #define __FPU_USED         0U
 122:Drivers/CMSIS/Include/core_cm4.h ****   #endif
 123:Drivers/CMSIS/Include/core_cm4.h **** 
 124:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __TI_ARM__ )
 125:Drivers/CMSIS/Include/core_cm4.h ****   #if defined __TI_VFP_SUPPORT__
 126:Drivers/CMSIS/Include/core_cm4.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
 127:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       1U
 128:Drivers/CMSIS/Include/core_cm4.h ****     #else
 129:Drivers/CMSIS/Include/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 130:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       0U
 131:Drivers/CMSIS/Include/core_cm4.h ****     #endif
 132:Drivers/CMSIS/Include/core_cm4.h ****   #else
 133:Drivers/CMSIS/Include/core_cm4.h ****     #define __FPU_USED         0U
 134:Drivers/CMSIS/Include/core_cm4.h ****   #endif
 135:Drivers/CMSIS/Include/core_cm4.h **** 
 136:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __TASKING__ )
 137:Drivers/CMSIS/Include/core_cm4.h ****   #if defined __FPU_VFP__
 138:Drivers/CMSIS/Include/core_cm4.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
 139:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       1U
 140:Drivers/CMSIS/Include/core_cm4.h ****     #else
 141:Drivers/CMSIS/Include/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 142:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       0U
 143:Drivers/CMSIS/Include/core_cm4.h ****     #endif
ARM GAS  /tmp/ccfiAGGE.s 			page 4


 144:Drivers/CMSIS/Include/core_cm4.h ****   #else
 145:Drivers/CMSIS/Include/core_cm4.h ****     #define __FPU_USED         0U
 146:Drivers/CMSIS/Include/core_cm4.h ****   #endif
 147:Drivers/CMSIS/Include/core_cm4.h **** 
 148:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __CSMC__ )
 149:Drivers/CMSIS/Include/core_cm4.h ****   #if ( __CSMC__ & 0x400U)
 150:Drivers/CMSIS/Include/core_cm4.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
 151:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       1U
 152:Drivers/CMSIS/Include/core_cm4.h ****     #else
 153:Drivers/CMSIS/Include/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 154:Drivers/CMSIS/Include/core_cm4.h ****       #define __FPU_USED       0U
 155:Drivers/CMSIS/Include/core_cm4.h ****     #endif
 156:Drivers/CMSIS/Include/core_cm4.h ****   #else
 157:Drivers/CMSIS/Include/core_cm4.h ****     #define __FPU_USED         0U
 158:Drivers/CMSIS/Include/core_cm4.h ****   #endif
 159:Drivers/CMSIS/Include/core_cm4.h **** 
 160:Drivers/CMSIS/Include/core_cm4.h **** #endif
 161:Drivers/CMSIS/Include/core_cm4.h **** 
 162:Drivers/CMSIS/Include/core_cm4.h **** #include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
 163:Drivers/CMSIS/Include/core_cm4.h **** 
 164:Drivers/CMSIS/Include/core_cm4.h **** 
 165:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus
 166:Drivers/CMSIS/Include/core_cm4.h **** }
 167:Drivers/CMSIS/Include/core_cm4.h **** #endif
 168:Drivers/CMSIS/Include/core_cm4.h **** 
 169:Drivers/CMSIS/Include/core_cm4.h **** #endif /* __CORE_CM4_H_GENERIC */
 170:Drivers/CMSIS/Include/core_cm4.h **** 
 171:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CMSIS_GENERIC
 172:Drivers/CMSIS/Include/core_cm4.h **** 
 173:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CORE_CM4_H_DEPENDANT
 174:Drivers/CMSIS/Include/core_cm4.h **** #define __CORE_CM4_H_DEPENDANT
 175:Drivers/CMSIS/Include/core_cm4.h **** 
 176:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus
 177:Drivers/CMSIS/Include/core_cm4.h ****  extern "C" {
 178:Drivers/CMSIS/Include/core_cm4.h **** #endif
 179:Drivers/CMSIS/Include/core_cm4.h **** 
 180:Drivers/CMSIS/Include/core_cm4.h **** /* check device defines and use defaults */
 181:Drivers/CMSIS/Include/core_cm4.h **** #if defined __CHECK_DEVICE_DEFINES
 182:Drivers/CMSIS/Include/core_cm4.h ****   #ifndef __CM4_REV
 183:Drivers/CMSIS/Include/core_cm4.h ****     #define __CM4_REV               0x0000U
 184:Drivers/CMSIS/Include/core_cm4.h ****     #warning "__CM4_REV not defined in device header file; using default!"
 185:Drivers/CMSIS/Include/core_cm4.h ****   #endif
 186:Drivers/CMSIS/Include/core_cm4.h **** 
 187:Drivers/CMSIS/Include/core_cm4.h ****   #ifndef __FPU_PRESENT
 188:Drivers/CMSIS/Include/core_cm4.h ****     #define __FPU_PRESENT             0U
 189:Drivers/CMSIS/Include/core_cm4.h ****     #warning "__FPU_PRESENT not defined in device header file; using default!"
 190:Drivers/CMSIS/Include/core_cm4.h ****   #endif
 191:Drivers/CMSIS/Include/core_cm4.h **** 
 192:Drivers/CMSIS/Include/core_cm4.h ****   #ifndef __MPU_PRESENT
 193:Drivers/CMSIS/Include/core_cm4.h ****     #define __MPU_PRESENT             0U
 194:Drivers/CMSIS/Include/core_cm4.h ****     #warning "__MPU_PRESENT not defined in device header file; using default!"
 195:Drivers/CMSIS/Include/core_cm4.h ****   #endif
 196:Drivers/CMSIS/Include/core_cm4.h **** 
 197:Drivers/CMSIS/Include/core_cm4.h ****   #ifndef __VTOR_PRESENT
 198:Drivers/CMSIS/Include/core_cm4.h ****     #define __VTOR_PRESENT             1U
 199:Drivers/CMSIS/Include/core_cm4.h ****     #warning "__VTOR_PRESENT not defined in device header file; using default!"
 200:Drivers/CMSIS/Include/core_cm4.h ****   #endif
ARM GAS  /tmp/ccfiAGGE.s 			page 5


 201:Drivers/CMSIS/Include/core_cm4.h **** 
 202:Drivers/CMSIS/Include/core_cm4.h ****   #ifndef __NVIC_PRIO_BITS
 203:Drivers/CMSIS/Include/core_cm4.h ****     #define __NVIC_PRIO_BITS          3U
 204:Drivers/CMSIS/Include/core_cm4.h ****     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
 205:Drivers/CMSIS/Include/core_cm4.h ****   #endif
 206:Drivers/CMSIS/Include/core_cm4.h **** 
 207:Drivers/CMSIS/Include/core_cm4.h ****   #ifndef __Vendor_SysTickConfig
 208:Drivers/CMSIS/Include/core_cm4.h ****     #define __Vendor_SysTickConfig    0U
 209:Drivers/CMSIS/Include/core_cm4.h ****     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
 210:Drivers/CMSIS/Include/core_cm4.h ****   #endif
 211:Drivers/CMSIS/Include/core_cm4.h **** #endif
 212:Drivers/CMSIS/Include/core_cm4.h **** 
 213:Drivers/CMSIS/Include/core_cm4.h **** /* IO definitions (access restrictions to peripheral registers) */
 214:Drivers/CMSIS/Include/core_cm4.h **** /**
 215:Drivers/CMSIS/Include/core_cm4.h ****     \defgroup CMSIS_glob_defs CMSIS Global Defines
 216:Drivers/CMSIS/Include/core_cm4.h **** 
 217:Drivers/CMSIS/Include/core_cm4.h ****     <strong>IO Type Qualifiers</strong> are used
 218:Drivers/CMSIS/Include/core_cm4.h ****     \li to specify the access to peripheral variables.
 219:Drivers/CMSIS/Include/core_cm4.h ****     \li for automatic generation of peripheral register debug information.
 220:Drivers/CMSIS/Include/core_cm4.h **** */
 221:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus
 222:Drivers/CMSIS/Include/core_cm4.h ****   #define   __I     volatile             /*!< Defines 'read only' permissions */
 223:Drivers/CMSIS/Include/core_cm4.h **** #else
 224:Drivers/CMSIS/Include/core_cm4.h ****   #define   __I     volatile const       /*!< Defines 'read only' permissions */
 225:Drivers/CMSIS/Include/core_cm4.h **** #endif
 226:Drivers/CMSIS/Include/core_cm4.h **** #define     __O     volatile             /*!< Defines 'write only' permissions */
 227:Drivers/CMSIS/Include/core_cm4.h **** #define     __IO    volatile             /*!< Defines 'read / write' permissions */
 228:Drivers/CMSIS/Include/core_cm4.h **** 
 229:Drivers/CMSIS/Include/core_cm4.h **** /* following defines should be used for structure members */
 230:Drivers/CMSIS/Include/core_cm4.h **** #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
 231:Drivers/CMSIS/Include/core_cm4.h **** #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
 232:Drivers/CMSIS/Include/core_cm4.h **** #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
 233:Drivers/CMSIS/Include/core_cm4.h **** 
 234:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group Cortex_M4 */
 235:Drivers/CMSIS/Include/core_cm4.h **** 
 236:Drivers/CMSIS/Include/core_cm4.h **** 
 237:Drivers/CMSIS/Include/core_cm4.h **** 
 238:Drivers/CMSIS/Include/core_cm4.h **** /*******************************************************************************
 239:Drivers/CMSIS/Include/core_cm4.h ****  *                 Register Abstraction
 240:Drivers/CMSIS/Include/core_cm4.h ****   Core Register contain:
 241:Drivers/CMSIS/Include/core_cm4.h ****   - Core Register
 242:Drivers/CMSIS/Include/core_cm4.h ****   - Core NVIC Register
 243:Drivers/CMSIS/Include/core_cm4.h ****   - Core SCB Register
 244:Drivers/CMSIS/Include/core_cm4.h ****   - Core SysTick Register
 245:Drivers/CMSIS/Include/core_cm4.h ****   - Core Debug Register
 246:Drivers/CMSIS/Include/core_cm4.h ****   - Core MPU Register
 247:Drivers/CMSIS/Include/core_cm4.h ****   - Core FPU Register
 248:Drivers/CMSIS/Include/core_cm4.h ****  ******************************************************************************/
 249:Drivers/CMSIS/Include/core_cm4.h **** /**
 250:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_core_register Defines and Type Definitions
 251:Drivers/CMSIS/Include/core_cm4.h ****   \brief Type definitions and defines for Cortex-M processor based devices.
 252:Drivers/CMSIS/Include/core_cm4.h **** */
 253:Drivers/CMSIS/Include/core_cm4.h **** 
 254:Drivers/CMSIS/Include/core_cm4.h **** /**
 255:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup    CMSIS_core_register
 256:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup   CMSIS_CORE  Status and Control Registers
 257:Drivers/CMSIS/Include/core_cm4.h ****   \brief      Core Register type definitions.
ARM GAS  /tmp/ccfiAGGE.s 			page 6


 258:Drivers/CMSIS/Include/core_cm4.h ****   @{
 259:Drivers/CMSIS/Include/core_cm4.h ****  */
 260:Drivers/CMSIS/Include/core_cm4.h **** 
 261:Drivers/CMSIS/Include/core_cm4.h **** /**
 262:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Union type to access the Application Program Status Register (APSR).
 263:Drivers/CMSIS/Include/core_cm4.h ****  */
 264:Drivers/CMSIS/Include/core_cm4.h **** typedef union
 265:Drivers/CMSIS/Include/core_cm4.h **** {
 266:Drivers/CMSIS/Include/core_cm4.h ****   struct
 267:Drivers/CMSIS/Include/core_cm4.h ****   {
 268:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
 269:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
 270:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
 271:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
 272:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
 273:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
 274:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
 275:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
 276:Drivers/CMSIS/Include/core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
 277:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
 278:Drivers/CMSIS/Include/core_cm4.h **** } APSR_Type;
 279:Drivers/CMSIS/Include/core_cm4.h **** 
 280:Drivers/CMSIS/Include/core_cm4.h **** /* APSR Register Definitions */
 281:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_N_Pos                         31U                                            /*!< APSR
 282:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR
 283:Drivers/CMSIS/Include/core_cm4.h **** 
 284:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Z_Pos                         30U                                            /*!< APSR
 285:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR
 286:Drivers/CMSIS/Include/core_cm4.h **** 
 287:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_C_Pos                         29U                                            /*!< APSR
 288:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR
 289:Drivers/CMSIS/Include/core_cm4.h **** 
 290:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_V_Pos                         28U                                            /*!< APSR
 291:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR
 292:Drivers/CMSIS/Include/core_cm4.h **** 
 293:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Q_Pos                         27U                                            /*!< APSR
 294:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR
 295:Drivers/CMSIS/Include/core_cm4.h **** 
 296:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_GE_Pos                        16U                                            /*!< APSR
 297:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR
 298:Drivers/CMSIS/Include/core_cm4.h **** 
 299:Drivers/CMSIS/Include/core_cm4.h **** 
 300:Drivers/CMSIS/Include/core_cm4.h **** /**
 301:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Union type to access the Interrupt Program Status Register (IPSR).
 302:Drivers/CMSIS/Include/core_cm4.h ****  */
 303:Drivers/CMSIS/Include/core_cm4.h **** typedef union
 304:Drivers/CMSIS/Include/core_cm4.h **** {
 305:Drivers/CMSIS/Include/core_cm4.h ****   struct
 306:Drivers/CMSIS/Include/core_cm4.h ****   {
 307:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
 308:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
 309:Drivers/CMSIS/Include/core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
 310:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
 311:Drivers/CMSIS/Include/core_cm4.h **** } IPSR_Type;
 312:Drivers/CMSIS/Include/core_cm4.h **** 
 313:Drivers/CMSIS/Include/core_cm4.h **** /* IPSR Register Definitions */
 314:Drivers/CMSIS/Include/core_cm4.h **** #define IPSR_ISR_Pos                        0U                                            /*!< IPSR
ARM GAS  /tmp/ccfiAGGE.s 			page 7


 315:Drivers/CMSIS/Include/core_cm4.h **** #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR
 316:Drivers/CMSIS/Include/core_cm4.h **** 
 317:Drivers/CMSIS/Include/core_cm4.h **** 
 318:Drivers/CMSIS/Include/core_cm4.h **** /**
 319:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
 320:Drivers/CMSIS/Include/core_cm4.h ****  */
 321:Drivers/CMSIS/Include/core_cm4.h **** typedef union
 322:Drivers/CMSIS/Include/core_cm4.h **** {
 323:Drivers/CMSIS/Include/core_cm4.h ****   struct
 324:Drivers/CMSIS/Include/core_cm4.h ****   {
 325:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
 326:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
 327:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
 328:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
 329:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
 330:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t T:1;                        /*!< bit:     24  Thumb bit */
 331:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
 332:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
 333:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
 334:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
 335:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
 336:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
 337:Drivers/CMSIS/Include/core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
 338:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
 339:Drivers/CMSIS/Include/core_cm4.h **** } xPSR_Type;
 340:Drivers/CMSIS/Include/core_cm4.h **** 
 341:Drivers/CMSIS/Include/core_cm4.h **** /* xPSR Register Definitions */
 342:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_N_Pos                         31U                                            /*!< xPSR
 343:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR
 344:Drivers/CMSIS/Include/core_cm4.h **** 
 345:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Z_Pos                         30U                                            /*!< xPSR
 346:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR
 347:Drivers/CMSIS/Include/core_cm4.h **** 
 348:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_C_Pos                         29U                                            /*!< xPSR
 349:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR
 350:Drivers/CMSIS/Include/core_cm4.h **** 
 351:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_V_Pos                         28U                                            /*!< xPSR
 352:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR
 353:Drivers/CMSIS/Include/core_cm4.h **** 
 354:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Q_Pos                         27U                                            /*!< xPSR
 355:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR
 356:Drivers/CMSIS/Include/core_cm4.h **** 
 357:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR
 358:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR
 359:Drivers/CMSIS/Include/core_cm4.h **** 
 360:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_T_Pos                         24U                                            /*!< xPSR
 361:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR
 362:Drivers/CMSIS/Include/core_cm4.h **** 
 363:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_GE_Pos                        16U                                            /*!< xPSR
 364:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR
 365:Drivers/CMSIS/Include/core_cm4.h **** 
 366:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR
 367:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR
 368:Drivers/CMSIS/Include/core_cm4.h **** 
 369:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ISR_Pos                        0U                                            /*!< xPSR
 370:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR
 371:Drivers/CMSIS/Include/core_cm4.h **** 
ARM GAS  /tmp/ccfiAGGE.s 			page 8


 372:Drivers/CMSIS/Include/core_cm4.h **** 
 373:Drivers/CMSIS/Include/core_cm4.h **** /**
 374:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Union type to access the Control Registers (CONTROL).
 375:Drivers/CMSIS/Include/core_cm4.h ****  */
 376:Drivers/CMSIS/Include/core_cm4.h **** typedef union
 377:Drivers/CMSIS/Include/core_cm4.h **** {
 378:Drivers/CMSIS/Include/core_cm4.h ****   struct
 379:Drivers/CMSIS/Include/core_cm4.h ****   {
 380:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
 381:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
 382:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
 383:Drivers/CMSIS/Include/core_cm4.h ****     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
 384:Drivers/CMSIS/Include/core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
 385:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
 386:Drivers/CMSIS/Include/core_cm4.h **** } CONTROL_Type;
 387:Drivers/CMSIS/Include/core_cm4.h **** 
 388:Drivers/CMSIS/Include/core_cm4.h **** /* CONTROL Register Definitions */
 389:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_FPCA_Pos                    2U                                            /*!< CONT
 390:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONT
 391:Drivers/CMSIS/Include/core_cm4.h **** 
 392:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_SPSEL_Pos                   1U                                            /*!< CONT
 393:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONT
 394:Drivers/CMSIS/Include/core_cm4.h **** 
 395:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_nPRIV_Pos                   0U                                            /*!< CONT
 396:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONT
 397:Drivers/CMSIS/Include/core_cm4.h **** 
 398:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_CORE */
 399:Drivers/CMSIS/Include/core_cm4.h **** 
 400:Drivers/CMSIS/Include/core_cm4.h **** 
 401:Drivers/CMSIS/Include/core_cm4.h **** /**
 402:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup    CMSIS_core_register
 403:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
 404:Drivers/CMSIS/Include/core_cm4.h ****   \brief      Type definitions for the NVIC Registers
 405:Drivers/CMSIS/Include/core_cm4.h ****   @{
 406:Drivers/CMSIS/Include/core_cm4.h ****  */
 407:Drivers/CMSIS/Include/core_cm4.h **** 
 408:Drivers/CMSIS/Include/core_cm4.h **** /**
 409:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
 410:Drivers/CMSIS/Include/core_cm4.h ****  */
 411:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
 412:Drivers/CMSIS/Include/core_cm4.h **** {
 413:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
 414:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED0[24U];
 415:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register 
 416:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED1[24U];
 417:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register *
 418:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED2[24U];
 419:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register
 420:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED3[24U];
 421:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
 422:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED4[56U];
 423:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bi
 424:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED5[644U];
 425:Drivers/CMSIS/Include/core_cm4.h ****   __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Regis
 426:Drivers/CMSIS/Include/core_cm4.h **** }  NVIC_Type;
 427:Drivers/CMSIS/Include/core_cm4.h **** 
 428:Drivers/CMSIS/Include/core_cm4.h **** /* Software Triggered Interrupt Register Definitions */
ARM GAS  /tmp/ccfiAGGE.s 			page 9


 429:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: I
 430:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: I
 431:Drivers/CMSIS/Include/core_cm4.h **** 
 432:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_NVIC */
 433:Drivers/CMSIS/Include/core_cm4.h **** 
 434:Drivers/CMSIS/Include/core_cm4.h **** 
 435:Drivers/CMSIS/Include/core_cm4.h **** /**
 436:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_core_register
 437:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_SCB     System Control Block (SCB)
 438:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Type definitions for the System Control Block Registers
 439:Drivers/CMSIS/Include/core_cm4.h ****   @{
 440:Drivers/CMSIS/Include/core_cm4.h ****  */
 441:Drivers/CMSIS/Include/core_cm4.h **** 
 442:Drivers/CMSIS/Include/core_cm4.h **** /**
 443:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Structure type to access the System Control Block (SCB).
 444:Drivers/CMSIS/Include/core_cm4.h ****  */
 445:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
 446:Drivers/CMSIS/Include/core_cm4.h **** {
 447:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
 448:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Regi
 449:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
 450:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset 
 451:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
 452:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register *
 453:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registe
 454:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State
 455:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Regist
 456:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
 457:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
 458:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register
 459:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
 460:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register 
 461:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
 462:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
 463:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
 464:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
 465:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Regis
 466:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED0[5U];
 467:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Regis
 468:Drivers/CMSIS/Include/core_cm4.h **** } SCB_Type;
 469:Drivers/CMSIS/Include/core_cm4.h **** 
 470:Drivers/CMSIS/Include/core_cm4.h **** /* SCB CPUID Register Definitions */
 471:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB 
 472:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB 
 473:Drivers/CMSIS/Include/core_cm4.h **** 
 474:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB 
 475:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB 
 476:Drivers/CMSIS/Include/core_cm4.h **** 
 477:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB 
 478:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB 
 479:Drivers/CMSIS/Include/core_cm4.h **** 
 480:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB 
 481:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB 
 482:Drivers/CMSIS/Include/core_cm4.h **** 
 483:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB 
 484:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB 
 485:Drivers/CMSIS/Include/core_cm4.h **** 
ARM GAS  /tmp/ccfiAGGE.s 			page 10


 486:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Interrupt Control State Register Definitions */
 487:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB 
 488:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB 
 489:Drivers/CMSIS/Include/core_cm4.h **** 
 490:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB 
 491:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB 
 492:Drivers/CMSIS/Include/core_cm4.h **** 
 493:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB 
 494:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB 
 495:Drivers/CMSIS/Include/core_cm4.h **** 
 496:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB 
 497:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB 
 498:Drivers/CMSIS/Include/core_cm4.h **** 
 499:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB 
 500:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB 
 501:Drivers/CMSIS/Include/core_cm4.h **** 
 502:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB 
 503:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB 
 504:Drivers/CMSIS/Include/core_cm4.h **** 
 505:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB 
 506:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB 
 507:Drivers/CMSIS/Include/core_cm4.h **** 
 508:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB 
 509:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB 
 510:Drivers/CMSIS/Include/core_cm4.h **** 
 511:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB 
 512:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB 
 513:Drivers/CMSIS/Include/core_cm4.h **** 
 514:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB 
 515:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB 
 516:Drivers/CMSIS/Include/core_cm4.h **** 
 517:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Vector Table Offset Register Definitions */
 518:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB 
 519:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB 
 520:Drivers/CMSIS/Include/core_cm4.h **** 
 521:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Application Interrupt and Reset Control Register Definitions */
 522:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB 
 523:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB 
 524:Drivers/CMSIS/Include/core_cm4.h **** 
 525:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB 
 526:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB 
 527:Drivers/CMSIS/Include/core_cm4.h **** 
 528:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB 
 529:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB 
 530:Drivers/CMSIS/Include/core_cm4.h **** 
 531:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB 
 532:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB 
 533:Drivers/CMSIS/Include/core_cm4.h **** 
 534:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB 
 535:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB 
 536:Drivers/CMSIS/Include/core_cm4.h **** 
 537:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB 
 538:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB 
 539:Drivers/CMSIS/Include/core_cm4.h **** 
 540:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB 
 541:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB 
 542:Drivers/CMSIS/Include/core_cm4.h **** 
ARM GAS  /tmp/ccfiAGGE.s 			page 11


 543:Drivers/CMSIS/Include/core_cm4.h **** /* SCB System Control Register Definitions */
 544:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB 
 545:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB 
 546:Drivers/CMSIS/Include/core_cm4.h **** 
 547:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB 
 548:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB 
 549:Drivers/CMSIS/Include/core_cm4.h **** 
 550:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB 
 551:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB 
 552:Drivers/CMSIS/Include/core_cm4.h **** 
 553:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Configuration Control Register Definitions */
 554:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB 
 555:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB 
 556:Drivers/CMSIS/Include/core_cm4.h **** 
 557:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB 
 558:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB 
 559:Drivers/CMSIS/Include/core_cm4.h **** 
 560:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB 
 561:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB 
 562:Drivers/CMSIS/Include/core_cm4.h **** 
 563:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB 
 564:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB 
 565:Drivers/CMSIS/Include/core_cm4.h **** 
 566:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB 
 567:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB 
 568:Drivers/CMSIS/Include/core_cm4.h **** 
 569:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB 
 570:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB 
 571:Drivers/CMSIS/Include/core_cm4.h **** 
 572:Drivers/CMSIS/Include/core_cm4.h **** /* SCB System Handler Control and State Register Definitions */
 573:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB 
 574:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB 
 575:Drivers/CMSIS/Include/core_cm4.h **** 
 576:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB 
 577:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB 
 578:Drivers/CMSIS/Include/core_cm4.h **** 
 579:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB 
 580:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB 
 581:Drivers/CMSIS/Include/core_cm4.h **** 
 582:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB 
 583:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB 
 584:Drivers/CMSIS/Include/core_cm4.h **** 
 585:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB 
 586:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB 
 587:Drivers/CMSIS/Include/core_cm4.h **** 
 588:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB 
 589:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB 
 590:Drivers/CMSIS/Include/core_cm4.h **** 
 591:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB 
 592:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB 
 593:Drivers/CMSIS/Include/core_cm4.h **** 
 594:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB 
 595:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB 
 596:Drivers/CMSIS/Include/core_cm4.h **** 
 597:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB 
 598:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB 
 599:Drivers/CMSIS/Include/core_cm4.h **** 
ARM GAS  /tmp/ccfiAGGE.s 			page 12


 600:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB 
 601:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB 
 602:Drivers/CMSIS/Include/core_cm4.h **** 
 603:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB 
 604:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB 
 605:Drivers/CMSIS/Include/core_cm4.h **** 
 606:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB 
 607:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB 
 608:Drivers/CMSIS/Include/core_cm4.h **** 
 609:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB 
 610:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB 
 611:Drivers/CMSIS/Include/core_cm4.h **** 
 612:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB 
 613:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB 
 614:Drivers/CMSIS/Include/core_cm4.h **** 
 615:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Configurable Fault Status Register Definitions */
 616:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB 
 617:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB 
 618:Drivers/CMSIS/Include/core_cm4.h **** 
 619:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB 
 620:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB 
 621:Drivers/CMSIS/Include/core_cm4.h **** 
 622:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB 
 623:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB 
 624:Drivers/CMSIS/Include/core_cm4.h **** 
 625:Drivers/CMSIS/Include/core_cm4.h **** /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
 626:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MMARVALID_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 7U)                 /*!< SCB 
 627:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB 
 628:Drivers/CMSIS/Include/core_cm4.h **** 
 629:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MLSPERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 5U)                 /*!< SCB 
 630:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB 
 631:Drivers/CMSIS/Include/core_cm4.h **** 
 632:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MSTKERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 4U)                 /*!< SCB 
 633:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB 
 634:Drivers/CMSIS/Include/core_cm4.h **** 
 635:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MUNSTKERR_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 3U)                 /*!< SCB 
 636:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB 
 637:Drivers/CMSIS/Include/core_cm4.h **** 
 638:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 1U)                 /*!< SCB 
 639:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB 
 640:Drivers/CMSIS/Include/core_cm4.h **** 
 641:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 0U)                 /*!< SCB 
 642:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB 
 643:Drivers/CMSIS/Include/core_cm4.h **** 
 644:Drivers/CMSIS/Include/core_cm4.h **** /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
 645:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB 
 646:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB 
 647:Drivers/CMSIS/Include/core_cm4.h **** 
 648:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB 
 649:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB 
 650:Drivers/CMSIS/Include/core_cm4.h **** 
 651:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB 
 652:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB 
 653:Drivers/CMSIS/Include/core_cm4.h **** 
 654:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB 
 655:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB 
 656:Drivers/CMSIS/Include/core_cm4.h **** 
ARM GAS  /tmp/ccfiAGGE.s 			page 13


 657:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB 
 658:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB 
 659:Drivers/CMSIS/Include/core_cm4.h **** 
 660:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB 
 661:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB 
 662:Drivers/CMSIS/Include/core_cm4.h **** 
 663:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB 
 664:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB 
 665:Drivers/CMSIS/Include/core_cm4.h **** 
 666:Drivers/CMSIS/Include/core_cm4.h **** /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
 667:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB 
 668:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB 
 669:Drivers/CMSIS/Include/core_cm4.h **** 
 670:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB 
 671:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB 
 672:Drivers/CMSIS/Include/core_cm4.h **** 
 673:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB 
 674:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB 
 675:Drivers/CMSIS/Include/core_cm4.h **** 
 676:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB 
 677:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB 
 678:Drivers/CMSIS/Include/core_cm4.h **** 
 679:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB 
 680:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB 
 681:Drivers/CMSIS/Include/core_cm4.h **** 
 682:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB 
 683:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB 
 684:Drivers/CMSIS/Include/core_cm4.h **** 
 685:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Hard Fault Status Register Definitions */
 686:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB 
 687:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB 
 688:Drivers/CMSIS/Include/core_cm4.h **** 
 689:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB 
 690:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB 
 691:Drivers/CMSIS/Include/core_cm4.h **** 
 692:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB 
 693:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB 
 694:Drivers/CMSIS/Include/core_cm4.h **** 
 695:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Debug Fault Status Register Definitions */
 696:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB 
 697:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB 
 698:Drivers/CMSIS/Include/core_cm4.h **** 
 699:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB 
 700:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB 
 701:Drivers/CMSIS/Include/core_cm4.h **** 
 702:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB 
 703:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB 
 704:Drivers/CMSIS/Include/core_cm4.h **** 
 705:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB 
 706:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB 
 707:Drivers/CMSIS/Include/core_cm4.h **** 
 708:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB 
 709:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB 
 710:Drivers/CMSIS/Include/core_cm4.h **** 
 711:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_SCB */
 712:Drivers/CMSIS/Include/core_cm4.h **** 
 713:Drivers/CMSIS/Include/core_cm4.h **** 
ARM GAS  /tmp/ccfiAGGE.s 			page 14


 714:Drivers/CMSIS/Include/core_cm4.h **** /**
 715:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_core_register
 716:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
 717:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Type definitions for the System Control and ID Register not in the SCB
 718:Drivers/CMSIS/Include/core_cm4.h ****   @{
 719:Drivers/CMSIS/Include/core_cm4.h ****  */
 720:Drivers/CMSIS/Include/core_cm4.h **** 
 721:Drivers/CMSIS/Include/core_cm4.h **** /**
 722:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Structure type to access the System Control and ID Register not in the SCB.
 723:Drivers/CMSIS/Include/core_cm4.h ****  */
 724:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
 725:Drivers/CMSIS/Include/core_cm4.h **** {
 726:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED0[1U];
 727:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Regist
 728:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
 729:Drivers/CMSIS/Include/core_cm4.h **** } SCnSCB_Type;
 730:Drivers/CMSIS/Include/core_cm4.h **** 
 731:Drivers/CMSIS/Include/core_cm4.h **** /* Interrupt Controller Type Register Definitions */
 732:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: I
 733:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: I
 734:Drivers/CMSIS/Include/core_cm4.h **** 
 735:Drivers/CMSIS/Include/core_cm4.h **** /* Auxiliary Control Register Definitions */
 736:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: 
 737:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: 
 738:Drivers/CMSIS/Include/core_cm4.h **** 
 739:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: 
 740:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: 
 741:Drivers/CMSIS/Include/core_cm4.h **** 
 742:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: 
 743:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: 
 744:Drivers/CMSIS/Include/core_cm4.h **** 
 745:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: 
 746:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: 
 747:Drivers/CMSIS/Include/core_cm4.h **** 
 748:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: 
 749:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: 
 750:Drivers/CMSIS/Include/core_cm4.h **** 
 751:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_SCnotSCB */
 752:Drivers/CMSIS/Include/core_cm4.h **** 
 753:Drivers/CMSIS/Include/core_cm4.h **** 
 754:Drivers/CMSIS/Include/core_cm4.h **** /**
 755:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_core_register
 756:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
 757:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Type definitions for the System Timer Registers.
 758:Drivers/CMSIS/Include/core_cm4.h ****   @{
 759:Drivers/CMSIS/Include/core_cm4.h ****  */
 760:Drivers/CMSIS/Include/core_cm4.h **** 
 761:Drivers/CMSIS/Include/core_cm4.h **** /**
 762:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Structure type to access the System Timer (SysTick).
 763:Drivers/CMSIS/Include/core_cm4.h ****  */
 764:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
 765:Drivers/CMSIS/Include/core_cm4.h **** {
 766:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Regis
 767:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
 768:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register *
 769:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
 770:Drivers/CMSIS/Include/core_cm4.h **** } SysTick_Type;
ARM GAS  /tmp/ccfiAGGE.s 			page 15


 771:Drivers/CMSIS/Include/core_cm4.h **** 
 772:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Control / Status Register Definitions */
 773:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysT
 774:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysT
 775:Drivers/CMSIS/Include/core_cm4.h **** 
 776:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysT
 777:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysT
 778:Drivers/CMSIS/Include/core_cm4.h **** 
 779:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysT
 780:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysT
 781:Drivers/CMSIS/Include/core_cm4.h **** 
 782:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysT
 783:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysT
 784:Drivers/CMSIS/Include/core_cm4.h **** 
 785:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Reload Register Definitions */
 786:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysT
 787:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysT
 788:Drivers/CMSIS/Include/core_cm4.h **** 
 789:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Current Register Definitions */
 790:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysT
 791:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysT
 792:Drivers/CMSIS/Include/core_cm4.h **** 
 793:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Calibration Register Definitions */
 794:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysT
 795:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysT
 796:Drivers/CMSIS/Include/core_cm4.h **** 
 797:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysT
 798:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysT
 799:Drivers/CMSIS/Include/core_cm4.h **** 
 800:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysT
 801:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysT
 802:Drivers/CMSIS/Include/core_cm4.h **** 
 803:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_SysTick */
 804:Drivers/CMSIS/Include/core_cm4.h **** 
 805:Drivers/CMSIS/Include/core_cm4.h **** 
 806:Drivers/CMSIS/Include/core_cm4.h **** /**
 807:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_core_register
 808:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
 809:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
 810:Drivers/CMSIS/Include/core_cm4.h ****   @{
 811:Drivers/CMSIS/Include/core_cm4.h ****  */
 812:Drivers/CMSIS/Include/core_cm4.h **** 
 813:Drivers/CMSIS/Include/core_cm4.h **** /**
 814:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
 815:Drivers/CMSIS/Include/core_cm4.h ****  */
 816:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
 817:Drivers/CMSIS/Include/core_cm4.h **** {
 818:Drivers/CMSIS/Include/core_cm4.h ****   __OM  union
 819:Drivers/CMSIS/Include/core_cm4.h ****   {
 820:Drivers/CMSIS/Include/core_cm4.h ****     __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
 821:Drivers/CMSIS/Include/core_cm4.h ****     __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
 822:Drivers/CMSIS/Include/core_cm4.h ****     __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
 823:Drivers/CMSIS/Include/core_cm4.h ****   }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
 824:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED0[864U];
 825:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
 826:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED1[15U];
 827:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
ARM GAS  /tmp/ccfiAGGE.s 			page 16


 828:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED2[15U];
 829:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
 830:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED3[32U];
 831:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED4[43U];
 832:Drivers/CMSIS/Include/core_cm4.h ****   __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
 833:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
 834:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED5[6U];
 835:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Re
 836:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Re
 837:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Re
 838:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Re
 839:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Re
 840:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Re
 841:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Re
 842:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Re
 843:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Re
 844:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Re
 845:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Re
 846:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Re
 847:Drivers/CMSIS/Include/core_cm4.h **** } ITM_Type;
 848:Drivers/CMSIS/Include/core_cm4.h **** 
 849:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Trace Privilege Register Definitions */
 850:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM 
 851:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM 
 852:Drivers/CMSIS/Include/core_cm4.h **** 
 853:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Trace Control Register Definitions */
 854:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM 
 855:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM 
 856:Drivers/CMSIS/Include/core_cm4.h **** 
 857:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM 
 858:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM 
 859:Drivers/CMSIS/Include/core_cm4.h **** 
 860:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM 
 861:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM 
 862:Drivers/CMSIS/Include/core_cm4.h **** 
 863:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM 
 864:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM 
 865:Drivers/CMSIS/Include/core_cm4.h **** 
 866:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM 
 867:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM 
 868:Drivers/CMSIS/Include/core_cm4.h **** 
 869:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM 
 870:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM 
 871:Drivers/CMSIS/Include/core_cm4.h **** 
 872:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM 
 873:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM 
 874:Drivers/CMSIS/Include/core_cm4.h **** 
 875:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM 
 876:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM 
 877:Drivers/CMSIS/Include/core_cm4.h **** 
 878:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM 
 879:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM 
 880:Drivers/CMSIS/Include/core_cm4.h **** 
 881:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Lock Status Register Definitions */
 882:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM 
 883:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM 
 884:Drivers/CMSIS/Include/core_cm4.h **** 
ARM GAS  /tmp/ccfiAGGE.s 			page 17


 885:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Access_Pos                  1U                                            /*!< ITM 
 886:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM 
 887:Drivers/CMSIS/Include/core_cm4.h **** 
 888:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Present_Pos                 0U                                            /*!< ITM 
 889:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM 
 890:Drivers/CMSIS/Include/core_cm4.h **** 
 891:Drivers/CMSIS/Include/core_cm4.h **** /*@}*/ /* end of group CMSIS_ITM */
 892:Drivers/CMSIS/Include/core_cm4.h **** 
 893:Drivers/CMSIS/Include/core_cm4.h **** 
 894:Drivers/CMSIS/Include/core_cm4.h **** /**
 895:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_core_register
 896:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
 897:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Type definitions for the Data Watchpoint and Trace (DWT)
 898:Drivers/CMSIS/Include/core_cm4.h ****   @{
 899:Drivers/CMSIS/Include/core_cm4.h ****  */
 900:Drivers/CMSIS/Include/core_cm4.h **** 
 901:Drivers/CMSIS/Include/core_cm4.h **** /**
 902:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
 903:Drivers/CMSIS/Include/core_cm4.h ****  */
 904:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
 905:Drivers/CMSIS/Include/core_cm4.h **** {
 906:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
 907:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
 908:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
 909:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Registe
 910:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
 911:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
 912:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Registe
 913:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register 
 914:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
 915:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
 916:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
 917:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED0[1U];
 918:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
 919:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
 920:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
 921:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED1[1U];
 922:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
 923:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
 924:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
 925:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED2[1U];
 926:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
 927:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
 928:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
 929:Drivers/CMSIS/Include/core_cm4.h **** } DWT_Type;
 930:Drivers/CMSIS/Include/core_cm4.h **** 
 931:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Control Register Definitions */
 932:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTR
 933:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTR
 934:Drivers/CMSIS/Include/core_cm4.h **** 
 935:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTR
 936:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTR
 937:Drivers/CMSIS/Include/core_cm4.h **** 
 938:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTR
 939:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTR
 940:Drivers/CMSIS/Include/core_cm4.h **** 
 941:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTR
ARM GAS  /tmp/ccfiAGGE.s 			page 18


 942:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTR
 943:Drivers/CMSIS/Include/core_cm4.h **** 
 944:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTR
 945:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTR
 946:Drivers/CMSIS/Include/core_cm4.h **** 
 947:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTR
 948:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTR
 949:Drivers/CMSIS/Include/core_cm4.h **** 
 950:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTR
 951:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTR
 952:Drivers/CMSIS/Include/core_cm4.h **** 
 953:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTR
 954:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTR
 955:Drivers/CMSIS/Include/core_cm4.h **** 
 956:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTR
 957:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTR
 958:Drivers/CMSIS/Include/core_cm4.h **** 
 959:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTR
 960:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTR
 961:Drivers/CMSIS/Include/core_cm4.h **** 
 962:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTR
 963:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTR
 964:Drivers/CMSIS/Include/core_cm4.h **** 
 965:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTR
 966:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTR
 967:Drivers/CMSIS/Include/core_cm4.h **** 
 968:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTR
 969:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTR
 970:Drivers/CMSIS/Include/core_cm4.h **** 
 971:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTR
 972:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTR
 973:Drivers/CMSIS/Include/core_cm4.h **** 
 974:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTR
 975:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTR
 976:Drivers/CMSIS/Include/core_cm4.h **** 
 977:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTR
 978:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTR
 979:Drivers/CMSIS/Include/core_cm4.h **** 
 980:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTR
 981:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTR
 982:Drivers/CMSIS/Include/core_cm4.h **** 
 983:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTR
 984:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTR
 985:Drivers/CMSIS/Include/core_cm4.h **** 
 986:Drivers/CMSIS/Include/core_cm4.h **** /* DWT CPI Count Register Definitions */
 987:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPI
 988:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPI
 989:Drivers/CMSIS/Include/core_cm4.h **** 
 990:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Exception Overhead Count Register Definitions */
 991:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXC
 992:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXC
 993:Drivers/CMSIS/Include/core_cm4.h **** 
 994:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Sleep Count Register Definitions */
 995:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLE
 996:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLE
 997:Drivers/CMSIS/Include/core_cm4.h **** 
 998:Drivers/CMSIS/Include/core_cm4.h **** /* DWT LSU Count Register Definitions */
ARM GAS  /tmp/ccfiAGGE.s 			page 19


 999:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSU
1000:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSU
1001:Drivers/CMSIS/Include/core_cm4.h **** 
1002:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Folded-instruction Count Register Definitions */
1003:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOL
1004:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOL
1005:Drivers/CMSIS/Include/core_cm4.h **** 
1006:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Comparator Mask Register Definitions */
1007:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MAS
1008:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MAS
1009:Drivers/CMSIS/Include/core_cm4.h **** 
1010:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Comparator Function Register Definitions */
1011:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUN
1012:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUN
1013:Drivers/CMSIS/Include/core_cm4.h **** 
1014:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUN
1015:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUN
1016:Drivers/CMSIS/Include/core_cm4.h **** 
1017:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUN
1018:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUN
1019:Drivers/CMSIS/Include/core_cm4.h **** 
1020:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUN
1021:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUN
1022:Drivers/CMSIS/Include/core_cm4.h **** 
1023:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUN
1024:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUN
1025:Drivers/CMSIS/Include/core_cm4.h **** 
1026:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUN
1027:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUN
1028:Drivers/CMSIS/Include/core_cm4.h **** 
1029:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUN
1030:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUN
1031:Drivers/CMSIS/Include/core_cm4.h **** 
1032:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUN
1033:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUN
1034:Drivers/CMSIS/Include/core_cm4.h **** 
1035:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUN
1036:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUN
1037:Drivers/CMSIS/Include/core_cm4.h **** 
1038:Drivers/CMSIS/Include/core_cm4.h **** /*@}*/ /* end of group CMSIS_DWT */
1039:Drivers/CMSIS/Include/core_cm4.h **** 
1040:Drivers/CMSIS/Include/core_cm4.h **** 
1041:Drivers/CMSIS/Include/core_cm4.h **** /**
1042:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_core_register
1043:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_TPI     Trace Port Interface (TPI)
1044:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Type definitions for the Trace Port Interface (TPI)
1045:Drivers/CMSIS/Include/core_cm4.h ****   @{
1046:Drivers/CMSIS/Include/core_cm4.h ****  */
1047:Drivers/CMSIS/Include/core_cm4.h **** 
1048:Drivers/CMSIS/Include/core_cm4.h **** /**
1049:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Structure type to access the Trace Port Interface Register (TPI).
1050:Drivers/CMSIS/Include/core_cm4.h ****  */
1051:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
1052:Drivers/CMSIS/Include/core_cm4.h **** {
1053:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Reg
1054:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Regis
1055:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED0[2U];
ARM GAS  /tmp/ccfiAGGE.s 			page 20


1056:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Reg
1057:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED1[55U];
1058:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register *
1059:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED2[131U];
1060:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Regis
1061:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Regi
1062:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counte
1063:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED3[759U];
1064:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
1065:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
1066:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
1067:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED4[1U];
1068:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
1069:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
1070:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
1071:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED5[39U];
1072:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
1073:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
1074:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED7[8U];
1075:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
1076:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
1077:Drivers/CMSIS/Include/core_cm4.h **** } TPI_Type;
1078:Drivers/CMSIS/Include/core_cm4.h **** 
1079:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */
1080:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACP
1081:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACP
1082:Drivers/CMSIS/Include/core_cm4.h **** 
1083:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Selected Pin Protocol Register Definitions */
1084:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPP
1085:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPP
1086:Drivers/CMSIS/Include/core_cm4.h **** 
1087:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Formatter and Flush Status Register Definitions */
1088:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFS
1089:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFS
1090:Drivers/CMSIS/Include/core_cm4.h **** 
1091:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFS
1092:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFS
1093:Drivers/CMSIS/Include/core_cm4.h **** 
1094:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFS
1095:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFS
1096:Drivers/CMSIS/Include/core_cm4.h **** 
1097:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFS
1098:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFS
1099:Drivers/CMSIS/Include/core_cm4.h **** 
1100:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Formatter and Flush Control Register Definitions */
1101:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFC
1102:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFC
1103:Drivers/CMSIS/Include/core_cm4.h **** 
1104:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFC
1105:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFC
1106:Drivers/CMSIS/Include/core_cm4.h **** 
1107:Drivers/CMSIS/Include/core_cm4.h **** /* TPI TRIGGER Register Definitions */
1108:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRI
1109:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRI
1110:Drivers/CMSIS/Include/core_cm4.h **** 
1111:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */
1112:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIF
ARM GAS  /tmp/ccfiAGGE.s 			page 21


1113:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIF
1114:Drivers/CMSIS/Include/core_cm4.h **** 
1115:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIF
1116:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIF
1117:Drivers/CMSIS/Include/core_cm4.h **** 
1118:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIF
1119:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIF
1120:Drivers/CMSIS/Include/core_cm4.h **** 
1121:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIF
1122:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIF
1123:Drivers/CMSIS/Include/core_cm4.h **** 
1124:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIF
1125:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIF
1126:Drivers/CMSIS/Include/core_cm4.h **** 
1127:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIF
1128:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIF
1129:Drivers/CMSIS/Include/core_cm4.h **** 
1130:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIF
1131:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIF
1132:Drivers/CMSIS/Include/core_cm4.h **** 
1133:Drivers/CMSIS/Include/core_cm4.h **** /* TPI ITATBCTR2 Register Definitions */
1134:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITA
1135:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITA
1136:Drivers/CMSIS/Include/core_cm4.h **** 
1137:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITA
1138:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITA
1139:Drivers/CMSIS/Include/core_cm4.h **** 
1140:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */
1141:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIF
1142:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIF
1143:Drivers/CMSIS/Include/core_cm4.h **** 
1144:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIF
1145:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIF
1146:Drivers/CMSIS/Include/core_cm4.h **** 
1147:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIF
1148:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIF
1149:Drivers/CMSIS/Include/core_cm4.h **** 
1150:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIF
1151:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIF
1152:Drivers/CMSIS/Include/core_cm4.h **** 
1153:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIF
1154:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIF
1155:Drivers/CMSIS/Include/core_cm4.h **** 
1156:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIF
1157:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIF
1158:Drivers/CMSIS/Include/core_cm4.h **** 
1159:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIF
1160:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIF
1161:Drivers/CMSIS/Include/core_cm4.h **** 
1162:Drivers/CMSIS/Include/core_cm4.h **** /* TPI ITATBCTR0 Register Definitions */
1163:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITA
1164:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITA
1165:Drivers/CMSIS/Include/core_cm4.h **** 
1166:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITA
1167:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITA
1168:Drivers/CMSIS/Include/core_cm4.h **** 
1169:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Integration Mode Control Register Definitions */
ARM GAS  /tmp/ccfiAGGE.s 			page 22


1170:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITC
1171:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITC
1172:Drivers/CMSIS/Include/core_cm4.h **** 
1173:Drivers/CMSIS/Include/core_cm4.h **** /* TPI DEVID Register Definitions */
1174:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEV
1175:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEV
1176:Drivers/CMSIS/Include/core_cm4.h **** 
1177:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEV
1178:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEV
1179:Drivers/CMSIS/Include/core_cm4.h **** 
1180:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEV
1181:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEV
1182:Drivers/CMSIS/Include/core_cm4.h **** 
1183:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEV
1184:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEV
1185:Drivers/CMSIS/Include/core_cm4.h **** 
1186:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEV
1187:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEV
1188:Drivers/CMSIS/Include/core_cm4.h **** 
1189:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEV
1190:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEV
1191:Drivers/CMSIS/Include/core_cm4.h **** 
1192:Drivers/CMSIS/Include/core_cm4.h **** /* TPI DEVTYPE Register Definitions */
1193:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEV
1194:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEV
1195:Drivers/CMSIS/Include/core_cm4.h **** 
1196:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEV
1197:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEV
1198:Drivers/CMSIS/Include/core_cm4.h **** 
1199:Drivers/CMSIS/Include/core_cm4.h **** /*@}*/ /* end of group CMSIS_TPI */
1200:Drivers/CMSIS/Include/core_cm4.h **** 
1201:Drivers/CMSIS/Include/core_cm4.h **** 
1202:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1203:Drivers/CMSIS/Include/core_cm4.h **** /**
1204:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_core_register
1205:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
1206:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Type definitions for the Memory Protection Unit (MPU)
1207:Drivers/CMSIS/Include/core_cm4.h ****   @{
1208:Drivers/CMSIS/Include/core_cm4.h ****  */
1209:Drivers/CMSIS/Include/core_cm4.h **** 
1210:Drivers/CMSIS/Include/core_cm4.h **** /**
1211:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Structure type to access the Memory Protection Unit (MPU).
1212:Drivers/CMSIS/Include/core_cm4.h ****  */
1213:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
1214:Drivers/CMSIS/Include/core_cm4.h **** {
1215:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
1216:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
1217:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
1218:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register
1219:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Re
1220:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address 
1221:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and
1222:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address 
1223:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and
1224:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address 
1225:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and
1226:Drivers/CMSIS/Include/core_cm4.h **** } MPU_Type;
ARM GAS  /tmp/ccfiAGGE.s 			page 23


1227:Drivers/CMSIS/Include/core_cm4.h **** 
1228:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_RALIASES                  4U
1229:Drivers/CMSIS/Include/core_cm4.h **** 
1230:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Type Register Definitions */
1231:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU 
1232:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU 
1233:Drivers/CMSIS/Include/core_cm4.h **** 
1234:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU 
1235:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU 
1236:Drivers/CMSIS/Include/core_cm4.h **** 
1237:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU 
1238:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU 
1239:Drivers/CMSIS/Include/core_cm4.h **** 
1240:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Control Register Definitions */
1241:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU 
1242:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU 
1243:Drivers/CMSIS/Include/core_cm4.h **** 
1244:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU 
1245:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU 
1246:Drivers/CMSIS/Include/core_cm4.h **** 
1247:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU 
1248:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU 
1249:Drivers/CMSIS/Include/core_cm4.h **** 
1250:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Region Number Register Definitions */
1251:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU 
1252:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU 
1253:Drivers/CMSIS/Include/core_cm4.h **** 
1254:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Region Base Address Register Definitions */
1255:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU 
1256:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU 
1257:Drivers/CMSIS/Include/core_cm4.h **** 
1258:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU 
1259:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU 
1260:Drivers/CMSIS/Include/core_cm4.h **** 
1261:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU 
1262:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU 
1263:Drivers/CMSIS/Include/core_cm4.h **** 
1264:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Region Attribute and Size Register Definitions */
1265:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU 
1266:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU 
1267:Drivers/CMSIS/Include/core_cm4.h **** 
1268:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_XN_Pos                    28U                                            /*!< MPU 
1269:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU 
1270:Drivers/CMSIS/Include/core_cm4.h **** 
1271:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_AP_Pos                    24U                                            /*!< MPU 
1272:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU 
1273:Drivers/CMSIS/Include/core_cm4.h **** 
1274:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU 
1275:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU 
1276:Drivers/CMSIS/Include/core_cm4.h **** 
1277:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_S_Pos                     18U                                            /*!< MPU 
1278:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU 
1279:Drivers/CMSIS/Include/core_cm4.h **** 
1280:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_C_Pos                     17U                                            /*!< MPU 
1281:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU 
1282:Drivers/CMSIS/Include/core_cm4.h **** 
1283:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_B_Pos                     16U                                            /*!< MPU 
ARM GAS  /tmp/ccfiAGGE.s 			page 24


1284:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU 
1285:Drivers/CMSIS/Include/core_cm4.h **** 
1286:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU 
1287:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU 
1288:Drivers/CMSIS/Include/core_cm4.h **** 
1289:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU 
1290:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU 
1291:Drivers/CMSIS/Include/core_cm4.h **** 
1292:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU 
1293:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU 
1294:Drivers/CMSIS/Include/core_cm4.h **** 
1295:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_MPU */
1296:Drivers/CMSIS/Include/core_cm4.h **** #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
1297:Drivers/CMSIS/Include/core_cm4.h **** 
1298:Drivers/CMSIS/Include/core_cm4.h **** 
1299:Drivers/CMSIS/Include/core_cm4.h **** /**
1300:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_core_register
1301:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_FPU     Floating Point Unit (FPU)
1302:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Type definitions for the Floating Point Unit (FPU)
1303:Drivers/CMSIS/Include/core_cm4.h ****   @{
1304:Drivers/CMSIS/Include/core_cm4.h ****  */
1305:Drivers/CMSIS/Include/core_cm4.h **** 
1306:Drivers/CMSIS/Include/core_cm4.h **** /**
1307:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Structure type to access the Floating Point Unit (FPU).
1308:Drivers/CMSIS/Include/core_cm4.h ****  */
1309:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
1310:Drivers/CMSIS/Include/core_cm4.h **** {
1311:Drivers/CMSIS/Include/core_cm4.h ****         uint32_t RESERVED0[1U];
1312:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control R
1313:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address R
1314:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Co
1315:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 
1316:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 
1317:Drivers/CMSIS/Include/core_cm4.h ****   __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 
1318:Drivers/CMSIS/Include/core_cm4.h **** } FPU_Type;
1319:Drivers/CMSIS/Include/core_cm4.h **** 
1320:Drivers/CMSIS/Include/core_cm4.h **** /* Floating-Point Context Control Register Definitions */
1321:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCC
1322:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCC
1323:Drivers/CMSIS/Include/core_cm4.h **** 
1324:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCC
1325:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCC
1326:Drivers/CMSIS/Include/core_cm4.h **** 
1327:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCC
1328:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCC
1329:Drivers/CMSIS/Include/core_cm4.h **** 
1330:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCC
1331:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCC
1332:Drivers/CMSIS/Include/core_cm4.h **** 
1333:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCC
1334:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCC
1335:Drivers/CMSIS/Include/core_cm4.h **** 
1336:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCC
1337:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCC
1338:Drivers/CMSIS/Include/core_cm4.h **** 
1339:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCC
1340:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCC
ARM GAS  /tmp/ccfiAGGE.s 			page 25


1341:Drivers/CMSIS/Include/core_cm4.h **** 
1342:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCC
1343:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCC
1344:Drivers/CMSIS/Include/core_cm4.h **** 
1345:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCC
1346:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCC
1347:Drivers/CMSIS/Include/core_cm4.h **** 
1348:Drivers/CMSIS/Include/core_cm4.h **** /* Floating-Point Context Address Register Definitions */
1349:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCA
1350:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCA
1351:Drivers/CMSIS/Include/core_cm4.h **** 
1352:Drivers/CMSIS/Include/core_cm4.h **** /* Floating-Point Default Status Control Register Definitions */
1353:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDS
1354:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDS
1355:Drivers/CMSIS/Include/core_cm4.h **** 
1356:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDS
1357:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDS
1358:Drivers/CMSIS/Include/core_cm4.h **** 
1359:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDS
1360:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDS
1361:Drivers/CMSIS/Include/core_cm4.h **** 
1362:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDS
1363:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDS
1364:Drivers/CMSIS/Include/core_cm4.h **** 
1365:Drivers/CMSIS/Include/core_cm4.h **** /* Media and FP Feature Register 0 Definitions */
1366:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR
1367:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR
1368:Drivers/CMSIS/Include/core_cm4.h **** 
1369:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR
1370:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR
1371:Drivers/CMSIS/Include/core_cm4.h **** 
1372:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR
1373:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR
1374:Drivers/CMSIS/Include/core_cm4.h **** 
1375:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR
1376:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR
1377:Drivers/CMSIS/Include/core_cm4.h **** 
1378:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR
1379:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR
1380:Drivers/CMSIS/Include/core_cm4.h **** 
1381:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR
1382:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR
1383:Drivers/CMSIS/Include/core_cm4.h **** 
1384:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR
1385:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR
1386:Drivers/CMSIS/Include/core_cm4.h **** 
1387:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR
1388:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR
1389:Drivers/CMSIS/Include/core_cm4.h **** 
1390:Drivers/CMSIS/Include/core_cm4.h **** /* Media and FP Feature Register 1 Definitions */
1391:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR
1392:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR
1393:Drivers/CMSIS/Include/core_cm4.h **** 
1394:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR
1395:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR
1396:Drivers/CMSIS/Include/core_cm4.h **** 
1397:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR
ARM GAS  /tmp/ccfiAGGE.s 			page 26


1398:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR
1399:Drivers/CMSIS/Include/core_cm4.h **** 
1400:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR
1401:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR
1402:Drivers/CMSIS/Include/core_cm4.h **** 
1403:Drivers/CMSIS/Include/core_cm4.h **** /* Media and FP Feature Register 2 Definitions */
1404:Drivers/CMSIS/Include/core_cm4.h **** 
1405:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR2_VFP_Misc_Pos              4U                                            /*!< MVFR
1406:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR2_VFP_Misc_Msk             (0xFUL << FPU_MVFR2_VFP_Misc_Pos)              /*!< MVFR
1407:Drivers/CMSIS/Include/core_cm4.h **** 
1408:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_FPU */
1409:Drivers/CMSIS/Include/core_cm4.h **** 
1410:Drivers/CMSIS/Include/core_cm4.h **** 
1411:Drivers/CMSIS/Include/core_cm4.h **** /**
1412:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_core_register
1413:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
1414:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Type definitions for the Core Debug Registers
1415:Drivers/CMSIS/Include/core_cm4.h ****   @{
1416:Drivers/CMSIS/Include/core_cm4.h ****  */
1417:Drivers/CMSIS/Include/core_cm4.h **** 
1418:Drivers/CMSIS/Include/core_cm4.h **** /**
1419:Drivers/CMSIS/Include/core_cm4.h ****   \brief  Structure type to access the Core Debug Register (CoreDebug).
1420:Drivers/CMSIS/Include/core_cm4.h ****  */
1421:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
1422:Drivers/CMSIS/Include/core_cm4.h **** {
1423:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status
1424:Drivers/CMSIS/Include/core_cm4.h ****   __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Reg
1425:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Registe
1426:Drivers/CMSIS/Include/core_cm4.h ****   __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Cont
1427:Drivers/CMSIS/Include/core_cm4.h **** } CoreDebug_Type;
1428:Drivers/CMSIS/Include/core_cm4.h **** 
1429:Drivers/CMSIS/Include/core_cm4.h **** /* Debug Halting Control and Status Register Definitions */
1430:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< Core
1431:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< Core
1432:Drivers/CMSIS/Include/core_cm4.h **** 
1433:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< Core
1434:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< Core
1435:Drivers/CMSIS/Include/core_cm4.h **** 
1436:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< Core
1437:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< Core
1438:Drivers/CMSIS/Include/core_cm4.h **** 
1439:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< Core
1440:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< Core
1441:Drivers/CMSIS/Include/core_cm4.h **** 
1442:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< Core
1443:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< Core
1444:Drivers/CMSIS/Include/core_cm4.h **** 
1445:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< Core
1446:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< Core
1447:Drivers/CMSIS/Include/core_cm4.h **** 
1448:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< Core
1449:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< Core
1450:Drivers/CMSIS/Include/core_cm4.h **** 
1451:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< Core
1452:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< Core
1453:Drivers/CMSIS/Include/core_cm4.h **** 
1454:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< Core
ARM GAS  /tmp/ccfiAGGE.s 			page 27


1455:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< Core
1456:Drivers/CMSIS/Include/core_cm4.h **** 
1457:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< Core
1458:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< Core
1459:Drivers/CMSIS/Include/core_cm4.h **** 
1460:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< Core
1461:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< Core
1462:Drivers/CMSIS/Include/core_cm4.h **** 
1463:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< Core
1464:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< Core
1465:Drivers/CMSIS/Include/core_cm4.h **** 
1466:Drivers/CMSIS/Include/core_cm4.h **** /* Debug Core Register Selector Register Definitions */
1467:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< Core
1468:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< Core
1469:Drivers/CMSIS/Include/core_cm4.h **** 
1470:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< Core
1471:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< Core
1472:Drivers/CMSIS/Include/core_cm4.h **** 
1473:Drivers/CMSIS/Include/core_cm4.h **** /* Debug Exception and Monitor Control Register Definitions */
1474:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< Core
1475:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< Core
1476:Drivers/CMSIS/Include/core_cm4.h **** 
1477:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< Core
1478:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< Core
1479:Drivers/CMSIS/Include/core_cm4.h **** 
1480:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< Core
1481:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< Core
1482:Drivers/CMSIS/Include/core_cm4.h **** 
1483:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< Core
1484:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< Core
1485:Drivers/CMSIS/Include/core_cm4.h **** 
1486:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< Core
1487:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< Core
1488:Drivers/CMSIS/Include/core_cm4.h **** 
1489:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< Core
1490:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< Core
1491:Drivers/CMSIS/Include/core_cm4.h **** 
1492:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< Core
1493:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< Core
1494:Drivers/CMSIS/Include/core_cm4.h **** 
1495:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< Core
1496:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< Core
1497:Drivers/CMSIS/Include/core_cm4.h **** 
1498:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< Core
1499:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< Core
1500:Drivers/CMSIS/Include/core_cm4.h **** 
1501:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< Core
1502:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< Core
1503:Drivers/CMSIS/Include/core_cm4.h **** 
1504:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< Core
1505:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< Core
1506:Drivers/CMSIS/Include/core_cm4.h **** 
1507:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< Core
1508:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< Core
1509:Drivers/CMSIS/Include/core_cm4.h **** 
1510:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< Core
1511:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< Core
ARM GAS  /tmp/ccfiAGGE.s 			page 28


1512:Drivers/CMSIS/Include/core_cm4.h **** 
1513:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_CoreDebug */
1514:Drivers/CMSIS/Include/core_cm4.h **** 
1515:Drivers/CMSIS/Include/core_cm4.h **** 
1516:Drivers/CMSIS/Include/core_cm4.h **** /**
1517:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup    CMSIS_core_register
1518:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup   CMSIS_core_bitfield     Core register bit field macros
1519:Drivers/CMSIS/Include/core_cm4.h ****   \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1520:Drivers/CMSIS/Include/core_cm4.h ****   @{
1521:Drivers/CMSIS/Include/core_cm4.h ****  */
1522:Drivers/CMSIS/Include/core_cm4.h **** 
1523:Drivers/CMSIS/Include/core_cm4.h **** /**
1524:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Mask and shift a bit field value for use in a register bit range.
1525:Drivers/CMSIS/Include/core_cm4.h ****   \param[in] field  Name of the register bit field.
1526:Drivers/CMSIS/Include/core_cm4.h ****   \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
1527:Drivers/CMSIS/Include/core_cm4.h ****   \return           Masked and shifted value.
1528:Drivers/CMSIS/Include/core_cm4.h **** */
1529:Drivers/CMSIS/Include/core_cm4.h **** #define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1530:Drivers/CMSIS/Include/core_cm4.h **** 
1531:Drivers/CMSIS/Include/core_cm4.h **** /**
1532:Drivers/CMSIS/Include/core_cm4.h ****   \brief     Mask and shift a register value to extract a bit filed value.
1533:Drivers/CMSIS/Include/core_cm4.h ****   \param[in] field  Name of the register bit field.
1534:Drivers/CMSIS/Include/core_cm4.h ****   \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
1535:Drivers/CMSIS/Include/core_cm4.h ****   \return           Masked and shifted bit field value.
1536:Drivers/CMSIS/Include/core_cm4.h **** */
1537:Drivers/CMSIS/Include/core_cm4.h **** #define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1538:Drivers/CMSIS/Include/core_cm4.h **** 
1539:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_core_bitfield */
1540:Drivers/CMSIS/Include/core_cm4.h **** 
1541:Drivers/CMSIS/Include/core_cm4.h **** 
1542:Drivers/CMSIS/Include/core_cm4.h **** /**
1543:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup    CMSIS_core_register
1544:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup   CMSIS_core_base     Core Definitions
1545:Drivers/CMSIS/Include/core_cm4.h ****   \brief      Definitions for base addresses, unions, and structures.
1546:Drivers/CMSIS/Include/core_cm4.h ****   @{
1547:Drivers/CMSIS/Include/core_cm4.h ****  */
1548:Drivers/CMSIS/Include/core_cm4.h **** 
1549:Drivers/CMSIS/Include/core_cm4.h **** /* Memory mapping of Core Hardware */
1550:Drivers/CMSIS/Include/core_cm4.h **** #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Bas
1551:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
1552:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
1553:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
1554:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address 
1555:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
1556:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
1557:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Bas
1558:Drivers/CMSIS/Include/core_cm4.h **** 
1559:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register 
1560:Drivers/CMSIS/Include/core_cm4.h **** #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct
1561:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration st
1562:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struc
1563:Drivers/CMSIS/Include/core_cm4.h **** #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct
1564:Drivers/CMSIS/Include/core_cm4.h **** #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct
1565:Drivers/CMSIS/Include/core_cm4.h **** #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct
1566:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration
1567:Drivers/CMSIS/Include/core_cm4.h **** 
1568:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
ARM GAS  /tmp/ccfiAGGE.s 			page 29


1569:Drivers/CMSIS/Include/core_cm4.h ****   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit *
1570:Drivers/CMSIS/Include/core_cm4.h ****   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit *
1571:Drivers/CMSIS/Include/core_cm4.h **** #endif
1572:Drivers/CMSIS/Include/core_cm4.h **** 
1573:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
1574:Drivers/CMSIS/Include/core_cm4.h **** #define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
1575:Drivers/CMSIS/Include/core_cm4.h **** 
1576:Drivers/CMSIS/Include/core_cm4.h **** /*@} */
1577:Drivers/CMSIS/Include/core_cm4.h **** 
1578:Drivers/CMSIS/Include/core_cm4.h **** 
1579:Drivers/CMSIS/Include/core_cm4.h **** 
1580:Drivers/CMSIS/Include/core_cm4.h **** /*******************************************************************************
1581:Drivers/CMSIS/Include/core_cm4.h ****  *                Hardware Abstraction Layer
1582:Drivers/CMSIS/Include/core_cm4.h ****   Core Function Interface contains:
1583:Drivers/CMSIS/Include/core_cm4.h ****   - Core NVIC Functions
1584:Drivers/CMSIS/Include/core_cm4.h ****   - Core SysTick Functions
1585:Drivers/CMSIS/Include/core_cm4.h ****   - Core Debug Functions
1586:Drivers/CMSIS/Include/core_cm4.h ****   - Core Register Access Functions
1587:Drivers/CMSIS/Include/core_cm4.h ****  ******************************************************************************/
1588:Drivers/CMSIS/Include/core_cm4.h **** /**
1589:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1590:Drivers/CMSIS/Include/core_cm4.h **** */
1591:Drivers/CMSIS/Include/core_cm4.h **** 
1592:Drivers/CMSIS/Include/core_cm4.h **** 
1593:Drivers/CMSIS/Include/core_cm4.h **** 
1594:Drivers/CMSIS/Include/core_cm4.h **** /* ##########################   NVIC functions  #################################### */
1595:Drivers/CMSIS/Include/core_cm4.h **** /**
1596:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_Core_FunctionInterface
1597:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1598:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Functions that manage interrupts and exceptions via the NVIC.
1599:Drivers/CMSIS/Include/core_cm4.h ****   @{
1600:Drivers/CMSIS/Include/core_cm4.h ****  */
1601:Drivers/CMSIS/Include/core_cm4.h **** 
1602:Drivers/CMSIS/Include/core_cm4.h **** #ifdef CMSIS_NVIC_VIRTUAL
1603:Drivers/CMSIS/Include/core_cm4.h ****   #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1604:Drivers/CMSIS/Include/core_cm4.h ****     #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1605:Drivers/CMSIS/Include/core_cm4.h ****   #endif
1606:Drivers/CMSIS/Include/core_cm4.h ****   #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1607:Drivers/CMSIS/Include/core_cm4.h **** #else
1608:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
1609:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
1610:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_EnableIRQ              __NVIC_EnableIRQ
1611:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
1612:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_DisableIRQ             __NVIC_DisableIRQ
1613:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
1614:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
1615:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
1616:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_GetActive              __NVIC_GetActive
1617:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_SetPriority            __NVIC_SetPriority
1618:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_GetPriority            __NVIC_GetPriority
1619:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_SystemReset            __NVIC_SystemReset
1620:Drivers/CMSIS/Include/core_cm4.h **** #endif /* CMSIS_NVIC_VIRTUAL */
1621:Drivers/CMSIS/Include/core_cm4.h **** 
1622:Drivers/CMSIS/Include/core_cm4.h **** #ifdef CMSIS_VECTAB_VIRTUAL
1623:Drivers/CMSIS/Include/core_cm4.h ****   #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1624:Drivers/CMSIS/Include/core_cm4.h ****     #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1625:Drivers/CMSIS/Include/core_cm4.h ****   #endif
ARM GAS  /tmp/ccfiAGGE.s 			page 30


1626:Drivers/CMSIS/Include/core_cm4.h ****   #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1627:Drivers/CMSIS/Include/core_cm4.h **** #else
1628:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_SetVector              __NVIC_SetVector
1629:Drivers/CMSIS/Include/core_cm4.h ****   #define NVIC_GetVector              __NVIC_GetVector
1630:Drivers/CMSIS/Include/core_cm4.h **** #endif  /* (CMSIS_VECTAB_VIRTUAL) */
1631:Drivers/CMSIS/Include/core_cm4.h **** 
1632:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_USER_IRQ_OFFSET          16
1633:Drivers/CMSIS/Include/core_cm4.h **** 
1634:Drivers/CMSIS/Include/core_cm4.h **** 
1635:Drivers/CMSIS/Include/core_cm4.h **** /* The following EXC_RETURN values are saved the LR on exception entry */
1636:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after ret
1637:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after retu
1638:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after retu
1639:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after ret
1640:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after retu
1641:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after retu
1642:Drivers/CMSIS/Include/core_cm4.h **** 
1643:Drivers/CMSIS/Include/core_cm4.h **** 
1644:Drivers/CMSIS/Include/core_cm4.h **** /**
1645:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Set Priority Grouping
1646:Drivers/CMSIS/Include/core_cm4.h ****   \details Sets the priority grouping field using the required unlock sequence.
1647:Drivers/CMSIS/Include/core_cm4.h ****            The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1648:Drivers/CMSIS/Include/core_cm4.h ****            Only values from 0..7 are used.
1649:Drivers/CMSIS/Include/core_cm4.h ****            In case of a conflict between priority grouping and available
1650:Drivers/CMSIS/Include/core_cm4.h ****            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1651:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]      PriorityGroup  Priority grouping field.
1652:Drivers/CMSIS/Include/core_cm4.h ****  */
1653:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1654:Drivers/CMSIS/Include/core_cm4.h **** {
1655:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t reg_value;
1656:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 a
1657:Drivers/CMSIS/Include/core_cm4.h **** 
1658:Drivers/CMSIS/Include/core_cm4.h ****   reg_value  =  SCB->AIRCR;                                                   /* read old register 
1659:Drivers/CMSIS/Include/core_cm4.h ****   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan
1660:Drivers/CMSIS/Include/core_cm4.h ****   reg_value  =  (reg_value                                   |
1661:Drivers/CMSIS/Include/core_cm4.h ****                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1662:Drivers/CMSIS/Include/core_cm4.h ****                 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key a
1663:Drivers/CMSIS/Include/core_cm4.h ****   SCB->AIRCR =  reg_value;
1664:Drivers/CMSIS/Include/core_cm4.h **** }
1665:Drivers/CMSIS/Include/core_cm4.h **** 
1666:Drivers/CMSIS/Include/core_cm4.h **** 
1667:Drivers/CMSIS/Include/core_cm4.h **** /**
1668:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Get Priority Grouping
1669:Drivers/CMSIS/Include/core_cm4.h ****   \details Reads the priority grouping field from the NVIC Interrupt Controller.
1670:Drivers/CMSIS/Include/core_cm4.h ****   \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1671:Drivers/CMSIS/Include/core_cm4.h ****  */
1672:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
1673:Drivers/CMSIS/Include/core_cm4.h **** {
1674:Drivers/CMSIS/Include/core_cm4.h ****   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1675:Drivers/CMSIS/Include/core_cm4.h **** }
1676:Drivers/CMSIS/Include/core_cm4.h **** 
1677:Drivers/CMSIS/Include/core_cm4.h **** 
1678:Drivers/CMSIS/Include/core_cm4.h **** /**
1679:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Enable Interrupt
1680:Drivers/CMSIS/Include/core_cm4.h ****   \details Enables a device specific interrupt in the NVIC interrupt controller.
1681:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]      IRQn  Device specific interrupt number.
1682:Drivers/CMSIS/Include/core_cm4.h ****   \note    IRQn must not be negative.
ARM GAS  /tmp/ccfiAGGE.s 			page 31


1683:Drivers/CMSIS/Include/core_cm4.h ****  */
1684:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1685:Drivers/CMSIS/Include/core_cm4.h **** {
  30              		.loc 2 1685 1 view -0
  31              		.cfi_startproc
  32              		@ args = 0, pretend = 0, frame = 0
  33              		@ frame_needed = 0, uses_anonymous_args = 0
  34              		@ link register save eliminated.
1686:Drivers/CMSIS/Include/core_cm4.h ****   if ((int32_t)(IRQn) >= 0)
  35              		.loc 2 1686 3 view .LVU1
  36              		.loc 2 1686 6 is_stmt 0 view .LVU2
  37 0000 0028     		cmp	r0, #0
  38              		.loc 2 1686 6 view .LVU3
  39 0002 07DB     		blt	.L1
1687:Drivers/CMSIS/Include/core_cm4.h ****   {
1688:Drivers/CMSIS/Include/core_cm4.h ****     __COMPILER_BARRIER();
  40              		.loc 2 1688 5 is_stmt 1 view .LVU4
1689:Drivers/CMSIS/Include/core_cm4.h ****     NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
  41              		.loc 2 1689 5 view .LVU5
  42              		.loc 2 1689 81 is_stmt 0 view .LVU6
  43 0004 00F01F02 		and	r2, r0, #31
  44              		.loc 2 1689 34 view .LVU7
  45 0008 4009     		lsrs	r0, r0, #5
  46              	.LVL1:
  47              		.loc 2 1689 45 view .LVU8
  48 000a 0123     		movs	r3, #1
  49 000c 9340     		lsls	r3, r3, r2
  50              		.loc 2 1689 43 view .LVU9
  51 000e 024A     		ldr	r2, .L3
  52 0010 42F82030 		str	r3, [r2, r0, lsl #2]
1690:Drivers/CMSIS/Include/core_cm4.h ****     __COMPILER_BARRIER();
  53              		.loc 2 1690 5 is_stmt 1 view .LVU10
  54              	.L1:
1691:Drivers/CMSIS/Include/core_cm4.h ****   }
1692:Drivers/CMSIS/Include/core_cm4.h **** }
  55              		.loc 2 1692 1 is_stmt 0 view .LVU11
  56 0014 7047     		bx	lr
  57              	.L4:
  58 0016 00BF     		.align	2
  59              	.L3:
  60 0018 00E100E0 		.word	-536813312
  61              		.cfi_endproc
  62              	.LFE108:
  64              		.section	.text.__NVIC_DisableIRQ,"ax",%progbits
  65              		.align	1
  66              		.syntax unified
  67              		.thumb
  68              		.thumb_func
  70              	__NVIC_DisableIRQ:
  71              	.LVL2:
  72              	.LFB110:
1693:Drivers/CMSIS/Include/core_cm4.h **** 
1694:Drivers/CMSIS/Include/core_cm4.h **** 
1695:Drivers/CMSIS/Include/core_cm4.h **** /**
1696:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Get Interrupt Enable status
1697:Drivers/CMSIS/Include/core_cm4.h ****   \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1698:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]      IRQn  Device specific interrupt number.
ARM GAS  /tmp/ccfiAGGE.s 			page 32


1699:Drivers/CMSIS/Include/core_cm4.h ****   \return             0  Interrupt is not enabled.
1700:Drivers/CMSIS/Include/core_cm4.h ****   \return             1  Interrupt is enabled.
1701:Drivers/CMSIS/Include/core_cm4.h ****   \note    IRQn must not be negative.
1702:Drivers/CMSIS/Include/core_cm4.h ****  */
1703:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1704:Drivers/CMSIS/Include/core_cm4.h **** {
1705:Drivers/CMSIS/Include/core_cm4.h ****   if ((int32_t)(IRQn) >= 0)
1706:Drivers/CMSIS/Include/core_cm4.h ****   {
1707:Drivers/CMSIS/Include/core_cm4.h ****     return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
1708:Drivers/CMSIS/Include/core_cm4.h ****   }
1709:Drivers/CMSIS/Include/core_cm4.h ****   else
1710:Drivers/CMSIS/Include/core_cm4.h ****   {
1711:Drivers/CMSIS/Include/core_cm4.h ****     return(0U);
1712:Drivers/CMSIS/Include/core_cm4.h ****   }
1713:Drivers/CMSIS/Include/core_cm4.h **** }
1714:Drivers/CMSIS/Include/core_cm4.h **** 
1715:Drivers/CMSIS/Include/core_cm4.h **** 
1716:Drivers/CMSIS/Include/core_cm4.h **** /**
1717:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Disable Interrupt
1718:Drivers/CMSIS/Include/core_cm4.h ****   \details Disables a device specific interrupt in the NVIC interrupt controller.
1719:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]      IRQn  Device specific interrupt number.
1720:Drivers/CMSIS/Include/core_cm4.h ****   \note    IRQn must not be negative.
1721:Drivers/CMSIS/Include/core_cm4.h ****  */
1722:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1723:Drivers/CMSIS/Include/core_cm4.h **** {
  73              		.loc 2 1723 1 is_stmt 1 view -0
  74              		.cfi_startproc
  75              		@ args = 0, pretend = 0, frame = 0
  76              		@ frame_needed = 0, uses_anonymous_args = 0
  77              		@ link register save eliminated.
1724:Drivers/CMSIS/Include/core_cm4.h ****   if ((int32_t)(IRQn) >= 0)
  78              		.loc 2 1724 3 view .LVU13
  79              		.loc 2 1724 6 is_stmt 0 view .LVU14
  80 0000 0028     		cmp	r0, #0
  81              		.loc 2 1724 6 view .LVU15
  82 0002 0CDB     		blt	.L5
1725:Drivers/CMSIS/Include/core_cm4.h ****   {
1726:Drivers/CMSIS/Include/core_cm4.h ****     NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
  83              		.loc 2 1726 5 is_stmt 1 view .LVU16
  84              		.loc 2 1726 81 is_stmt 0 view .LVU17
  85 0004 00F01F02 		and	r2, r0, #31
  86              		.loc 2 1726 34 view .LVU18
  87 0008 4009     		lsrs	r0, r0, #5
  88              	.LVL3:
  89              		.loc 2 1726 45 view .LVU19
  90 000a 0123     		movs	r3, #1
  91 000c 9340     		lsls	r3, r3, r2
  92              		.loc 2 1726 43 view .LVU20
  93 000e 2030     		adds	r0, r0, #32
  94 0010 034A     		ldr	r2, .L7
  95 0012 42F82030 		str	r3, [r2, r0, lsl #2]
1727:Drivers/CMSIS/Include/core_cm4.h ****     __DSB();
  96              		.loc 2 1727 5 is_stmt 1 view .LVU21
  97              	.LBB36:
  98              	.LBI36:
  99              		.file 3 "Drivers/CMSIS/Include/cmsis_gcc.h"
   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
ARM GAS  /tmp/ccfiAGGE.s 			page 33


   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.4.1
   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     27. May 2021
   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE
  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
ARM GAS  /tmp/ccfiAGGE.s 			page 34


  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
ARM GAS  /tmp/ccfiAGGE.s 			page 35


 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __COMPILER_BARRIER
 117:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 119:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* #########################  Startup and Lowlevel Init  ######################## */
 121:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START
 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Initializes data and bss sections
 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details This default implementations initialized all data and additional bss
 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            sections relying on .copy.table and .zero.table specified properly
 128:Drivers/CMSIS/Include/cmsis_gcc.h ****            in the used linker script.
 129:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 130:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
 132:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 133:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern void _start(void) __NO_RETURN;
 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 135:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
 136:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t const* src;
 137:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
 138:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
 139:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __copy_table_t;
 140:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 141:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
 142:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
 143:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
 144:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __zero_table_t;
 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 146:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_start__;
 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_end__;
 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_start__;
 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_end__;
 150:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 151:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
 152:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 153:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = pTable->src[i];
 154:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 156:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 157:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
 158:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 159:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = 0u;
 160:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
 161:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 162:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   _start();
 164:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 165:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START           __cmsis_start
 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 168:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP
 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP              __StackTop
 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 172:Drivers/CMSIS/Include/cmsis_gcc.h **** 
ARM GAS  /tmp/ccfiAGGE.s 			page 36


 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT
 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT             __StackLimit
 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 176:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE            __Vectors
 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 180:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(".vectors")))
 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 184:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 185:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
 186:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_SEAL
 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_SEAL              __StackSeal
 188:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 189:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 190:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_SIZE
 191:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __TZ_STACK_SEAL_SIZE      8U
 192:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 193:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 194:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_VALUE
 195:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL
 196:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 197:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 199:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
 200:Drivers/CMSIS/Include/cmsis_gcc.h ****   *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
 201:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 202:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 203:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 204:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 205:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
 206:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
 207:Drivers/CMSIS/Include/cmsis_gcc.h ****   Access to dedicated instructions
 208:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
 209:Drivers/CMSIS/Include/cmsis_gcc.h **** */
 210:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 211:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
 212:Drivers/CMSIS/Include/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
 213:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
 214:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
 215:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
 216:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
 217:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
 218:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 219:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
 220:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
 221:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
 222:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 223:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 224:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 225:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   No Operation
 226:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
 227:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 228:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
 229:Drivers/CMSIS/Include/cmsis_gcc.h **** 
ARM GAS  /tmp/ccfiAGGE.s 			page 37


 230:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 231:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Interrupt
 232:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
 233:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 234:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi":::"memory")
 235:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 237:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 238:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Event
 239:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
 240:Drivers/CMSIS/Include/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
 241:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 242:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe":::"memory")
 243:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 244:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 245:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 246:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Send Event
 247:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
 248:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 249:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 251:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 252:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 253:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
 254:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
 255:Drivers/CMSIS/Include/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
 256:Drivers/CMSIS/Include/cmsis_gcc.h ****            after the instruction has been completed.
 257:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 258:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
 259:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 260:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
 261:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 262:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 263:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 264:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 265:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
 266:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
 267:Drivers/CMSIS/Include/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
 268:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 269:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
 100              		.loc 3 269 27 view .LVU22
 101              	.LBB37:
 270:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 271:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
 102              		.loc 3 271 3 view .LVU23
 103              		.syntax unified
 104              	@ 271 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 105 0016 BFF34F8F 		dsb 0xF
 106              	@ 0 "" 2
 107              		.thumb
 108              		.syntax unified
 109              	.LBE37:
 110              	.LBE36:
1728:Drivers/CMSIS/Include/core_cm4.h ****     __ISB();
 111              		.loc 2 1728 5 view .LVU24
 112              	.LBB38:
 113              	.LBI38:
ARM GAS  /tmp/ccfiAGGE.s 			page 38


 258:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 114              		.loc 3 258 27 view .LVU25
 115              	.LBB39:
 260:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 116              		.loc 3 260 3 view .LVU26
 117              		.syntax unified
 118              	@ 260 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 119 001a BFF36F8F 		isb 0xF
 120              	@ 0 "" 2
 121              		.thumb
 122              		.syntax unified
 123              	.L5:
 124              	.LBE39:
 125              	.LBE38:
1729:Drivers/CMSIS/Include/core_cm4.h ****   }
1730:Drivers/CMSIS/Include/core_cm4.h **** }
 126              		.loc 2 1730 1 is_stmt 0 view .LVU27
 127 001e 7047     		bx	lr
 128              	.L8:
 129              		.align	2
 130              	.L7:
 131 0020 00E100E0 		.word	-536813312
 132              		.cfi_endproc
 133              	.LFE110:
 135              		.section	.text.__NVIC_SetPriority,"ax",%progbits
 136              		.align	1
 137              		.syntax unified
 138              		.thumb
 139              		.thumb_func
 141              	__NVIC_SetPriority:
 142              	.LVL4:
 143              	.LFB115:
1731:Drivers/CMSIS/Include/core_cm4.h **** 
1732:Drivers/CMSIS/Include/core_cm4.h **** 
1733:Drivers/CMSIS/Include/core_cm4.h **** /**
1734:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Get Pending Interrupt
1735:Drivers/CMSIS/Include/core_cm4.h ****   \details Reads the NVIC pending register and returns the pending bit for the specified device spe
1736:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]      IRQn  Device specific interrupt number.
1737:Drivers/CMSIS/Include/core_cm4.h ****   \return             0  Interrupt status is not pending.
1738:Drivers/CMSIS/Include/core_cm4.h ****   \return             1  Interrupt status is pending.
1739:Drivers/CMSIS/Include/core_cm4.h ****   \note    IRQn must not be negative.
1740:Drivers/CMSIS/Include/core_cm4.h ****  */
1741:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1742:Drivers/CMSIS/Include/core_cm4.h **** {
1743:Drivers/CMSIS/Include/core_cm4.h ****   if ((int32_t)(IRQn) >= 0)
1744:Drivers/CMSIS/Include/core_cm4.h ****   {
1745:Drivers/CMSIS/Include/core_cm4.h ****     return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
1746:Drivers/CMSIS/Include/core_cm4.h ****   }
1747:Drivers/CMSIS/Include/core_cm4.h ****   else
1748:Drivers/CMSIS/Include/core_cm4.h ****   {
1749:Drivers/CMSIS/Include/core_cm4.h ****     return(0U);
1750:Drivers/CMSIS/Include/core_cm4.h ****   }
1751:Drivers/CMSIS/Include/core_cm4.h **** }
1752:Drivers/CMSIS/Include/core_cm4.h **** 
1753:Drivers/CMSIS/Include/core_cm4.h **** 
1754:Drivers/CMSIS/Include/core_cm4.h **** /**
1755:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Set Pending Interrupt
ARM GAS  /tmp/ccfiAGGE.s 			page 39


1756:Drivers/CMSIS/Include/core_cm4.h ****   \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
1757:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]      IRQn  Device specific interrupt number.
1758:Drivers/CMSIS/Include/core_cm4.h ****   \note    IRQn must not be negative.
1759:Drivers/CMSIS/Include/core_cm4.h ****  */
1760:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1761:Drivers/CMSIS/Include/core_cm4.h **** {
1762:Drivers/CMSIS/Include/core_cm4.h ****   if ((int32_t)(IRQn) >= 0)
1763:Drivers/CMSIS/Include/core_cm4.h ****   {
1764:Drivers/CMSIS/Include/core_cm4.h ****     NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1765:Drivers/CMSIS/Include/core_cm4.h ****   }
1766:Drivers/CMSIS/Include/core_cm4.h **** }
1767:Drivers/CMSIS/Include/core_cm4.h **** 
1768:Drivers/CMSIS/Include/core_cm4.h **** 
1769:Drivers/CMSIS/Include/core_cm4.h **** /**
1770:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Clear Pending Interrupt
1771:Drivers/CMSIS/Include/core_cm4.h ****   \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
1772:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]      IRQn  Device specific interrupt number.
1773:Drivers/CMSIS/Include/core_cm4.h ****   \note    IRQn must not be negative.
1774:Drivers/CMSIS/Include/core_cm4.h ****  */
1775:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1776:Drivers/CMSIS/Include/core_cm4.h **** {
1777:Drivers/CMSIS/Include/core_cm4.h ****   if ((int32_t)(IRQn) >= 0)
1778:Drivers/CMSIS/Include/core_cm4.h ****   {
1779:Drivers/CMSIS/Include/core_cm4.h ****     NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1780:Drivers/CMSIS/Include/core_cm4.h ****   }
1781:Drivers/CMSIS/Include/core_cm4.h **** }
1782:Drivers/CMSIS/Include/core_cm4.h **** 
1783:Drivers/CMSIS/Include/core_cm4.h **** 
1784:Drivers/CMSIS/Include/core_cm4.h **** /**
1785:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Get Active Interrupt
1786:Drivers/CMSIS/Include/core_cm4.h ****   \details Reads the active register in the NVIC and returns the active bit for the device specific
1787:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]      IRQn  Device specific interrupt number.
1788:Drivers/CMSIS/Include/core_cm4.h ****   \return             0  Interrupt status is not active.
1789:Drivers/CMSIS/Include/core_cm4.h ****   \return             1  Interrupt status is active.
1790:Drivers/CMSIS/Include/core_cm4.h ****   \note    IRQn must not be negative.
1791:Drivers/CMSIS/Include/core_cm4.h ****  */
1792:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1793:Drivers/CMSIS/Include/core_cm4.h **** {
1794:Drivers/CMSIS/Include/core_cm4.h ****   if ((int32_t)(IRQn) >= 0)
1795:Drivers/CMSIS/Include/core_cm4.h ****   {
1796:Drivers/CMSIS/Include/core_cm4.h ****     return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
1797:Drivers/CMSIS/Include/core_cm4.h ****   }
1798:Drivers/CMSIS/Include/core_cm4.h ****   else
1799:Drivers/CMSIS/Include/core_cm4.h ****   {
1800:Drivers/CMSIS/Include/core_cm4.h ****     return(0U);
1801:Drivers/CMSIS/Include/core_cm4.h ****   }
1802:Drivers/CMSIS/Include/core_cm4.h **** }
1803:Drivers/CMSIS/Include/core_cm4.h **** 
1804:Drivers/CMSIS/Include/core_cm4.h **** 
1805:Drivers/CMSIS/Include/core_cm4.h **** /**
1806:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Set Interrupt Priority
1807:Drivers/CMSIS/Include/core_cm4.h ****   \details Sets the priority of a device specific interrupt or a processor exception.
1808:Drivers/CMSIS/Include/core_cm4.h ****            The interrupt number can be positive to specify a device specific interrupt,
1809:Drivers/CMSIS/Include/core_cm4.h ****            or negative to specify a processor exception.
1810:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]      IRQn  Interrupt number.
1811:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]  priority  Priority to set.
1812:Drivers/CMSIS/Include/core_cm4.h ****   \note    The priority cannot be set for every processor exception.
ARM GAS  /tmp/ccfiAGGE.s 			page 40


1813:Drivers/CMSIS/Include/core_cm4.h ****  */
1814:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1815:Drivers/CMSIS/Include/core_cm4.h **** {
 144              		.loc 2 1815 1 is_stmt 1 view -0
 145              		.cfi_startproc
 146              		@ args = 0, pretend = 0, frame = 0
 147              		@ frame_needed = 0, uses_anonymous_args = 0
 148              		@ link register save eliminated.
1816:Drivers/CMSIS/Include/core_cm4.h ****   if ((int32_t)(IRQn) >= 0)
 149              		.loc 2 1816 3 view .LVU29
 150              		.loc 2 1816 6 is_stmt 0 view .LVU30
 151 0000 0028     		cmp	r0, #0
 152              		.loc 2 1816 6 view .LVU31
 153 0002 08DB     		blt	.L10
1817:Drivers/CMSIS/Include/core_cm4.h ****   {
1818:Drivers/CMSIS/Include/core_cm4.h ****     NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (u
 154              		.loc 2 1818 5 is_stmt 1 view .LVU32
 155              		.loc 2 1818 48 is_stmt 0 view .LVU33
 156 0004 0901     		lsls	r1, r1, #4
 157              	.LVL5:
 158              		.loc 2 1818 48 view .LVU34
 159 0006 C9B2     		uxtb	r1, r1
 160              		.loc 2 1818 46 view .LVU35
 161 0008 00F16040 		add	r0, r0, #-536870912
 162              	.LVL6:
 163              		.loc 2 1818 46 view .LVU36
 164 000c 00F56140 		add	r0, r0, #57600
 165              	.LVL7:
 166              		.loc 2 1818 46 view .LVU37
 167 0010 80F80013 		strb	r1, [r0, #768]
 168 0014 7047     		bx	lr
 169              	.LVL8:
 170              	.L10:
1819:Drivers/CMSIS/Include/core_cm4.h ****   }
1820:Drivers/CMSIS/Include/core_cm4.h ****   else
1821:Drivers/CMSIS/Include/core_cm4.h ****   {
1822:Drivers/CMSIS/Include/core_cm4.h ****     SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (u
 171              		.loc 2 1822 5 is_stmt 1 view .LVU38
 172              		.loc 2 1822 32 is_stmt 0 view .LVU39
 173 0016 00F00F00 		and	r0, r0, #15
 174              	.LVL9:
 175              		.loc 2 1822 48 view .LVU40
 176 001a 0901     		lsls	r1, r1, #4
 177              	.LVL10:
 178              		.loc 2 1822 48 view .LVU41
 179 001c C9B2     		uxtb	r1, r1
 180              		.loc 2 1822 46 view .LVU42
 181 001e 014B     		ldr	r3, .L12
 182 0020 1954     		strb	r1, [r3, r0]
1823:Drivers/CMSIS/Include/core_cm4.h ****   }
1824:Drivers/CMSIS/Include/core_cm4.h **** }
 183              		.loc 2 1824 1 view .LVU43
 184 0022 7047     		bx	lr
 185              	.L13:
 186              		.align	2
 187              	.L12:
 188 0024 14ED00E0 		.word	-536810220
ARM GAS  /tmp/ccfiAGGE.s 			page 41


 189              		.cfi_endproc
 190              	.LFE115:
 192              		.section	.text.__NVIC_GetPriority,"ax",%progbits
 193              		.align	1
 194              		.syntax unified
 195              		.thumb
 196              		.thumb_func
 198              	__NVIC_GetPriority:
 199              	.LVL11:
 200              	.LFB116:
1825:Drivers/CMSIS/Include/core_cm4.h **** 
1826:Drivers/CMSIS/Include/core_cm4.h **** 
1827:Drivers/CMSIS/Include/core_cm4.h **** /**
1828:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Get Interrupt Priority
1829:Drivers/CMSIS/Include/core_cm4.h ****   \details Reads the priority of a device specific interrupt or a processor exception.
1830:Drivers/CMSIS/Include/core_cm4.h ****            The interrupt number can be positive to specify a device specific interrupt,
1831:Drivers/CMSIS/Include/core_cm4.h ****            or negative to specify a processor exception.
1832:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]   IRQn  Interrupt number.
1833:Drivers/CMSIS/Include/core_cm4.h ****   \return             Interrupt Priority.
1834:Drivers/CMSIS/Include/core_cm4.h ****                       Value is aligned automatically to the implemented priority bits of the microc
1835:Drivers/CMSIS/Include/core_cm4.h ****  */
1836:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1837:Drivers/CMSIS/Include/core_cm4.h **** {
 201              		.loc 2 1837 1 is_stmt 1 view -0
 202              		.cfi_startproc
 203              		@ args = 0, pretend = 0, frame = 0
 204              		@ frame_needed = 0, uses_anonymous_args = 0
 205              		@ link register save eliminated.
1838:Drivers/CMSIS/Include/core_cm4.h **** 
1839:Drivers/CMSIS/Include/core_cm4.h ****   if ((int32_t)(IRQn) >= 0)
 206              		.loc 2 1839 3 view .LVU45
 207              		.loc 2 1839 6 is_stmt 0 view .LVU46
 208 0000 0028     		cmp	r0, #0
 209              		.loc 2 1839 6 view .LVU47
 210 0002 07DB     		blt	.L15
1840:Drivers/CMSIS/Include/core_cm4.h ****   {
1841:Drivers/CMSIS/Include/core_cm4.h ****     return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
 211              		.loc 2 1841 5 is_stmt 1 view .LVU48
 212              		.loc 2 1841 31 is_stmt 0 view .LVU49
 213 0004 00F16040 		add	r0, r0, #-536870912
 214              	.LVL12:
 215              		.loc 2 1841 31 view .LVU50
 216 0008 00F56140 		add	r0, r0, #57600
 217              	.LVL13:
 218              		.loc 2 1841 31 view .LVU51
 219 000c 90F80003 		ldrb	r0, [r0, #768]	@ zero_extendqisi2
 220              	.LVL14:
 221              		.loc 2 1841 64 view .LVU52
 222 0010 0009     		lsrs	r0, r0, #4
 223 0012 7047     		bx	lr
 224              	.L15:
1842:Drivers/CMSIS/Include/core_cm4.h ****   }
1843:Drivers/CMSIS/Include/core_cm4.h ****   else
1844:Drivers/CMSIS/Include/core_cm4.h ****   {
1845:Drivers/CMSIS/Include/core_cm4.h ****     return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
 225              		.loc 2 1845 5 is_stmt 1 view .LVU53
 226              		.loc 2 1845 50 is_stmt 0 view .LVU54
ARM GAS  /tmp/ccfiAGGE.s 			page 42


 227 0014 00F00F00 		and	r0, r0, #15
 228              		.loc 2 1845 31 view .LVU55
 229 0018 014B     		ldr	r3, .L17
 230 001a 185C     		ldrb	r0, [r3, r0]	@ zero_extendqisi2
 231              		.loc 2 1845 64 view .LVU56
 232 001c 0009     		lsrs	r0, r0, #4
1846:Drivers/CMSIS/Include/core_cm4.h ****   }
1847:Drivers/CMSIS/Include/core_cm4.h **** }
 233              		.loc 2 1847 1 view .LVU57
 234 001e 7047     		bx	lr
 235              	.L18:
 236              		.align	2
 237              	.L17:
 238 0020 14ED00E0 		.word	-536810220
 239              		.cfi_endproc
 240              	.LFE116:
 242              		.section	.text.NVIC_EncodePriority,"ax",%progbits
 243              		.align	1
 244              		.syntax unified
 245              		.thumb
 246              		.thumb_func
 248              	NVIC_EncodePriority:
 249              	.LVL15:
 250              	.LFB117:
1848:Drivers/CMSIS/Include/core_cm4.h **** 
1849:Drivers/CMSIS/Include/core_cm4.h **** 
1850:Drivers/CMSIS/Include/core_cm4.h **** /**
1851:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Encode Priority
1852:Drivers/CMSIS/Include/core_cm4.h ****   \details Encodes the priority for an interrupt with the given priority group,
1853:Drivers/CMSIS/Include/core_cm4.h ****            preemptive priority value, and subpriority value.
1854:Drivers/CMSIS/Include/core_cm4.h ****            In case of a conflict between priority grouping and available
1855:Drivers/CMSIS/Include/core_cm4.h ****            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1856:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]     PriorityGroup  Used priority group.
1857:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
1858:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]       SubPriority  Subpriority value (starting from 0).
1859:Drivers/CMSIS/Include/core_cm4.h ****   \return                        Encoded priority. Value can be used in the function \ref NVIC_SetP
1860:Drivers/CMSIS/Include/core_cm4.h ****  */
1861:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin
1862:Drivers/CMSIS/Include/core_cm4.h **** {
 251              		.loc 2 1862 1 is_stmt 1 view -0
 252              		.cfi_startproc
 253              		@ args = 0, pretend = 0, frame = 0
 254              		@ frame_needed = 0, uses_anonymous_args = 0
 255              		.loc 2 1862 1 is_stmt 0 view .LVU59
 256 0000 00B5     		push	{lr}
 257              	.LCFI0:
 258              		.cfi_def_cfa_offset 4
 259              		.cfi_offset 14, -4
1863:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used   
 260              		.loc 2 1863 3 is_stmt 1 view .LVU60
 261              		.loc 2 1863 12 is_stmt 0 view .LVU61
 262 0002 00F00700 		and	r0, r0, #7
 263              	.LVL16:
1864:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t PreemptPriorityBits;
 264              		.loc 2 1864 3 is_stmt 1 view .LVU62
1865:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t SubPriorityBits;
 265              		.loc 2 1865 3 view .LVU63
ARM GAS  /tmp/ccfiAGGE.s 			page 43


1866:Drivers/CMSIS/Include/core_cm4.h **** 
1867:Drivers/CMSIS/Include/core_cm4.h ****   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
 266              		.loc 2 1867 3 view .LVU64
 267              		.loc 2 1867 31 is_stmt 0 view .LVU65
 268 0006 C0F1070C 		rsb	ip, r0, #7
 269              		.loc 2 1867 23 view .LVU66
 270 000a BCF1040F 		cmp	ip, #4
 271 000e 28BF     		it	cs
 272 0010 4FF0040C 		movcs	ip, #4
 273              	.LVL17:
1868:Drivers/CMSIS/Include/core_cm4.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
 274              		.loc 2 1868 3 is_stmt 1 view .LVU67
 275              		.loc 2 1868 44 is_stmt 0 view .LVU68
 276 0014 031D     		adds	r3, r0, #4
 277              		.loc 2 1868 109 view .LVU69
 278 0016 062B     		cmp	r3, #6
 279 0018 0FD9     		bls	.L21
 280              		.loc 2 1868 109 discriminator 1 view .LVU70
 281 001a C31E     		subs	r3, r0, #3
 282              	.L20:
 283              	.LVL18:
1869:Drivers/CMSIS/Include/core_cm4.h **** 
1870:Drivers/CMSIS/Include/core_cm4.h ****   return (
 284              		.loc 2 1870 3 is_stmt 1 view .LVU71
1871:Drivers/CMSIS/Include/core_cm4.h ****            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
 285              		.loc 2 1871 30 is_stmt 0 view .LVU72
 286 001c 4FF0FF3E 		mov	lr, #-1
 287 0020 0EFA0CF0 		lsl	r0, lr, ip
 288              	.LVL19:
 289              		.loc 2 1871 30 view .LVU73
 290 0024 21EA0001 		bic	r1, r1, r0
 291              	.LVL20:
 292              		.loc 2 1871 82 view .LVU74
 293 0028 9940     		lsls	r1, r1, r3
1872:Drivers/CMSIS/Include/core_cm4.h ****            ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 294              		.loc 2 1872 30 view .LVU75
 295 002a 0EFA03FE 		lsl	lr, lr, r3
 296 002e 22EA0E02 		bic	r2, r2, lr
 297              	.LVL21:
1873:Drivers/CMSIS/Include/core_cm4.h ****          );
1874:Drivers/CMSIS/Include/core_cm4.h **** }
 298              		.loc 2 1874 1 view .LVU76
 299 0032 41EA0200 		orr	r0, r1, r2
 300 0036 5DF804FB 		ldr	pc, [sp], #4
 301              	.LVL22:
 302              	.L21:
1868:Drivers/CMSIS/Include/core_cm4.h **** 
 303              		.loc 2 1868 109 discriminator 2 view .LVU77
 304 003a 0023     		movs	r3, #0
 305 003c EEE7     		b	.L20
 306              		.cfi_endproc
 307              	.LFE117:
 309              		.section	.text.NVIC_DecodePriority,"ax",%progbits
 310              		.align	1
 311              		.syntax unified
 312              		.thumb
 313              		.thumb_func
ARM GAS  /tmp/ccfiAGGE.s 			page 44


 315              	NVIC_DecodePriority:
 316              	.LVL23:
 317              	.LFB118:
1875:Drivers/CMSIS/Include/core_cm4.h **** 
1876:Drivers/CMSIS/Include/core_cm4.h **** 
1877:Drivers/CMSIS/Include/core_cm4.h **** /**
1878:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Decode Priority
1879:Drivers/CMSIS/Include/core_cm4.h ****   \details Decodes an interrupt priority value with a given priority group to
1880:Drivers/CMSIS/Include/core_cm4.h ****            preemptive priority value and subpriority value.
1881:Drivers/CMSIS/Include/core_cm4.h ****            In case of a conflict between priority grouping and available
1882:Drivers/CMSIS/Include/core_cm4.h ****            priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1883:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC
1884:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]     PriorityGroup  Used priority group.
1885:Drivers/CMSIS/Include/core_cm4.h ****   \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
1886:Drivers/CMSIS/Include/core_cm4.h ****   \param [out]     pSubPriority  Subpriority value (starting from 0).
1887:Drivers/CMSIS/Include/core_cm4.h ****  */
1888:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* cons
1889:Drivers/CMSIS/Include/core_cm4.h **** {
 318              		.loc 2 1889 1 is_stmt 1 view -0
 319              		.cfi_startproc
 320              		@ args = 0, pretend = 0, frame = 0
 321              		@ frame_needed = 0, uses_anonymous_args = 0
 322              		.loc 2 1889 1 is_stmt 0 view .LVU79
 323 0000 10B5     		push	{r4, lr}
 324              	.LCFI1:
 325              		.cfi_def_cfa_offset 8
 326              		.cfi_offset 4, -8
 327              		.cfi_offset 14, -4
1890:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used   
 328              		.loc 2 1890 3 is_stmt 1 view .LVU80
 329              		.loc 2 1890 12 is_stmt 0 view .LVU81
 330 0002 01F00701 		and	r1, r1, #7
 331              	.LVL24:
1891:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t PreemptPriorityBits;
 332              		.loc 2 1891 3 is_stmt 1 view .LVU82
1892:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t SubPriorityBits;
 333              		.loc 2 1892 3 view .LVU83
1893:Drivers/CMSIS/Include/core_cm4.h **** 
1894:Drivers/CMSIS/Include/core_cm4.h ****   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
 334              		.loc 2 1894 3 view .LVU84
 335              		.loc 2 1894 31 is_stmt 0 view .LVU85
 336 0006 C1F1070C 		rsb	ip, r1, #7
 337              		.loc 2 1894 23 view .LVU86
 338 000a BCF1040F 		cmp	ip, #4
 339 000e 28BF     		it	cs
 340 0010 4FF0040C 		movcs	ip, #4
 341              	.LVL25:
1895:Drivers/CMSIS/Include/core_cm4.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
 342              		.loc 2 1895 3 is_stmt 1 view .LVU87
 343              		.loc 2 1895 44 is_stmt 0 view .LVU88
 344 0014 0C1D     		adds	r4, r1, #4
 345              		.loc 2 1895 109 view .LVU89
 346 0016 062C     		cmp	r4, #6
 347 0018 0FD9     		bls	.L25
 348              		.loc 2 1895 109 discriminator 1 view .LVU90
 349 001a 0339     		subs	r1, r1, #3
 350              	.LVL26:
ARM GAS  /tmp/ccfiAGGE.s 			page 45


 351              	.L24:
1896:Drivers/CMSIS/Include/core_cm4.h **** 
1897:Drivers/CMSIS/Include/core_cm4.h ****   *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1
 352              		.loc 2 1897 3 is_stmt 1 view .LVU91
 353              		.loc 2 1897 33 is_stmt 0 view .LVU92
 354 001c 20FA01F4 		lsr	r4, r0, r1
 355              	.LVL27:
 356              		.loc 2 1897 53 view .LVU93
 357 0020 4FF0FF3E 		mov	lr, #-1
 358 0024 0EFA0CFC 		lsl	ip, lr, ip
 359              	.LVL28:
 360              		.loc 2 1897 53 view .LVU94
 361 0028 24EA0C04 		bic	r4, r4, ip
 362              		.loc 2 1897 21 view .LVU95
 363 002c 1460     		str	r4, [r2]
1898:Drivers/CMSIS/Include/core_cm4.h ****   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1
 364              		.loc 2 1898 3 is_stmt 1 view .LVU96
 365              		.loc 2 1898 53 is_stmt 0 view .LVU97
 366 002e 0EFA01FE 		lsl	lr, lr, r1
 367 0032 20EA0E00 		bic	r0, r0, lr
 368              	.LVL29:
 369              		.loc 2 1898 21 view .LVU98
 370 0036 1860     		str	r0, [r3]
1899:Drivers/CMSIS/Include/core_cm4.h **** }
 371              		.loc 2 1899 1 view .LVU99
 372 0038 10BD     		pop	{r4, pc}
 373              	.LVL30:
 374              	.L25:
1895:Drivers/CMSIS/Include/core_cm4.h **** 
 375              		.loc 2 1895 109 discriminator 2 view .LVU100
 376 003a 0021     		movs	r1, #0
 377              	.LVL31:
1895:Drivers/CMSIS/Include/core_cm4.h **** 
 378              		.loc 2 1895 109 discriminator 2 view .LVU101
 379 003c EEE7     		b	.L24
 380              		.cfi_endproc
 381              	.LFE118:
 383              		.section	.text.__NVIC_SystemReset,"ax",%progbits
 384              		.align	1
 385              		.syntax unified
 386              		.thumb
 387              		.thumb_func
 389              	__NVIC_SystemReset:
 390              	.LFB121:
1900:Drivers/CMSIS/Include/core_cm4.h **** 
1901:Drivers/CMSIS/Include/core_cm4.h **** 
1902:Drivers/CMSIS/Include/core_cm4.h **** /**
1903:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Set Interrupt Vector
1904:Drivers/CMSIS/Include/core_cm4.h ****   \details Sets an interrupt vector in SRAM based interrupt vector table.
1905:Drivers/CMSIS/Include/core_cm4.h ****            The interrupt number can be positive to specify a device specific interrupt,
1906:Drivers/CMSIS/Include/core_cm4.h ****            or negative to specify a processor exception.
1907:Drivers/CMSIS/Include/core_cm4.h ****            VTOR must been relocated to SRAM before.
1908:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]   IRQn      Interrupt number
1909:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]   vector    Address of interrupt handler function
1910:Drivers/CMSIS/Include/core_cm4.h ****  */
1911:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1912:Drivers/CMSIS/Include/core_cm4.h **** {
ARM GAS  /tmp/ccfiAGGE.s 			page 46


1913:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t *vectors = (uint32_t *)SCB->VTOR;
1914:Drivers/CMSIS/Include/core_cm4.h ****   vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1915:Drivers/CMSIS/Include/core_cm4.h ****   /* ARM Application Note 321 states that the M4 does not require the architectural barrier */
1916:Drivers/CMSIS/Include/core_cm4.h **** }
1917:Drivers/CMSIS/Include/core_cm4.h **** 
1918:Drivers/CMSIS/Include/core_cm4.h **** 
1919:Drivers/CMSIS/Include/core_cm4.h **** /**
1920:Drivers/CMSIS/Include/core_cm4.h ****   \brief   Get Interrupt Vector
1921:Drivers/CMSIS/Include/core_cm4.h ****   \details Reads an interrupt vector from interrupt vector table.
1922:Drivers/CMSIS/Include/core_cm4.h ****            The interrupt number can be positive to specify a device specific interrupt,
1923:Drivers/CMSIS/Include/core_cm4.h ****            or negative to specify a processor exception.
1924:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]   IRQn      Interrupt number.
1925:Drivers/CMSIS/Include/core_cm4.h ****   \return                 Address of interrupt handler function
1926:Drivers/CMSIS/Include/core_cm4.h ****  */
1927:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1928:Drivers/CMSIS/Include/core_cm4.h **** {
1929:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t *vectors = (uint32_t *)SCB->VTOR;
1930:Drivers/CMSIS/Include/core_cm4.h ****   return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1931:Drivers/CMSIS/Include/core_cm4.h **** }
1932:Drivers/CMSIS/Include/core_cm4.h **** 
1933:Drivers/CMSIS/Include/core_cm4.h **** 
1934:Drivers/CMSIS/Include/core_cm4.h **** /**
1935:Drivers/CMSIS/Include/core_cm4.h ****   \brief   System Reset
1936:Drivers/CMSIS/Include/core_cm4.h ****   \details Initiates a system reset request to reset the MCU.
1937:Drivers/CMSIS/Include/core_cm4.h ****  */
1938:Drivers/CMSIS/Include/core_cm4.h **** __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
1939:Drivers/CMSIS/Include/core_cm4.h **** {
 391              		.loc 2 1939 1 is_stmt 1 view -0
 392              		.cfi_startproc
 393              		@ Volatile: function does not return.
 394              		@ args = 0, pretend = 0, frame = 0
 395              		@ frame_needed = 0, uses_anonymous_args = 0
 396              		@ link register save eliminated.
1940:Drivers/CMSIS/Include/core_cm4.h ****   __DSB();                                                          /* Ensure all outstanding memor
 397              		.loc 2 1940 3 view .LVU103
 398              	.LBB40:
 399              	.LBI40:
 269:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 400              		.loc 3 269 27 view .LVU104
 401              	.LBB41:
 402              		.loc 3 271 3 view .LVU105
 403              		.syntax unified
 404              	@ 271 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 405 0000 BFF34F8F 		dsb 0xF
 406              	@ 0 "" 2
 407              		.thumb
 408              		.syntax unified
 409              	.LBE41:
 410              	.LBE40:
1941:Drivers/CMSIS/Include/core_cm4.h ****                                                                        buffered write are completed
1942:Drivers/CMSIS/Include/core_cm4.h ****   SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
 411              		.loc 2 1942 3 view .LVU106
1943:Drivers/CMSIS/Include/core_cm4.h ****                            (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
 412              		.loc 2 1943 32 is_stmt 0 view .LVU107
 413 0004 0549     		ldr	r1, .L29
 414 0006 CA68     		ldr	r2, [r1, #12]
 415              		.loc 2 1943 40 view .LVU108
ARM GAS  /tmp/ccfiAGGE.s 			page 47


 416 0008 02F4E062 		and	r2, r2, #1792
1942:Drivers/CMSIS/Include/core_cm4.h ****                            (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
 417              		.loc 2 1942 17 view .LVU109
 418 000c 044B     		ldr	r3, .L29+4
 419 000e 1343     		orrs	r3, r3, r2
1942:Drivers/CMSIS/Include/core_cm4.h ****                            (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
 420              		.loc 2 1942 15 view .LVU110
 421 0010 CB60     		str	r3, [r1, #12]
1944:Drivers/CMSIS/Include/core_cm4.h ****                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchange
1945:Drivers/CMSIS/Include/core_cm4.h ****   __DSB();                                                          /* Ensure completion of memory 
 422              		.loc 2 1945 3 is_stmt 1 view .LVU111
 423              	.LBB42:
 424              	.LBI42:
 269:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 425              		.loc 3 269 27 view .LVU112
 426              	.LBB43:
 427              		.loc 3 271 3 view .LVU113
 428              		.syntax unified
 429              	@ 271 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 430 0012 BFF34F8F 		dsb 0xF
 431              	@ 0 "" 2
 432              		.thumb
 433              		.syntax unified
 434              	.L28:
 435              	.LBE43:
 436              	.LBE42:
1946:Drivers/CMSIS/Include/core_cm4.h **** 
1947:Drivers/CMSIS/Include/core_cm4.h ****   for(;;)                                                           /* wait until reset */
 437              		.loc 2 1947 3 view .LVU114
1948:Drivers/CMSIS/Include/core_cm4.h ****   {
1949:Drivers/CMSIS/Include/core_cm4.h ****     __NOP();
 438              		.loc 2 1949 5 discriminator 1 view .LVU115
 439              		.syntax unified
 440              	@ 1949 "Drivers/CMSIS/Include/core_cm4.h" 1
 441 0016 00BF     		nop
 442              	@ 0 "" 2
1947:Drivers/CMSIS/Include/core_cm4.h ****   {
 443              		.loc 2 1947 3 view .LVU116
 444              		.thumb
 445              		.syntax unified
 446 0018 FDE7     		b	.L28
 447              	.L30:
 448 001a 00BF     		.align	2
 449              	.L29:
 450 001c 00ED00E0 		.word	-536810240
 451 0020 0400FA05 		.word	100270084
 452              		.cfi_endproc
 453              	.LFE121:
 455              		.section	.text.HAL_NVIC_SetPriorityGrouping,"ax",%progbits
 456              		.align	1
 457              		.global	HAL_NVIC_SetPriorityGrouping
 458              		.syntax unified
 459              		.thumb
 460              		.thumb_func
 462              	HAL_NVIC_SetPriorityGrouping:
 463              	.LVL32:
 464              	.LFB239:
ARM GAS  /tmp/ccfiAGGE.s 			page 48


   1:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
   2:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   ******************************************************************************
   3:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @file    stm32f4xx_hal_cortex.c
   4:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @author  MCD Application Team
   5:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief   CORTEX HAL module driver.
   6:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *          This file provides firmware functions to manage the following 
   7:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *          functionalities of the CORTEX:
   8:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *           + Initialization and de-initialization functions
   9:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *           + Peripheral Control functions 
  10:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *
  11:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   @verbatim  
  12:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   ==============================================================================
  13:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****                         ##### How to use this driver #####
  14:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   ==============================================================================
  15:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
  16:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****     [..]  
  17:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****     *** How to configure Interrupts using CORTEX HAL driver ***
  18:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****     ===========================================================
  19:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****     [..]     
  20:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****     This section provides functions allowing to configure the NVIC interrupts (IRQ).
  21:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****     The Cortex-M4 exceptions are managed by CMSIS functions.
  22:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****    
  23:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****     (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
  24:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****         function according to the following table.
  25:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****     (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). 
  26:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****     (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
  27:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****     (#) please refer to programming manual for details in how to configure priority. 
  28:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****       
  29:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****      -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. 
  30:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****          The pending IRQ priority will be managed only by the sub priority.
  31:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****    
  32:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****      -@- IRQ priority order (sorted by highest to lowest priority):
  33:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****         (+@) Lowest preemption priority
  34:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****         (+@) Lowest sub priority
  35:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****         (+@) Lowest hardware priority (IRQ number)
  36:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****  
  37:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****     [..]  
  38:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****     *** How to configure Systick using CORTEX HAL driver ***
  39:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****     ========================================================
  40:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****     [..]
  41:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****     Setup SysTick Timer for time base.
  42:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****            
  43:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****    (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
  44:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****        is a CMSIS function that:
  45:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****         (++) Configures the SysTick Reload register with value passed as function parameter.
  46:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****         (++) Configures the SysTick IRQ priority to the lowest value 0x0F.
  47:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****         (++) Resets the SysTick Counter register.
  48:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****         (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
  49:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****         (++) Enables the SysTick Interrupt.
  50:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****         (++) Starts the SysTick Counter.
  51:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****     
  52:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****    (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
  53:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****        __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
  54:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****        HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
  55:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****        inside the stm32f4xx_hal_cortex.h file.
  56:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
  57:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****    (+) You can change the SysTick IRQ priority by calling the
ARM GAS  /tmp/ccfiAGGE.s 			page 49


  58:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****        HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
  59:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****        call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS funct
  60:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
  61:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****    (+) To adjust the SysTick time base, use the following formula:
  62:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****                             
  63:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****        Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
  64:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****        (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
  65:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****        (++) Reload Value should not exceed 0xFFFFFF
  66:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****    
  67:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   @endverbatim
  68:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   ******************************************************************************
  69:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @attention
  70:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *
  71:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * Copyright (c) 2017 STMicroelectronics.
  72:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * All rights reserved.
  73:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *
  74:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * This software is licensed under terms that can be found in the LICENSE file in
  75:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * the root directory of this software component.
  76:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
  77:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   ******************************************************************************
  78:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
  79:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
  80:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Includes ------------------------------------------------------------------*/
  81:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** #include "stm32f4xx_hal.h"
  82:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
  83:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** @addtogroup STM32F4xx_HAL_Driver
  84:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @{
  85:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
  86:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
  87:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** @defgroup CORTEX CORTEX
  88:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief CORTEX HAL module driver
  89:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @{
  90:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
  91:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
  92:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** #ifdef HAL_CORTEX_MODULE_ENABLED
  93:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
  94:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Private types -------------------------------------------------------------*/
  95:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Private variables ---------------------------------------------------------*/
  96:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Private constants ---------------------------------------------------------*/
  97:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Private macros ------------------------------------------------------------*/
  98:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Private functions ---------------------------------------------------------*/
  99:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Exported functions --------------------------------------------------------*/
 100:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 101:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
 102:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @{
 103:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 104:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 105:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 106:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
 107:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****  *  @brief    Initialization and Configuration functions 
 108:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****  *
 109:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** @verbatim    
 110:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   ==============================================================================
 111:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****               ##### Initialization and de-initialization functions #####
 112:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   ==============================================================================
 113:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****     [..]
 114:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****       This section provides the CORTEX HAL driver functions allowing to configure Interrupts
ARM GAS  /tmp/ccfiAGGE.s 			page 50


 115:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****       Systick functionalities 
 116:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 117:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** @endverbatim
 118:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @{
 119:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 120:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 121:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 122:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
 123:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief  Sets the priority grouping field (preemption priority and subpriority)
 124:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         using the required unlock sequence.
 125:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @param  PriorityGroup The priority grouping bits length. 
 126:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         This parameter can be one of the following values:
 127:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
 128:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *                                    4 bits for subpriority
 129:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
 130:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *                                    3 bits for subpriority
 131:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
 132:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *                                    2 bits for subpriority
 133:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
 134:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *                                    1 bits for subpriority
 135:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
 136:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *                                    0 bits for subpriority
 137:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. 
 138:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         The pending IRQ priority will be managed only by the subpriority. 
 139:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @retval None
 140:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 141:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 142:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** {
 465              		.loc 1 142 1 view -0
 466              		.cfi_startproc
 467              		@ args = 0, pretend = 0, frame = 0
 468              		@ frame_needed = 0, uses_anonymous_args = 0
 469              		@ link register save eliminated.
 143:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Check the parameters */
 144:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
 470              		.loc 1 144 3 view .LVU118
 145:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   
 146:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
 147:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   NVIC_SetPriorityGrouping(PriorityGroup);
 471              		.loc 1 147 3 view .LVU119
 472              	.LBB44:
 473              	.LBI44:
1653:Drivers/CMSIS/Include/core_cm4.h **** {
 474              		.loc 2 1653 22 view .LVU120
 475              	.LBB45:
1655:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 a
 476              		.loc 2 1655 3 view .LVU121
1656:Drivers/CMSIS/Include/core_cm4.h **** 
 477              		.loc 2 1656 3 view .LVU122
1658:Drivers/CMSIS/Include/core_cm4.h ****   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan
 478              		.loc 2 1658 3 view .LVU123
1658:Drivers/CMSIS/Include/core_cm4.h ****   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan
 479              		.loc 2 1658 14 is_stmt 0 view .LVU124
 480 0000 074A     		ldr	r2, .L32
 481 0002 D368     		ldr	r3, [r2, #12]
 482              	.LVL33:
1659:Drivers/CMSIS/Include/core_cm4.h ****   reg_value  =  (reg_value                                   |
ARM GAS  /tmp/ccfiAGGE.s 			page 51


 483              		.loc 2 1659 3 is_stmt 1 view .LVU125
1659:Drivers/CMSIS/Include/core_cm4.h ****   reg_value  =  (reg_value                                   |
 484              		.loc 2 1659 13 is_stmt 0 view .LVU126
 485 0004 23F4E063 		bic	r3, r3, #1792
 486              	.LVL34:
1659:Drivers/CMSIS/Include/core_cm4.h ****   reg_value  =  (reg_value                                   |
 487              		.loc 2 1659 13 view .LVU127
 488 0008 1B04     		lsls	r3, r3, #16
 489 000a 1B0C     		lsrs	r3, r3, #16
 490              	.LVL35:
1660:Drivers/CMSIS/Include/core_cm4.h ****                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 491              		.loc 2 1660 3 is_stmt 1 view .LVU128
1662:Drivers/CMSIS/Include/core_cm4.h ****   SCB->AIRCR =  reg_value;
 492              		.loc 2 1662 35 is_stmt 0 view .LVU129
 493 000c 0002     		lsls	r0, r0, #8
 494              	.LVL36:
1662:Drivers/CMSIS/Include/core_cm4.h ****   SCB->AIRCR =  reg_value;
 495              		.loc 2 1662 35 view .LVU130
 496 000e 00F4E060 		and	r0, r0, #1792
1661:Drivers/CMSIS/Include/core_cm4.h ****                 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key a
 497              		.loc 2 1661 62 view .LVU131
 498 0012 0343     		orrs	r3, r3, r0
 499              	.LVL37:
1660:Drivers/CMSIS/Include/core_cm4.h ****                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 500              		.loc 2 1660 14 view .LVU132
 501 0014 43F0BF63 		orr	r3, r3, #100139008
 502 0018 43F40033 		orr	r3, r3, #131072
 503              	.LVL38:
1663:Drivers/CMSIS/Include/core_cm4.h **** }
 504              		.loc 2 1663 3 is_stmt 1 view .LVU133
1663:Drivers/CMSIS/Include/core_cm4.h **** }
 505              		.loc 2 1663 14 is_stmt 0 view .LVU134
 506 001c D360     		str	r3, [r2, #12]
 507              	.LVL39:
1663:Drivers/CMSIS/Include/core_cm4.h **** }
 508              		.loc 2 1663 14 view .LVU135
 509              	.LBE45:
 510              	.LBE44:
 148:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** }
 511              		.loc 1 148 1 view .LVU136
 512 001e 7047     		bx	lr
 513              	.L33:
 514              		.align	2
 515              	.L32:
 516 0020 00ED00E0 		.word	-536810240
 517              		.cfi_endproc
 518              	.LFE239:
 520              		.section	.text.HAL_NVIC_SetPriority,"ax",%progbits
 521              		.align	1
 522              		.global	HAL_NVIC_SetPriority
 523              		.syntax unified
 524              		.thumb
 525              		.thumb_func
 527              	HAL_NVIC_SetPriority:
 528              	.LVL40:
 529              	.LFB240:
 149:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
ARM GAS  /tmp/ccfiAGGE.s 			page 52


 150:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
 151:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief  Sets the priority of an interrupt.
 152:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
 153:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
 154:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
 155:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @param  PreemptPriority The preemption priority for the IRQn channel.
 156:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         This parameter can be a value between 0 and 15
 157:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         A lower priority value indicates a higher priority 
 158:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @param  SubPriority the subpriority level for the IRQ channel.
 159:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         This parameter can be a value between 0 and 15
 160:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         A lower priority value indicates a higher priority.          
 161:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @retval None
 162:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 163:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
 164:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 
 530              		.loc 1 164 1 is_stmt 1 view -0
 531              		.cfi_startproc
 532              		@ args = 0, pretend = 0, frame = 0
 533              		@ frame_needed = 0, uses_anonymous_args = 0
 534              		.loc 1 164 1 is_stmt 0 view .LVU138
 535 0000 10B5     		push	{r4, lr}
 536              	.LCFI2:
 537              		.cfi_def_cfa_offset 8
 538              		.cfi_offset 4, -8
 539              		.cfi_offset 14, -4
 540 0002 0446     		mov	r4, r0
 165:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   uint32_t prioritygroup = 0x00U;
 541              		.loc 1 165 3 is_stmt 1 view .LVU139
 542              	.LVL41:
 166:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   
 167:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Check the parameters */
 168:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
 543              		.loc 1 168 3 view .LVU140
 169:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
 544              		.loc 1 169 3 view .LVU141
 170:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   
 171:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   prioritygroup = NVIC_GetPriorityGrouping();
 545              		.loc 1 171 3 view .LVU142
 546              	.LBB46:
 547              	.LBI46:
1672:Drivers/CMSIS/Include/core_cm4.h **** {
 548              		.loc 2 1672 26 view .LVU143
 549              	.LBB47:
1674:Drivers/CMSIS/Include/core_cm4.h **** }
 550              		.loc 2 1674 3 view .LVU144
1674:Drivers/CMSIS/Include/core_cm4.h **** }
 551              		.loc 2 1674 26 is_stmt 0 view .LVU145
 552 0004 054B     		ldr	r3, .L36
 553 0006 D868     		ldr	r0, [r3, #12]
 554              	.LVL42:
1674:Drivers/CMSIS/Include/core_cm4.h **** }
 555              		.loc 2 1674 26 view .LVU146
 556              	.LBE47:
 557              	.LBE46:
 172:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   
 173:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
 558              		.loc 1 173 3 is_stmt 1 view .LVU147
ARM GAS  /tmp/ccfiAGGE.s 			page 53


 559 0008 C0F30220 		ubfx	r0, r0, #8, #3
 560              	.LVL43:
 561              		.loc 1 173 3 is_stmt 0 view .LVU148
 562 000c FFF7FEFF 		bl	NVIC_EncodePriority
 563              	.LVL44:
 564              		.loc 1 173 3 view .LVU149
 565 0010 0146     		mov	r1, r0
 566              		.loc 1 173 3 discriminator 1 view .LVU150
 567 0012 2046     		mov	r0, r4
 568 0014 FFF7FEFF 		bl	__NVIC_SetPriority
 569              	.LVL45:
 174:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** }
 570              		.loc 1 174 1 view .LVU151
 571 0018 10BD     		pop	{r4, pc}
 572              	.LVL46:
 573              	.L37:
 574              		.loc 1 174 1 view .LVU152
 575 001a 00BF     		.align	2
 576              	.L36:
 577 001c 00ED00E0 		.word	-536810240
 578              		.cfi_endproc
 579              	.LFE240:
 581              		.section	.text.HAL_NVIC_EnableIRQ,"ax",%progbits
 582              		.align	1
 583              		.global	HAL_NVIC_EnableIRQ
 584              		.syntax unified
 585              		.thumb
 586              		.thumb_func
 588              	HAL_NVIC_EnableIRQ:
 589              	.LVL47:
 590              	.LFB241:
 175:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 176:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
 177:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
 178:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
 179:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         function should be called before. 
 180:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
 181:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
 182:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
 183:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @retval None
 184:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 185:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
 186:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** {
 591              		.loc 1 186 1 is_stmt 1 view -0
 592              		.cfi_startproc
 593              		@ args = 0, pretend = 0, frame = 0
 594              		@ frame_needed = 0, uses_anonymous_args = 0
 595              		.loc 1 186 1 is_stmt 0 view .LVU154
 596 0000 08B5     		push	{r3, lr}
 597              	.LCFI3:
 598              		.cfi_def_cfa_offset 8
 599              		.cfi_offset 3, -8
 600              		.cfi_offset 14, -4
 187:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Check the parameters */
 188:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 601              		.loc 1 188 3 is_stmt 1 view .LVU155
 189:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   
ARM GAS  /tmp/ccfiAGGE.s 			page 54


 190:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Enable interrupt */
 191:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   NVIC_EnableIRQ(IRQn);
 602              		.loc 1 191 3 view .LVU156
 603 0002 FFF7FEFF 		bl	__NVIC_EnableIRQ
 604              	.LVL48:
 192:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** }
 605              		.loc 1 192 1 is_stmt 0 view .LVU157
 606 0006 08BD     		pop	{r3, pc}
 607              		.cfi_endproc
 608              	.LFE241:
 610              		.section	.text.HAL_NVIC_DisableIRQ,"ax",%progbits
 611              		.align	1
 612              		.global	HAL_NVIC_DisableIRQ
 613              		.syntax unified
 614              		.thumb
 615              		.thumb_func
 617              	HAL_NVIC_DisableIRQ:
 618              	.LVL49:
 619              	.LFB242:
 193:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 194:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
 195:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
 196:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
 197:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
 198:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
 199:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @retval None
 200:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 201:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
 202:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** {
 620              		.loc 1 202 1 is_stmt 1 view -0
 621              		.cfi_startproc
 622              		@ args = 0, pretend = 0, frame = 0
 623              		@ frame_needed = 0, uses_anonymous_args = 0
 624              		.loc 1 202 1 is_stmt 0 view .LVU159
 625 0000 08B5     		push	{r3, lr}
 626              	.LCFI4:
 627              		.cfi_def_cfa_offset 8
 628              		.cfi_offset 3, -8
 629              		.cfi_offset 14, -4
 203:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Check the parameters */
 204:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 630              		.loc 1 204 3 is_stmt 1 view .LVU160
 205:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   
 206:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Disable interrupt */
 207:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   NVIC_DisableIRQ(IRQn);
 631              		.loc 1 207 3 view .LVU161
 632 0002 FFF7FEFF 		bl	__NVIC_DisableIRQ
 633              	.LVL50:
 208:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** }
 634              		.loc 1 208 1 is_stmt 0 view .LVU162
 635 0006 08BD     		pop	{r3, pc}
 636              		.cfi_endproc
 637              	.LFE242:
 639              		.section	.text.HAL_NVIC_SystemReset,"ax",%progbits
 640              		.align	1
 641              		.global	HAL_NVIC_SystemReset
 642              		.syntax unified
ARM GAS  /tmp/ccfiAGGE.s 			page 55


 643              		.thumb
 644              		.thumb_func
 646              	HAL_NVIC_SystemReset:
 647              	.LFB243:
 209:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 210:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
 211:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief  Initiates a system reset request to reset the MCU.
 212:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @retval None
 213:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 214:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_NVIC_SystemReset(void)
 215:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** {
 648              		.loc 1 215 1 is_stmt 1 view -0
 649              		.cfi_startproc
 650              		@ Volatile: function does not return.
 651              		@ args = 0, pretend = 0, frame = 0
 652              		@ frame_needed = 0, uses_anonymous_args = 0
 653 0000 08B5     		push	{r3, lr}
 654              	.LCFI5:
 655              		.cfi_def_cfa_offset 8
 656              		.cfi_offset 3, -8
 657              		.cfi_offset 14, -4
 216:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* System Reset */
 217:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   NVIC_SystemReset();
 658              		.loc 1 217 3 view .LVU164
 659 0002 FFF7FEFF 		bl	__NVIC_SystemReset
 660              	.LVL51:
 661              		.cfi_endproc
 662              	.LFE243:
 664              		.section	.text.HAL_SYSTICK_Config,"ax",%progbits
 665              		.align	1
 666              		.global	HAL_SYSTICK_Config
 667              		.syntax unified
 668              		.thumb
 669              		.thumb_func
 671              	HAL_SYSTICK_Config:
 672              	.LVL52:
 673              	.LFB244:
 218:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** }
 219:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 220:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
 221:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
 222:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         Counter is in free running mode to generate periodic interrupts.
 223:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
 224:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @retval status:  - 0  Function succeeded.
 225:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *                  - 1  Function failed.
 226:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 227:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
 228:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** {
 674              		.loc 1 228 1 view -0
 675              		.cfi_startproc
 676              		@ args = 0, pretend = 0, frame = 0
 677              		@ frame_needed = 0, uses_anonymous_args = 0
 678              		@ link register save eliminated.
 229:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****    return SysTick_Config(TicksNumb);
 679              		.loc 1 229 4 view .LVU166
 680              	.LBB48:
 681              	.LBI48:
ARM GAS  /tmp/ccfiAGGE.s 			page 56


1950:Drivers/CMSIS/Include/core_cm4.h ****   }
1951:Drivers/CMSIS/Include/core_cm4.h **** }
1952:Drivers/CMSIS/Include/core_cm4.h **** 
1953:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of CMSIS_Core_NVICFunctions */
1954:Drivers/CMSIS/Include/core_cm4.h **** 
1955:Drivers/CMSIS/Include/core_cm4.h **** 
1956:Drivers/CMSIS/Include/core_cm4.h **** /* ##########################  MPU functions  #################################### */
1957:Drivers/CMSIS/Include/core_cm4.h **** 
1958:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1959:Drivers/CMSIS/Include/core_cm4.h **** 
1960:Drivers/CMSIS/Include/core_cm4.h **** #include "mpu_armv7.h"
1961:Drivers/CMSIS/Include/core_cm4.h **** 
1962:Drivers/CMSIS/Include/core_cm4.h **** #endif
1963:Drivers/CMSIS/Include/core_cm4.h **** 
1964:Drivers/CMSIS/Include/core_cm4.h **** 
1965:Drivers/CMSIS/Include/core_cm4.h **** /* ##########################  FPU functions  #################################### */
1966:Drivers/CMSIS/Include/core_cm4.h **** /**
1967:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_Core_FunctionInterface
1968:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_Core_FpuFunctions FPU Functions
1969:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Function that provides FPU type.
1970:Drivers/CMSIS/Include/core_cm4.h ****   @{
1971:Drivers/CMSIS/Include/core_cm4.h ****  */
1972:Drivers/CMSIS/Include/core_cm4.h **** 
1973:Drivers/CMSIS/Include/core_cm4.h **** /**
1974:Drivers/CMSIS/Include/core_cm4.h ****   \brief   get FPU type
1975:Drivers/CMSIS/Include/core_cm4.h ****   \details returns the FPU type
1976:Drivers/CMSIS/Include/core_cm4.h ****   \returns
1977:Drivers/CMSIS/Include/core_cm4.h ****    - \b  0: No FPU
1978:Drivers/CMSIS/Include/core_cm4.h ****    - \b  1: Single precision FPU
1979:Drivers/CMSIS/Include/core_cm4.h ****    - \b  2: Double + Single precision FPU
1980:Drivers/CMSIS/Include/core_cm4.h ****  */
1981:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t SCB_GetFPUType(void)
1982:Drivers/CMSIS/Include/core_cm4.h **** {
1983:Drivers/CMSIS/Include/core_cm4.h ****   uint32_t mvfr0;
1984:Drivers/CMSIS/Include/core_cm4.h **** 
1985:Drivers/CMSIS/Include/core_cm4.h ****   mvfr0 = FPU->MVFR0;
1986:Drivers/CMSIS/Include/core_cm4.h ****   if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
1987:Drivers/CMSIS/Include/core_cm4.h ****   {
1988:Drivers/CMSIS/Include/core_cm4.h ****     return 1U;           /* Single precision FPU */
1989:Drivers/CMSIS/Include/core_cm4.h ****   }
1990:Drivers/CMSIS/Include/core_cm4.h ****   else
1991:Drivers/CMSIS/Include/core_cm4.h ****   {
1992:Drivers/CMSIS/Include/core_cm4.h ****     return 0U;           /* No FPU */
1993:Drivers/CMSIS/Include/core_cm4.h ****   }
1994:Drivers/CMSIS/Include/core_cm4.h **** }
1995:Drivers/CMSIS/Include/core_cm4.h **** 
1996:Drivers/CMSIS/Include/core_cm4.h **** 
1997:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of CMSIS_Core_FpuFunctions */
1998:Drivers/CMSIS/Include/core_cm4.h **** 
1999:Drivers/CMSIS/Include/core_cm4.h **** 
2000:Drivers/CMSIS/Include/core_cm4.h **** 
2001:Drivers/CMSIS/Include/core_cm4.h **** /* ##################################    SysTick function  ########################################
2002:Drivers/CMSIS/Include/core_cm4.h **** /**
2003:Drivers/CMSIS/Include/core_cm4.h ****   \ingroup  CMSIS_Core_FunctionInterface
2004:Drivers/CMSIS/Include/core_cm4.h ****   \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
2005:Drivers/CMSIS/Include/core_cm4.h ****   \brief    Functions that configure the System.
2006:Drivers/CMSIS/Include/core_cm4.h ****   @{
ARM GAS  /tmp/ccfiAGGE.s 			page 57


2007:Drivers/CMSIS/Include/core_cm4.h ****  */
2008:Drivers/CMSIS/Include/core_cm4.h **** 
2009:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2010:Drivers/CMSIS/Include/core_cm4.h **** 
2011:Drivers/CMSIS/Include/core_cm4.h **** /**
2012:Drivers/CMSIS/Include/core_cm4.h ****   \brief   System Tick Configuration
2013:Drivers/CMSIS/Include/core_cm4.h ****   \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
2014:Drivers/CMSIS/Include/core_cm4.h ****            Counter is in free running mode to generate periodic interrupts.
2015:Drivers/CMSIS/Include/core_cm4.h ****   \param [in]  ticks  Number of ticks between two interrupts.
2016:Drivers/CMSIS/Include/core_cm4.h ****   \return          0  Function succeeded.
2017:Drivers/CMSIS/Include/core_cm4.h ****   \return          1  Function failed.
2018:Drivers/CMSIS/Include/core_cm4.h ****   \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2019:Drivers/CMSIS/Include/core_cm4.h ****            function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.
2020:Drivers/CMSIS/Include/core_cm4.h ****            must contain a vendor-specific implementation of this function.
2021:Drivers/CMSIS/Include/core_cm4.h ****  */
2022:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 682              		.loc 2 2022 26 view .LVU167
 683              	.LBB49:
2023:Drivers/CMSIS/Include/core_cm4.h **** {
2024:Drivers/CMSIS/Include/core_cm4.h ****   if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 684              		.loc 2 2024 3 view .LVU168
 685              		.loc 2 2024 14 is_stmt 0 view .LVU169
 686 0000 0138     		subs	r0, r0, #1
 687              	.LVL53:
 688              		.loc 2 2024 6 view .LVU170
 689 0002 B0F1807F 		cmp	r0, #16777216
 690 0006 0BD2     		bcs	.L46
2025:Drivers/CMSIS/Include/core_cm4.h ****   {
2026:Drivers/CMSIS/Include/core_cm4.h ****     return (1UL);                                                   /* Reload value impossible */
2027:Drivers/CMSIS/Include/core_cm4.h ****   }
2028:Drivers/CMSIS/Include/core_cm4.h **** 
2029:Drivers/CMSIS/Include/core_cm4.h ****   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 691              		.loc 2 2029 3 is_stmt 1 view .LVU171
 692              		.loc 2 2029 18 is_stmt 0 view .LVU172
 693 0008 4FF0E023 		mov	r3, #-536813568
 694 000c 5861     		str	r0, [r3, #20]
2030:Drivers/CMSIS/Include/core_cm4.h ****   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Int
 695              		.loc 2 2030 3 is_stmt 1 view .LVU173
 696              	.LVL54:
 697              	.LBB50:
 698              	.LBI50:
1814:Drivers/CMSIS/Include/core_cm4.h **** {
 699              		.loc 2 1814 22 view .LVU174
 700              	.LBB51:
1816:Drivers/CMSIS/Include/core_cm4.h ****   {
 701              		.loc 2 1816 3 view .LVU175
1822:Drivers/CMSIS/Include/core_cm4.h ****   }
 702              		.loc 2 1822 5 view .LVU176
1822:Drivers/CMSIS/Include/core_cm4.h ****   }
 703              		.loc 2 1822 46 is_stmt 0 view .LVU177
 704 000e 054A     		ldr	r2, .L47
 705 0010 F021     		movs	r1, #240
 706 0012 82F82310 		strb	r1, [r2, #35]
 707              	.LVL55:
1822:Drivers/CMSIS/Include/core_cm4.h ****   }
 708              		.loc 2 1822 46 view .LVU178
 709              	.LBE51:
ARM GAS  /tmp/ccfiAGGE.s 			page 58


 710              	.LBE50:
2031:Drivers/CMSIS/Include/core_cm4.h ****   SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Val
 711              		.loc 2 2031 3 is_stmt 1 view .LVU179
 712              		.loc 2 2031 18 is_stmt 0 view .LVU180
 713 0016 0020     		movs	r0, #0
 714              	.LVL56:
 715              		.loc 2 2031 18 view .LVU181
 716 0018 9861     		str	r0, [r3, #24]
2032:Drivers/CMSIS/Include/core_cm4.h ****   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 717              		.loc 2 2032 3 is_stmt 1 view .LVU182
 718              		.loc 2 2032 18 is_stmt 0 view .LVU183
 719 001a 0722     		movs	r2, #7
 720 001c 1A61     		str	r2, [r3, #16]
2033:Drivers/CMSIS/Include/core_cm4.h ****                    SysTick_CTRL_TICKINT_Msk   |
2034:Drivers/CMSIS/Include/core_cm4.h ****                    SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTi
2035:Drivers/CMSIS/Include/core_cm4.h ****   return (0UL);                                                     /* Function successful */
 721              		.loc 2 2035 3 is_stmt 1 view .LVU184
 722              		.loc 2 2035 10 is_stmt 0 view .LVU185
 723 001e 7047     		bx	lr
 724              	.L46:
2026:Drivers/CMSIS/Include/core_cm4.h ****   }
 725              		.loc 2 2026 12 view .LVU186
 726 0020 0120     		movs	r0, #1
 727              	.LVL57:
2026:Drivers/CMSIS/Include/core_cm4.h ****   }
 728              		.loc 2 2026 12 view .LVU187
 729              	.LBE49:
 730              	.LBE48:
 230:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** }
 731              		.loc 1 230 1 view .LVU188
 732 0022 7047     		bx	lr
 733              	.L48:
 734              		.align	2
 735              	.L47:
 736 0024 00ED00E0 		.word	-536810240
 737              		.cfi_endproc
 738              	.LFE244:
 740              		.section	.text.HAL_MPU_Disable,"ax",%progbits
 741              		.align	1
 742              		.global	HAL_MPU_Disable
 743              		.syntax unified
 744              		.thumb
 745              		.thumb_func
 747              	HAL_MPU_Disable:
 748              	.LFB245:
 231:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
 232:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @}
 233:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 234:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 235:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
 236:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****  *  @brief   Cortex control functions 
 237:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****  *
 238:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** @verbatim   
 239:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   ==============================================================================
 240:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****                       ##### Peripheral Control functions #####
 241:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   ==============================================================================  
 242:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****     [..]
ARM GAS  /tmp/ccfiAGGE.s 			page 59


 243:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****       This subsection provides a set of functions allowing to control the CORTEX
 244:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****       (NVIC, SYSTICK, MPU) functionalities. 
 245:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****  
 246:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****       
 247:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** @endverbatim
 248:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @{
 249:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 250:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 251:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** #if (__MPU_PRESENT == 1U)
 252:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
 253:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief  Disables the MPU
 254:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @retval None
 255:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 256:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_MPU_Disable(void)
 257:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** {
 749              		.loc 1 257 1 is_stmt 1 view -0
 750              		.cfi_startproc
 751              		@ args = 0, pretend = 0, frame = 0
 752              		@ frame_needed = 0, uses_anonymous_args = 0
 753              		@ link register save eliminated.
 258:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Make sure outstanding transfers are done */
 259:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   __DMB();
 754              		.loc 1 259 3 view .LVU190
 755              	.LBB52:
 756              	.LBI52:
 272:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 273:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 274:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 275:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 276:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Memory Barrier
 277:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
 278:Drivers/CMSIS/Include/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
 279:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 280:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
 757              		.loc 3 280 27 view .LVU191
 758              	.LBB53:
 281:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 282:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
 759              		.loc 3 282 3 view .LVU192
 760              		.syntax unified
 761              	@ 282 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 762 0000 BFF35F8F 		dmb 0xF
 763              	@ 0 "" 2
 764              		.thumb
 765              		.syntax unified
 766              	.LBE53:
 767              	.LBE52:
 260:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 261:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Disable fault exceptions */
 262:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
 768              		.loc 1 262 3 view .LVU193
 769              		.loc 1 262 6 is_stmt 0 view .LVU194
 770 0004 044B     		ldr	r3, .L50
 771 0006 5A6A     		ldr	r2, [r3, #36]
 772              		.loc 1 262 14 view .LVU195
 773 0008 22F48032 		bic	r2, r2, #65536
 774 000c 5A62     		str	r2, [r3, #36]
ARM GAS  /tmp/ccfiAGGE.s 			page 60


 263:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   
 264:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Disable the MPU and clear the control register*/
 265:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   MPU->CTRL = 0U;
 775              		.loc 1 265 3 is_stmt 1 view .LVU196
 776              		.loc 1 265 13 is_stmt 0 view .LVU197
 777 000e 0022     		movs	r2, #0
 778 0010 C3F89420 		str	r2, [r3, #148]
 266:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** }
 779              		.loc 1 266 1 view .LVU198
 780 0014 7047     		bx	lr
 781              	.L51:
 782 0016 00BF     		.align	2
 783              	.L50:
 784 0018 00ED00E0 		.word	-536810240
 785              		.cfi_endproc
 786              	.LFE245:
 788              		.section	.text.HAL_MPU_Enable,"ax",%progbits
 789              		.align	1
 790              		.global	HAL_MPU_Enable
 791              		.syntax unified
 792              		.thumb
 793              		.thumb_func
 795              	HAL_MPU_Enable:
 796              	.LVL58:
 797              	.LFB246:
 267:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 268:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
 269:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief  Enable the MPU.
 270:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @param  MPU_Control Specifies the control mode of the MPU during hard fault, 
 271:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *          NMI, FAULTMASK and privileged access to the default memory 
 272:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *          This parameter can be one of the following values:
 273:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *            @arg MPU_HFNMI_PRIVDEF_NONE
 274:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *            @arg MPU_HARDFAULT_NMI
 275:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *            @arg MPU_PRIVILEGED_DEFAULT
 276:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *            @arg MPU_HFNMI_PRIVDEF
 277:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @retval None
 278:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 279:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_MPU_Enable(uint32_t MPU_Control)
 280:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** {
 798              		.loc 1 280 1 is_stmt 1 view -0
 799              		.cfi_startproc
 800              		@ args = 0, pretend = 0, frame = 0
 801              		@ frame_needed = 0, uses_anonymous_args = 0
 802              		@ link register save eliminated.
 281:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Enable the MPU */
 282:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
 803              		.loc 1 282 3 view .LVU200
 804              		.loc 1 282 27 is_stmt 0 view .LVU201
 805 0000 40F00100 		orr	r0, r0, #1
 806              	.LVL59:
 807              		.loc 1 282 13 view .LVU202
 808 0004 054B     		ldr	r3, .L53
 809 0006 C3F89400 		str	r0, [r3, #148]
 283:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   
 284:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Enable fault exceptions */
 285:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
 810              		.loc 1 285 3 is_stmt 1 view .LVU203
ARM GAS  /tmp/ccfiAGGE.s 			page 61


 811              		.loc 1 285 6 is_stmt 0 view .LVU204
 812 000a 5A6A     		ldr	r2, [r3, #36]
 813              		.loc 1 285 14 view .LVU205
 814 000c 42F48032 		orr	r2, r2, #65536
 815 0010 5A62     		str	r2, [r3, #36]
 286:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   
 287:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Ensure MPU setting take effects */
 288:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   __DSB();
 816              		.loc 1 288 3 is_stmt 1 view .LVU206
 817              	.LBB54:
 818              	.LBI54:
 269:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 819              		.loc 3 269 27 view .LVU207
 820              	.LBB55:
 271:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 821              		.loc 3 271 3 view .LVU208
 822              		.syntax unified
 823              	@ 271 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 824 0012 BFF34F8F 		dsb 0xF
 825              	@ 0 "" 2
 826              		.thumb
 827              		.syntax unified
 828              	.LBE55:
 829              	.LBE54:
 289:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   __ISB();
 830              		.loc 1 289 3 view .LVU209
 831              	.LBB56:
 832              	.LBI56:
 258:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 833              		.loc 3 258 27 view .LVU210
 834              	.LBB57:
 260:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 835              		.loc 3 260 3 view .LVU211
 836              		.syntax unified
 837              	@ 260 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 838 0016 BFF36F8F 		isb 0xF
 839              	@ 0 "" 2
 840              		.thumb
 841              		.syntax unified
 842              	.LBE57:
 843              	.LBE56:
 290:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** }
 844              		.loc 1 290 1 is_stmt 0 view .LVU212
 845 001a 7047     		bx	lr
 846              	.L54:
 847              		.align	2
 848              	.L53:
 849 001c 00ED00E0 		.word	-536810240
 850              		.cfi_endproc
 851              	.LFE246:
 853              		.section	.text.HAL_MPU_EnableRegion,"ax",%progbits
 854              		.align	1
 855              		.global	HAL_MPU_EnableRegion
 856              		.syntax unified
 857              		.thumb
 858              		.thumb_func
 860              	HAL_MPU_EnableRegion:
ARM GAS  /tmp/ccfiAGGE.s 			page 62


 861              	.LVL60:
 862              	.LFB247:
 291:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 292:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
 293:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief  Enables the MPU Region.
 294:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @retval None
 295:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 296:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_MPU_EnableRegion(uint32_t RegionNumber)
 297:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** {
 863              		.loc 1 297 1 is_stmt 1 view -0
 864              		.cfi_startproc
 865              		@ args = 0, pretend = 0, frame = 0
 866              		@ frame_needed = 0, uses_anonymous_args = 0
 867              		@ link register save eliminated.
 298:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Check the parameters */
 299:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
 868              		.loc 1 299 3 view .LVU214
 300:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 301:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Set the Region number */
 302:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   MPU->RNR = RegionNumber;
 869              		.loc 1 302 3 view .LVU215
 870              		.loc 1 302 12 is_stmt 0 view .LVU216
 871 0000 044B     		ldr	r3, .L56
 872 0002 C3F89800 		str	r0, [r3, #152]
 303:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 304:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Enable the Region */
 305:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
 873              		.loc 1 305 3 is_stmt 1 view .LVU217
 874 0006 D3F8A020 		ldr	r2, [r3, #160]
 875 000a 42F00102 		orr	r2, r2, #1
 876 000e C3F8A020 		str	r2, [r3, #160]
 306:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** }
 877              		.loc 1 306 1 is_stmt 0 view .LVU218
 878 0012 7047     		bx	lr
 879              	.L57:
 880              		.align	2
 881              	.L56:
 882 0014 00ED00E0 		.word	-536810240
 883              		.cfi_endproc
 884              	.LFE247:
 886              		.section	.text.HAL_MPU_DisableRegion,"ax",%progbits
 887              		.align	1
 888              		.global	HAL_MPU_DisableRegion
 889              		.syntax unified
 890              		.thumb
 891              		.thumb_func
 893              	HAL_MPU_DisableRegion:
 894              	.LVL61:
 895              	.LFB248:
 307:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 308:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
 309:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief  Disables the MPU Region.
 310:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @retval None
 311:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 312:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_MPU_DisableRegion(uint32_t RegionNumber)
 313:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** {
 896              		.loc 1 313 1 is_stmt 1 view -0
ARM GAS  /tmp/ccfiAGGE.s 			page 63


 897              		.cfi_startproc
 898              		@ args = 0, pretend = 0, frame = 0
 899              		@ frame_needed = 0, uses_anonymous_args = 0
 900              		@ link register save eliminated.
 314:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Check the parameters */
 315:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
 901              		.loc 1 315 3 view .LVU220
 316:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 317:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Set the Region number */
 318:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   MPU->RNR = RegionNumber;
 902              		.loc 1 318 3 view .LVU221
 903              		.loc 1 318 12 is_stmt 0 view .LVU222
 904 0000 044B     		ldr	r3, .L59
 905 0002 C3F89800 		str	r0, [r3, #152]
 319:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 320:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Disable the Region */
 321:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
 906              		.loc 1 321 3 is_stmt 1 view .LVU223
 907 0006 D3F8A020 		ldr	r2, [r3, #160]
 908 000a 22F00102 		bic	r2, r2, #1
 909 000e C3F8A020 		str	r2, [r3, #160]
 322:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** }
 910              		.loc 1 322 1 is_stmt 0 view .LVU224
 911 0012 7047     		bx	lr
 912              	.L60:
 913              		.align	2
 914              	.L59:
 915 0014 00ED00E0 		.word	-536810240
 916              		.cfi_endproc
 917              	.LFE248:
 919              		.section	.text.HAL_MPU_ConfigRegion,"ax",%progbits
 920              		.align	1
 921              		.global	HAL_MPU_ConfigRegion
 922              		.syntax unified
 923              		.thumb
 924              		.thumb_func
 926              	HAL_MPU_ConfigRegion:
 927              	.LVL62:
 928              	.LFB249:
 323:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 324:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
 325:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief  Initializes and configures the Region and the memory to be protected.
 326:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
 327:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *                the initialization and configuration information.
 328:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @retval None
 329:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 330:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
 331:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** {
 929              		.loc 1 331 1 is_stmt 1 view -0
 930              		.cfi_startproc
 931              		@ args = 0, pretend = 0, frame = 0
 932              		@ frame_needed = 0, uses_anonymous_args = 0
 933              		@ link register save eliminated.
 332:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Check the parameters */
 333:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
 934              		.loc 1 333 3 view .LVU226
 334:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
ARM GAS  /tmp/ccfiAGGE.s 			page 64


 935              		.loc 1 334 3 view .LVU227
 335:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
 936              		.loc 1 335 3 view .LVU228
 336:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
 937              		.loc 1 336 3 view .LVU229
 337:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
 938              		.loc 1 337 3 view .LVU230
 338:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
 939              		.loc 1 338 3 view .LVU231
 339:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
 940              		.loc 1 339 3 view .LVU232
 340:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
 941              		.loc 1 340 3 view .LVU233
 341:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
 942              		.loc 1 341 3 view .LVU234
 342:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
 943              		.loc 1 342 3 view .LVU235
 343:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 344:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Set the Region number */
 345:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   MPU->RNR = MPU_Init->Number;
 944              		.loc 1 345 3 view .LVU236
 945              		.loc 1 345 22 is_stmt 0 view .LVU237
 946 0000 4378     		ldrb	r3, [r0, #1]	@ zero_extendqisi2
 947              		.loc 1 345 12 view .LVU238
 948 0002 144A     		ldr	r2, .L62
 949 0004 C2F89830 		str	r3, [r2, #152]
 346:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 347:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Disable the Region */
 348:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
 950              		.loc 1 348 3 is_stmt 1 view .LVU239
 951 0008 D2F8A030 		ldr	r3, [r2, #160]
 952 000c 23F00103 		bic	r3, r3, #1
 953 0010 C2F8A030 		str	r3, [r2, #160]
 349:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 350:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Apply configuration */
 351:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   MPU->RBAR = MPU_Init->BaseAddress;
 954              		.loc 1 351 3 view .LVU240
 955              		.loc 1 351 23 is_stmt 0 view .LVU241
 956 0014 4368     		ldr	r3, [r0, #4]
 957              		.loc 1 351 13 view .LVU242
 958 0016 C2F89C30 		str	r3, [r2, #156]
 352:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
 959              		.loc 1 352 3 is_stmt 1 view .LVU243
 960              		.loc 1 352 34 is_stmt 0 view .LVU244
 961 001a 017B     		ldrb	r1, [r0, #12]	@ zero_extendqisi2
 353:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****               ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
 962              		.loc 1 353 34 view .LVU245
 963 001c C37A     		ldrb	r3, [r0, #11]	@ zero_extendqisi2
 964              		.loc 1 353 60 view .LVU246
 965 001e 1B06     		lsls	r3, r3, #24
 352:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
 966              		.loc 1 352 82 view .LVU247
 967 0020 43EA0173 		orr	r3, r3, r1, lsl #28
 354:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****               ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
 968              		.loc 1 354 34 view .LVU248
 969 0024 817A     		ldrb	r1, [r0, #10]	@ zero_extendqisi2
 353:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****               ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
ARM GAS  /tmp/ccfiAGGE.s 			page 65


 970              		.loc 1 353 82 view .LVU249
 971 0026 43EAC143 		orr	r3, r3, r1, lsl #19
 355:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****               ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
 972              		.loc 1 355 34 view .LVU250
 973 002a 417B     		ldrb	r1, [r0, #13]	@ zero_extendqisi2
 354:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****               ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
 974              		.loc 1 354 82 view .LVU251
 975 002c 43EA8143 		orr	r3, r3, r1, lsl #18
 356:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****               ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
 976              		.loc 1 356 34 view .LVU252
 977 0030 817B     		ldrb	r1, [r0, #14]	@ zero_extendqisi2
 355:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****               ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
 978              		.loc 1 355 82 view .LVU253
 979 0032 43EA4143 		orr	r3, r3, r1, lsl #17
 357:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****               ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
 980              		.loc 1 357 34 view .LVU254
 981 0036 C17B     		ldrb	r1, [r0, #15]	@ zero_extendqisi2
 356:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****               ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
 982              		.loc 1 356 82 view .LVU255
 983 0038 43EA0143 		orr	r3, r3, r1, lsl #16
 358:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****               ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
 984              		.loc 1 358 34 view .LVU256
 985 003c 417A     		ldrb	r1, [r0, #9]	@ zero_extendqisi2
 357:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****               ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
 986              		.loc 1 357 82 view .LVU257
 987 003e 43EA0123 		orr	r3, r3, r1, lsl #8
 359:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****               ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
 988              		.loc 1 359 34 view .LVU258
 989 0042 017A     		ldrb	r1, [r0, #8]	@ zero_extendqisi2
 358:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****               ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
 990              		.loc 1 358 82 view .LVU259
 991 0044 43EA4103 		orr	r3, r3, r1, lsl #1
 360:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****               ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
 992              		.loc 1 360 34 view .LVU260
 993 0048 0178     		ldrb	r1, [r0]	@ zero_extendqisi2
 359:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****               ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
 994              		.loc 1 359 82 view .LVU261
 995 004a 0B43     		orrs	r3, r3, r1
 352:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****               ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
 996              		.loc 1 352 13 view .LVU262
 997 004c C2F8A030 		str	r3, [r2, #160]
 361:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** }
 998              		.loc 1 361 1 view .LVU263
 999 0050 7047     		bx	lr
 1000              	.L63:
 1001 0052 00BF     		.align	2
 1002              	.L62:
 1003 0054 00ED00E0 		.word	-536810240
 1004              		.cfi_endproc
 1005              	.LFE249:
 1007              		.section	.text.HAL_CORTEX_ClearEvent,"ax",%progbits
 1008              		.align	1
 1009              		.global	HAL_CORTEX_ClearEvent
 1010              		.syntax unified
 1011              		.thumb
 1012              		.thumb_func
 1014              	HAL_CORTEX_ClearEvent:
ARM GAS  /tmp/ccfiAGGE.s 			page 66


 1015              	.LFB250:
 362:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** #endif /* __MPU_PRESENT */
 363:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 364:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
 365:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief  Clear pending events.
 366:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @retval None
 367:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 368:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_CORTEX_ClearEvent(void)
 369:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** {
 1016              		.loc 1 369 1 is_stmt 1 view -0
 1017              		.cfi_startproc
 1018              		@ args = 0, pretend = 0, frame = 0
 1019              		@ frame_needed = 0, uses_anonymous_args = 0
 1020              		@ link register save eliminated.
 370:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   __SEV();
 1021              		.loc 1 370 3 view .LVU265
 1022              		.syntax unified
 1023              	@ 370 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c" 1
 1024 0000 40BF     		sev
 1025              	@ 0 "" 2
 371:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   __WFE();
 1026              		.loc 1 371 3 view .LVU266
 1027              	@ 371 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c" 1
 1028 0002 20BF     		wfe
 1029              	@ 0 "" 2
 372:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** }
 1030              		.loc 1 372 1 is_stmt 0 view .LVU267
 1031              		.thumb
 1032              		.syntax unified
 1033 0004 7047     		bx	lr
 1034              		.cfi_endproc
 1035              	.LFE250:
 1037              		.section	.text.HAL_NVIC_GetPriorityGrouping,"ax",%progbits
 1038              		.align	1
 1039              		.global	HAL_NVIC_GetPriorityGrouping
 1040              		.syntax unified
 1041              		.thumb
 1042              		.thumb_func
 1044              	HAL_NVIC_GetPriorityGrouping:
 1045              	.LFB251:
 373:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 374:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
 375:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
 376:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
 377:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 378:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPriorityGrouping(void)
 379:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** {
 1046              		.loc 1 379 1 is_stmt 1 view -0
 1047              		.cfi_startproc
 1048              		@ args = 0, pretend = 0, frame = 0
 1049              		@ frame_needed = 0, uses_anonymous_args = 0
 1050              		@ link register save eliminated.
 380:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Get the PRIGROUP[10:8] field value */
 381:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   return NVIC_GetPriorityGrouping();
 1051              		.loc 1 381 3 view .LVU269
 1052              	.LBB58:
 1053              	.LBI58:
ARM GAS  /tmp/ccfiAGGE.s 			page 67


1672:Drivers/CMSIS/Include/core_cm4.h **** {
 1054              		.loc 2 1672 26 view .LVU270
 1055              	.LBB59:
1674:Drivers/CMSIS/Include/core_cm4.h **** }
 1056              		.loc 2 1674 3 view .LVU271
1674:Drivers/CMSIS/Include/core_cm4.h **** }
 1057              		.loc 2 1674 26 is_stmt 0 view .LVU272
 1058 0000 024B     		ldr	r3, .L66
 1059 0002 D868     		ldr	r0, [r3, #12]
 1060              	.LBE59:
 1061              	.LBE58:
 382:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** }
 1062              		.loc 1 382 1 view .LVU273
 1063 0004 C0F30220 		ubfx	r0, r0, #8, #3
 1064 0008 7047     		bx	lr
 1065              	.L67:
 1066 000a 00BF     		.align	2
 1067              	.L66:
 1068 000c 00ED00E0 		.word	-536810240
 1069              		.cfi_endproc
 1070              	.LFE251:
 1072              		.section	.text.HAL_NVIC_GetPriority,"ax",%progbits
 1073              		.align	1
 1074              		.global	HAL_NVIC_GetPriority
 1075              		.syntax unified
 1076              		.thumb
 1077              		.thumb_func
 1079              	HAL_NVIC_GetPriority:
 1080              	.LVL63:
 1081              	.LFB252:
 383:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 384:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
 385:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief  Gets the priority of an interrupt.
 386:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
 387:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
 388:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
 389:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @param   PriorityGroup the priority grouping bits length.
 390:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         This parameter can be one of the following values:
 391:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
 392:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *                                      4 bits for subpriority
 393:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
 394:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *                                      3 bits for subpriority
 395:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
 396:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *                                      2 bits for subpriority
 397:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
 398:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *                                      1 bits for subpriority
 399:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
 400:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *                                      0 bits for subpriority
 401:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @param  pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
 402:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @param  pSubPriority Pointer on the Subpriority value (starting from 0).
 403:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @retval None
 404:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 405:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint3
 406:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** {
 1082              		.loc 1 406 1 is_stmt 1 view -0
 1083              		.cfi_startproc
 1084              		@ args = 0, pretend = 0, frame = 0
ARM GAS  /tmp/ccfiAGGE.s 			page 68


 1085              		@ frame_needed = 0, uses_anonymous_args = 0
 1086              		.loc 1 406 1 is_stmt 0 view .LVU275
 1087 0000 70B5     		push	{r4, r5, r6, lr}
 1088              	.LCFI6:
 1089              		.cfi_def_cfa_offset 16
 1090              		.cfi_offset 4, -16
 1091              		.cfi_offset 5, -12
 1092              		.cfi_offset 6, -8
 1093              		.cfi_offset 14, -4
 1094 0002 0C46     		mov	r4, r1
 1095 0004 1546     		mov	r5, r2
 1096 0006 1E46     		mov	r6, r3
 407:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Check the parameters */
 408:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
 1097              		.loc 1 408 3 is_stmt 1 view .LVU276
 409:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****  /* Get priority for Cortex-M system or device specific interrupts */
 410:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
 1098              		.loc 1 410 3 view .LVU277
 1099 0008 FFF7FEFF 		bl	__NVIC_GetPriority
 1100              	.LVL64:
 1101              		.loc 1 410 3 is_stmt 0 discriminator 1 view .LVU278
 1102 000c 3346     		mov	r3, r6
 1103 000e 2A46     		mov	r2, r5
 1104 0010 2146     		mov	r1, r4
 1105 0012 FFF7FEFF 		bl	NVIC_DecodePriority
 1106              	.LVL65:
 411:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** }
 1107              		.loc 1 411 1 view .LVU279
 1108 0016 70BD     		pop	{r4, r5, r6, pc}
 1109              		.loc 1 411 1 view .LVU280
 1110              		.cfi_endproc
 1111              	.LFE252:
 1113              		.section	.text.HAL_NVIC_SetPendingIRQ,"ax",%progbits
 1114              		.align	1
 1115              		.global	HAL_NVIC_SetPendingIRQ
 1116              		.syntax unified
 1117              		.thumb
 1118              		.thumb_func
 1120              	HAL_NVIC_SetPendingIRQ:
 1121              	.LVL66:
 1122              	.LFB253:
 412:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 413:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
 414:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief  Sets Pending bit of an external interrupt.
 415:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @param  IRQn External interrupt number
 416:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
 417:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
 418:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @retval None
 419:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 420:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
 421:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** {
 1123              		.loc 1 421 1 is_stmt 1 view -0
 1124              		.cfi_startproc
 1125              		@ args = 0, pretend = 0, frame = 0
 1126              		@ frame_needed = 0, uses_anonymous_args = 0
 1127              		@ link register save eliminated.
 422:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Check the parameters */
ARM GAS  /tmp/ccfiAGGE.s 			page 69


 423:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 1128              		.loc 1 423 3 view .LVU282
 424:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   
 425:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Set interrupt pending */
 426:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   NVIC_SetPendingIRQ(IRQn);
 1129              		.loc 1 426 3 view .LVU283
 1130              	.LBB60:
 1131              	.LBI60:
1760:Drivers/CMSIS/Include/core_cm4.h **** {
 1132              		.loc 2 1760 22 view .LVU284
 1133              	.LBB61:
1762:Drivers/CMSIS/Include/core_cm4.h ****   {
 1134              		.loc 2 1762 3 view .LVU285
1762:Drivers/CMSIS/Include/core_cm4.h ****   {
 1135              		.loc 2 1762 6 is_stmt 0 view .LVU286
 1136 0000 0028     		cmp	r0, #0
1762:Drivers/CMSIS/Include/core_cm4.h ****   {
 1137              		.loc 2 1762 6 view .LVU287
 1138 0002 08DB     		blt	.L70
1764:Drivers/CMSIS/Include/core_cm4.h ****   }
 1139              		.loc 2 1764 5 is_stmt 1 view .LVU288
1764:Drivers/CMSIS/Include/core_cm4.h ****   }
 1140              		.loc 2 1764 81 is_stmt 0 view .LVU289
 1141 0004 00F01F02 		and	r2, r0, #31
1764:Drivers/CMSIS/Include/core_cm4.h ****   }
 1142              		.loc 2 1764 34 view .LVU290
 1143 0008 4009     		lsrs	r0, r0, #5
 1144              	.LVL67:
1764:Drivers/CMSIS/Include/core_cm4.h ****   }
 1145              		.loc 2 1764 45 view .LVU291
 1146 000a 0123     		movs	r3, #1
 1147 000c 9340     		lsls	r3, r3, r2
1764:Drivers/CMSIS/Include/core_cm4.h ****   }
 1148              		.loc 2 1764 43 view .LVU292
 1149 000e 4030     		adds	r0, r0, #64
 1150 0010 014A     		ldr	r2, .L72
 1151 0012 42F82030 		str	r3, [r2, r0, lsl #2]
 1152              	.LVL68:
 1153              	.L70:
1764:Drivers/CMSIS/Include/core_cm4.h ****   }
 1154              		.loc 2 1764 43 view .LVU293
 1155              	.LBE61:
 1156              	.LBE60:
 427:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** }
 1157              		.loc 1 427 1 view .LVU294
 1158 0016 7047     		bx	lr
 1159              	.L73:
 1160              		.align	2
 1161              	.L72:
 1162 0018 00E100E0 		.word	-536813312
 1163              		.cfi_endproc
 1164              	.LFE253:
 1166              		.section	.text.HAL_NVIC_GetPendingIRQ,"ax",%progbits
 1167              		.align	1
 1168              		.global	HAL_NVIC_GetPendingIRQ
 1169              		.syntax unified
 1170              		.thumb
ARM GAS  /tmp/ccfiAGGE.s 			page 70


 1171              		.thumb_func
 1173              	HAL_NVIC_GetPendingIRQ:
 1174              	.LVL69:
 1175              	.LFB254:
 428:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 429:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
 430:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief  Gets Pending Interrupt (reads the pending register in the NVIC 
 431:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         and returns the pending bit for the specified interrupt).
 432:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
 433:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *          This parameter can be an enumerator of IRQn_Type enumeration
 434:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
 435:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @retval status: - 0  Interrupt status is not pending.
 436:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *                 - 1  Interrupt status is pending.
 437:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 438:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
 439:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** {
 1176              		.loc 1 439 1 is_stmt 1 view -0
 1177              		.cfi_startproc
 1178              		@ args = 0, pretend = 0, frame = 0
 1179              		@ frame_needed = 0, uses_anonymous_args = 0
 1180              		@ link register save eliminated.
 440:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Check the parameters */
 441:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 1181              		.loc 1 441 3 view .LVU296
 442:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   
 443:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Return 1 if pending else 0 */
 444:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   return NVIC_GetPendingIRQ(IRQn);
 1182              		.loc 1 444 3 view .LVU297
 1183              	.LBB62:
 1184              	.LBI62:
1741:Drivers/CMSIS/Include/core_cm4.h **** {
 1185              		.loc 2 1741 26 view .LVU298
 1186              	.LBB63:
1743:Drivers/CMSIS/Include/core_cm4.h ****   {
 1187              		.loc 2 1743 3 view .LVU299
1743:Drivers/CMSIS/Include/core_cm4.h ****   {
 1188              		.loc 2 1743 6 is_stmt 0 view .LVU300
 1189 0000 0028     		cmp	r0, #0
1743:Drivers/CMSIS/Include/core_cm4.h ****   {
 1190              		.loc 2 1743 6 view .LVU301
 1191 0002 0BDB     		blt	.L76
1745:Drivers/CMSIS/Include/core_cm4.h ****   }
 1192              		.loc 2 1745 5 is_stmt 1 view .LVU302
1745:Drivers/CMSIS/Include/core_cm4.h ****   }
 1193              		.loc 2 1745 54 is_stmt 0 view .LVU303
 1194 0004 4309     		lsrs	r3, r0, #5
1745:Drivers/CMSIS/Include/core_cm4.h ****   }
 1195              		.loc 2 1745 35 view .LVU304
 1196 0006 4033     		adds	r3, r3, #64
 1197 0008 054A     		ldr	r2, .L77
 1198 000a 52F82330 		ldr	r3, [r2, r3, lsl #2]
1745:Drivers/CMSIS/Include/core_cm4.h ****   }
 1199              		.loc 2 1745 91 view .LVU305
 1200 000e 00F01F00 		and	r0, r0, #31
 1201              	.LVL70:
1745:Drivers/CMSIS/Include/core_cm4.h ****   }
 1202              		.loc 2 1745 103 view .LVU306
ARM GAS  /tmp/ccfiAGGE.s 			page 71


 1203 0012 23FA00F0 		lsr	r0, r3, r0
1745:Drivers/CMSIS/Include/core_cm4.h ****   }
 1204              		.loc 2 1745 12 view .LVU307
 1205 0016 00F00100 		and	r0, r0, #1
 1206 001a 7047     		bx	lr
 1207              	.L76:
1749:Drivers/CMSIS/Include/core_cm4.h ****   }
 1208              		.loc 2 1749 11 view .LVU308
 1209 001c 0020     		movs	r0, #0
 1210              	.LVL71:
1749:Drivers/CMSIS/Include/core_cm4.h ****   }
 1211              		.loc 2 1749 11 view .LVU309
 1212              	.LBE63:
 1213              	.LBE62:
 445:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** }
 1214              		.loc 1 445 1 view .LVU310
 1215 001e 7047     		bx	lr
 1216              	.L78:
 1217              		.align	2
 1218              	.L77:
 1219 0020 00E100E0 		.word	-536813312
 1220              		.cfi_endproc
 1221              	.LFE254:
 1223              		.section	.text.HAL_NVIC_ClearPendingIRQ,"ax",%progbits
 1224              		.align	1
 1225              		.global	HAL_NVIC_ClearPendingIRQ
 1226              		.syntax unified
 1227              		.thumb
 1228              		.thumb_func
 1230              	HAL_NVIC_ClearPendingIRQ:
 1231              	.LVL72:
 1232              	.LFB255:
 446:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 447:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
 448:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief  Clears the pending bit of an external interrupt.
 449:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
 450:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
 451:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
 452:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @retval None
 453:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 454:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 455:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** {
 1233              		.loc 1 455 1 is_stmt 1 view -0
 1234              		.cfi_startproc
 1235              		@ args = 0, pretend = 0, frame = 0
 1236              		@ frame_needed = 0, uses_anonymous_args = 0
 1237              		@ link register save eliminated.
 456:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Check the parameters */
 457:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 1238              		.loc 1 457 3 view .LVU312
 458:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   
 459:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Clear pending interrupt */
 460:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   NVIC_ClearPendingIRQ(IRQn);
 1239              		.loc 1 460 3 view .LVU313
 1240              	.LBB64:
 1241              	.LBI64:
1775:Drivers/CMSIS/Include/core_cm4.h **** {
ARM GAS  /tmp/ccfiAGGE.s 			page 72


 1242              		.loc 2 1775 22 view .LVU314
 1243              	.LBB65:
1777:Drivers/CMSIS/Include/core_cm4.h ****   {
 1244              		.loc 2 1777 3 view .LVU315
1777:Drivers/CMSIS/Include/core_cm4.h ****   {
 1245              		.loc 2 1777 6 is_stmt 0 view .LVU316
 1246 0000 0028     		cmp	r0, #0
1777:Drivers/CMSIS/Include/core_cm4.h ****   {
 1247              		.loc 2 1777 6 view .LVU317
 1248 0002 08DB     		blt	.L79
1779:Drivers/CMSIS/Include/core_cm4.h ****   }
 1249              		.loc 2 1779 5 is_stmt 1 view .LVU318
1779:Drivers/CMSIS/Include/core_cm4.h ****   }
 1250              		.loc 2 1779 81 is_stmt 0 view .LVU319
 1251 0004 00F01F02 		and	r2, r0, #31
1779:Drivers/CMSIS/Include/core_cm4.h ****   }
 1252              		.loc 2 1779 34 view .LVU320
 1253 0008 4009     		lsrs	r0, r0, #5
 1254              	.LVL73:
1779:Drivers/CMSIS/Include/core_cm4.h ****   }
 1255              		.loc 2 1779 45 view .LVU321
 1256 000a 0123     		movs	r3, #1
 1257 000c 9340     		lsls	r3, r3, r2
1779:Drivers/CMSIS/Include/core_cm4.h ****   }
 1258              		.loc 2 1779 43 view .LVU322
 1259 000e 6030     		adds	r0, r0, #96
 1260 0010 014A     		ldr	r2, .L81
 1261 0012 42F82030 		str	r3, [r2, r0, lsl #2]
 1262              	.LVL74:
 1263              	.L79:
1779:Drivers/CMSIS/Include/core_cm4.h ****   }
 1264              		.loc 2 1779 43 view .LVU323
 1265              	.LBE65:
 1266              	.LBE64:
 461:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** }
 1267              		.loc 1 461 1 view .LVU324
 1268 0016 7047     		bx	lr
 1269              	.L82:
 1270              		.align	2
 1271              	.L81:
 1272 0018 00E100E0 		.word	-536813312
 1273              		.cfi_endproc
 1274              	.LFE255:
 1276              		.section	.text.HAL_NVIC_GetActive,"ax",%progbits
 1277              		.align	1
 1278              		.global	HAL_NVIC_GetActive
 1279              		.syntax unified
 1280              		.thumb
 1281              		.thumb_func
 1283              	HAL_NVIC_GetActive:
 1284              	.LVL75:
 1285              	.LFB256:
 462:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 463:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
 464:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
 465:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @param IRQn External interrupt number
 466:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
ARM GAS  /tmp/ccfiAGGE.s 			page 73


 467:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
 468:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @retval status: - 0  Interrupt status is not pending.
 469:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *                 - 1  Interrupt status is pending.
 470:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 471:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
 472:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** {
 1286              		.loc 1 472 1 is_stmt 1 view -0
 1287              		.cfi_startproc
 1288              		@ args = 0, pretend = 0, frame = 0
 1289              		@ frame_needed = 0, uses_anonymous_args = 0
 1290              		@ link register save eliminated.
 473:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Check the parameters */
 474:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 1291              		.loc 1 474 3 view .LVU326
 475:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   
 476:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Return 1 if active else 0 */
 477:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   return NVIC_GetActive(IRQn);
 1292              		.loc 1 477 3 view .LVU327
 1293              	.LBB66:
 1294              	.LBI66:
1792:Drivers/CMSIS/Include/core_cm4.h **** {
 1295              		.loc 2 1792 26 view .LVU328
 1296              	.LBB67:
1794:Drivers/CMSIS/Include/core_cm4.h ****   {
 1297              		.loc 2 1794 3 view .LVU329
1794:Drivers/CMSIS/Include/core_cm4.h ****   {
 1298              		.loc 2 1794 6 is_stmt 0 view .LVU330
 1299 0000 0028     		cmp	r0, #0
1794:Drivers/CMSIS/Include/core_cm4.h ****   {
 1300              		.loc 2 1794 6 view .LVU331
 1301 0002 0BDB     		blt	.L85
1796:Drivers/CMSIS/Include/core_cm4.h ****   }
 1302              		.loc 2 1796 5 is_stmt 1 view .LVU332
1796:Drivers/CMSIS/Include/core_cm4.h ****   }
 1303              		.loc 2 1796 54 is_stmt 0 view .LVU333
 1304 0004 4309     		lsrs	r3, r0, #5
1796:Drivers/CMSIS/Include/core_cm4.h ****   }
 1305              		.loc 2 1796 35 view .LVU334
 1306 0006 8033     		adds	r3, r3, #128
 1307 0008 054A     		ldr	r2, .L86
 1308 000a 52F82330 		ldr	r3, [r2, r3, lsl #2]
1796:Drivers/CMSIS/Include/core_cm4.h ****   }
 1309              		.loc 2 1796 91 view .LVU335
 1310 000e 00F01F00 		and	r0, r0, #31
 1311              	.LVL76:
1796:Drivers/CMSIS/Include/core_cm4.h ****   }
 1312              		.loc 2 1796 103 view .LVU336
 1313 0012 23FA00F0 		lsr	r0, r3, r0
1796:Drivers/CMSIS/Include/core_cm4.h ****   }
 1314              		.loc 2 1796 12 view .LVU337
 1315 0016 00F00100 		and	r0, r0, #1
 1316 001a 7047     		bx	lr
 1317              	.L85:
1800:Drivers/CMSIS/Include/core_cm4.h ****   }
 1318              		.loc 2 1800 11 view .LVU338
 1319 001c 0020     		movs	r0, #0
 1320              	.LVL77:
ARM GAS  /tmp/ccfiAGGE.s 			page 74


1800:Drivers/CMSIS/Include/core_cm4.h ****   }
 1321              		.loc 2 1800 11 view .LVU339
 1322              	.LBE67:
 1323              	.LBE66:
 478:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** }
 1324              		.loc 1 478 1 view .LVU340
 1325 001e 7047     		bx	lr
 1326              	.L87:
 1327              		.align	2
 1328              	.L86:
 1329 0020 00E100E0 		.word	-536813312
 1330              		.cfi_endproc
 1331              	.LFE256:
 1333              		.section	.text.HAL_SYSTICK_CLKSourceConfig,"ax",%progbits
 1334              		.align	1
 1335              		.global	HAL_SYSTICK_CLKSourceConfig
 1336              		.syntax unified
 1337              		.thumb
 1338              		.thumb_func
 1340              	HAL_SYSTICK_CLKSourceConfig:
 1341              	.LVL78:
 1342              	.LFB257:
 479:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 480:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
 481:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief  Configures the SysTick clock source.
 482:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @param  CLKSource specifies the SysTick clock source.
 483:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *          This parameter can be one of the following values:
 484:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock 
 485:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
 486:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @retval None
 487:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 488:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
 489:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** {
 1343              		.loc 1 489 1 is_stmt 1 view -0
 1344              		.cfi_startproc
 1345              		@ args = 0, pretend = 0, frame = 0
 1346              		@ frame_needed = 0, uses_anonymous_args = 0
 1347              		@ link register save eliminated.
 490:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* Check the parameters */
 491:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
 1348              		.loc 1 491 3 view .LVU342
 492:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
 1349              		.loc 1 492 3 view .LVU343
 1350              		.loc 1 492 6 is_stmt 0 view .LVU344
 1351 0000 0428     		cmp	r0, #4
 1352 0002 06D0     		beq	.L91
 493:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   {
 494:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****     SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
 495:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   }
 496:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   else
 497:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   {
 498:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****     SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
 1353              		.loc 1 498 5 is_stmt 1 view .LVU345
 1354              		.loc 1 498 12 is_stmt 0 view .LVU346
 1355 0004 4FF0E022 		mov	r2, #-536813568
 1356 0008 1369     		ldr	r3, [r2, #16]
 1357              		.loc 1 498 19 view .LVU347
ARM GAS  /tmp/ccfiAGGE.s 			page 75


 1358 000a 23F00403 		bic	r3, r3, #4
 1359 000e 1361     		str	r3, [r2, #16]
 499:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   }
 500:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** }
 1360              		.loc 1 500 1 view .LVU348
 1361 0010 7047     		bx	lr
 1362              	.L91:
 494:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   }
 1363              		.loc 1 494 5 is_stmt 1 view .LVU349
 494:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   }
 1364              		.loc 1 494 12 is_stmt 0 view .LVU350
 1365 0012 4FF0E022 		mov	r2, #-536813568
 1366 0016 1369     		ldr	r3, [r2, #16]
 494:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   }
 1367              		.loc 1 494 19 view .LVU351
 1368 0018 43F00403 		orr	r3, r3, #4
 1369 001c 1361     		str	r3, [r2, #16]
 1370 001e 7047     		bx	lr
 1371              		.cfi_endproc
 1372              	.LFE257:
 1374              		.section	.text.HAL_SYSTICK_Callback,"ax",%progbits
 1375              		.align	1
 1376              		.weak	HAL_SYSTICK_Callback
 1377              		.syntax unified
 1378              		.thumb
 1379              		.thumb_func
 1381              	HAL_SYSTICK_Callback:
 1382              	.LFB259:
 501:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 502:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
 503:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief  This function handles SYSTICK interrupt request.
 504:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @retval None
 505:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 506:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_SYSTICK_IRQHandler(void)
 507:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** {
 508:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   HAL_SYSTICK_Callback();
 509:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** }
 510:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 511:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /**
 512:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @brief  SYSTICK callback.
 513:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   * @retval None
 514:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   */
 515:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** __weak void HAL_SYSTICK_Callback(void)
 516:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** {
 1383              		.loc 1 516 1 is_stmt 1 view -0
 1384              		.cfi_startproc
 1385              		@ args = 0, pretend = 0, frame = 0
 1386              		@ frame_needed = 0, uses_anonymous_args = 0
 1387              		@ link register save eliminated.
 517:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
 518:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****             the HAL_SYSTICK_Callback could be implemented in the user file
 519:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****    */
 520:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** }
 1388              		.loc 1 520 1 view .LVU353
 1389 0000 7047     		bx	lr
 1390              		.cfi_endproc
 1391              	.LFE259:
ARM GAS  /tmp/ccfiAGGE.s 			page 76


 1393              		.section	.text.HAL_SYSTICK_IRQHandler,"ax",%progbits
 1394              		.align	1
 1395              		.global	HAL_SYSTICK_IRQHandler
 1396              		.syntax unified
 1397              		.thumb
 1398              		.thumb_func
 1400              	HAL_SYSTICK_IRQHandler:
 1401              	.LFB258:
 507:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ****   HAL_SYSTICK_Callback();
 1402              		.loc 1 507 1 view -0
 1403              		.cfi_startproc
 1404              		@ args = 0, pretend = 0, frame = 0
 1405              		@ frame_needed = 0, uses_anonymous_args = 0
 1406 0000 08B5     		push	{r3, lr}
 1407              	.LCFI7:
 1408              		.cfi_def_cfa_offset 8
 1409              		.cfi_offset 3, -8
 1410              		.cfi_offset 14, -4
 508:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** }
 1411              		.loc 1 508 3 view .LVU355
 1412 0002 FFF7FEFF 		bl	HAL_SYSTICK_Callback
 1413              	.LVL79:
 509:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 
 1414              		.loc 1 509 1 is_stmt 0 view .LVU356
 1415 0006 08BD     		pop	{r3, pc}
 1416              		.cfi_endproc
 1417              	.LFE258:
 1419              		.text
 1420              	.Letext0:
 1421              		.file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h"
 1422              		.file 5 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h"
 1423              		.file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h"
ARM GAS  /tmp/ccfiAGGE.s 			page 77


DEFINED SYMBOLS
                            *ABS*:00000000 stm32f4xx_hal_cortex.c
     /tmp/ccfiAGGE.s:21     .text.__NVIC_EnableIRQ:00000000 $t
     /tmp/ccfiAGGE.s:26     .text.__NVIC_EnableIRQ:00000000 __NVIC_EnableIRQ
     /tmp/ccfiAGGE.s:60     .text.__NVIC_EnableIRQ:00000018 $d
     /tmp/ccfiAGGE.s:65     .text.__NVIC_DisableIRQ:00000000 $t
     /tmp/ccfiAGGE.s:70     .text.__NVIC_DisableIRQ:00000000 __NVIC_DisableIRQ
     /tmp/ccfiAGGE.s:131    .text.__NVIC_DisableIRQ:00000020 $d
     /tmp/ccfiAGGE.s:136    .text.__NVIC_SetPriority:00000000 $t
     /tmp/ccfiAGGE.s:141    .text.__NVIC_SetPriority:00000000 __NVIC_SetPriority
     /tmp/ccfiAGGE.s:188    .text.__NVIC_SetPriority:00000024 $d
     /tmp/ccfiAGGE.s:193    .text.__NVIC_GetPriority:00000000 $t
     /tmp/ccfiAGGE.s:198    .text.__NVIC_GetPriority:00000000 __NVIC_GetPriority
     /tmp/ccfiAGGE.s:238    .text.__NVIC_GetPriority:00000020 $d
     /tmp/ccfiAGGE.s:243    .text.NVIC_EncodePriority:00000000 $t
     /tmp/ccfiAGGE.s:248    .text.NVIC_EncodePriority:00000000 NVIC_EncodePriority
     /tmp/ccfiAGGE.s:310    .text.NVIC_DecodePriority:00000000 $t
     /tmp/ccfiAGGE.s:315    .text.NVIC_DecodePriority:00000000 NVIC_DecodePriority
     /tmp/ccfiAGGE.s:384    .text.__NVIC_SystemReset:00000000 $t
     /tmp/ccfiAGGE.s:389    .text.__NVIC_SystemReset:00000000 __NVIC_SystemReset
     /tmp/ccfiAGGE.s:450    .text.__NVIC_SystemReset:0000001c $d
     /tmp/ccfiAGGE.s:456    .text.HAL_NVIC_SetPriorityGrouping:00000000 $t
     /tmp/ccfiAGGE.s:462    .text.HAL_NVIC_SetPriorityGrouping:00000000 HAL_NVIC_SetPriorityGrouping
     /tmp/ccfiAGGE.s:516    .text.HAL_NVIC_SetPriorityGrouping:00000020 $d
     /tmp/ccfiAGGE.s:521    .text.HAL_NVIC_SetPriority:00000000 $t
     /tmp/ccfiAGGE.s:527    .text.HAL_NVIC_SetPriority:00000000 HAL_NVIC_SetPriority
     /tmp/ccfiAGGE.s:577    .text.HAL_NVIC_SetPriority:0000001c $d
     /tmp/ccfiAGGE.s:582    .text.HAL_NVIC_EnableIRQ:00000000 $t
     /tmp/ccfiAGGE.s:588    .text.HAL_NVIC_EnableIRQ:00000000 HAL_NVIC_EnableIRQ
     /tmp/ccfiAGGE.s:611    .text.HAL_NVIC_DisableIRQ:00000000 $t
     /tmp/ccfiAGGE.s:617    .text.HAL_NVIC_DisableIRQ:00000000 HAL_NVIC_DisableIRQ
     /tmp/ccfiAGGE.s:640    .text.HAL_NVIC_SystemReset:00000000 $t
     /tmp/ccfiAGGE.s:646    .text.HAL_NVIC_SystemReset:00000000 HAL_NVIC_SystemReset
     /tmp/ccfiAGGE.s:665    .text.HAL_SYSTICK_Config:00000000 $t
     /tmp/ccfiAGGE.s:671    .text.HAL_SYSTICK_Config:00000000 HAL_SYSTICK_Config
     /tmp/ccfiAGGE.s:736    .text.HAL_SYSTICK_Config:00000024 $d
     /tmp/ccfiAGGE.s:741    .text.HAL_MPU_Disable:00000000 $t
     /tmp/ccfiAGGE.s:747    .text.HAL_MPU_Disable:00000000 HAL_MPU_Disable
     /tmp/ccfiAGGE.s:784    .text.HAL_MPU_Disable:00000018 $d
     /tmp/ccfiAGGE.s:789    .text.HAL_MPU_Enable:00000000 $t
     /tmp/ccfiAGGE.s:795    .text.HAL_MPU_Enable:00000000 HAL_MPU_Enable
     /tmp/ccfiAGGE.s:849    .text.HAL_MPU_Enable:0000001c $d
     /tmp/ccfiAGGE.s:854    .text.HAL_MPU_EnableRegion:00000000 $t
     /tmp/ccfiAGGE.s:860    .text.HAL_MPU_EnableRegion:00000000 HAL_MPU_EnableRegion
     /tmp/ccfiAGGE.s:882    .text.HAL_MPU_EnableRegion:00000014 $d
     /tmp/ccfiAGGE.s:887    .text.HAL_MPU_DisableRegion:00000000 $t
     /tmp/ccfiAGGE.s:893    .text.HAL_MPU_DisableRegion:00000000 HAL_MPU_DisableRegion
     /tmp/ccfiAGGE.s:915    .text.HAL_MPU_DisableRegion:00000014 $d
     /tmp/ccfiAGGE.s:920    .text.HAL_MPU_ConfigRegion:00000000 $t
     /tmp/ccfiAGGE.s:926    .text.HAL_MPU_ConfigRegion:00000000 HAL_MPU_ConfigRegion
     /tmp/ccfiAGGE.s:1003   .text.HAL_MPU_ConfigRegion:00000054 $d
     /tmp/ccfiAGGE.s:1008   .text.HAL_CORTEX_ClearEvent:00000000 $t
     /tmp/ccfiAGGE.s:1014   .text.HAL_CORTEX_ClearEvent:00000000 HAL_CORTEX_ClearEvent
     /tmp/ccfiAGGE.s:1038   .text.HAL_NVIC_GetPriorityGrouping:00000000 $t
     /tmp/ccfiAGGE.s:1044   .text.HAL_NVIC_GetPriorityGrouping:00000000 HAL_NVIC_GetPriorityGrouping
     /tmp/ccfiAGGE.s:1068   .text.HAL_NVIC_GetPriorityGrouping:0000000c $d
     /tmp/ccfiAGGE.s:1073   .text.HAL_NVIC_GetPriority:00000000 $t
ARM GAS  /tmp/ccfiAGGE.s 			page 78


     /tmp/ccfiAGGE.s:1079   .text.HAL_NVIC_GetPriority:00000000 HAL_NVIC_GetPriority
     /tmp/ccfiAGGE.s:1114   .text.HAL_NVIC_SetPendingIRQ:00000000 $t
     /tmp/ccfiAGGE.s:1120   .text.HAL_NVIC_SetPendingIRQ:00000000 HAL_NVIC_SetPendingIRQ
     /tmp/ccfiAGGE.s:1162   .text.HAL_NVIC_SetPendingIRQ:00000018 $d
     /tmp/ccfiAGGE.s:1167   .text.HAL_NVIC_GetPendingIRQ:00000000 $t
     /tmp/ccfiAGGE.s:1173   .text.HAL_NVIC_GetPendingIRQ:00000000 HAL_NVIC_GetPendingIRQ
     /tmp/ccfiAGGE.s:1219   .text.HAL_NVIC_GetPendingIRQ:00000020 $d
     /tmp/ccfiAGGE.s:1224   .text.HAL_NVIC_ClearPendingIRQ:00000000 $t
     /tmp/ccfiAGGE.s:1230   .text.HAL_NVIC_ClearPendingIRQ:00000000 HAL_NVIC_ClearPendingIRQ
     /tmp/ccfiAGGE.s:1272   .text.HAL_NVIC_ClearPendingIRQ:00000018 $d
     /tmp/ccfiAGGE.s:1277   .text.HAL_NVIC_GetActive:00000000 $t
     /tmp/ccfiAGGE.s:1283   .text.HAL_NVIC_GetActive:00000000 HAL_NVIC_GetActive
     /tmp/ccfiAGGE.s:1329   .text.HAL_NVIC_GetActive:00000020 $d
     /tmp/ccfiAGGE.s:1334   .text.HAL_SYSTICK_CLKSourceConfig:00000000 $t
     /tmp/ccfiAGGE.s:1340   .text.HAL_SYSTICK_CLKSourceConfig:00000000 HAL_SYSTICK_CLKSourceConfig
     /tmp/ccfiAGGE.s:1375   .text.HAL_SYSTICK_Callback:00000000 $t
     /tmp/ccfiAGGE.s:1381   .text.HAL_SYSTICK_Callback:00000000 HAL_SYSTICK_Callback
     /tmp/ccfiAGGE.s:1394   .text.HAL_SYSTICK_IRQHandler:00000000 $t
     /tmp/ccfiAGGE.s:1400   .text.HAL_SYSTICK_IRQHandler:00000000 HAL_SYSTICK_IRQHandler

NO UNDEFINED SYMBOLS
