724 lines
32 KiB
C
724 lines
32 KiB
C
/* Blackfin on-chip ROM API
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*
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* Copyright 2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef __BFROM_H__
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#define __BFROM_H__
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#include <stdint.h>
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/* Possible syscontrol action flags */
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#define SYSCTRL_READ 0x00000000 /* read registers */
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#define SYSCTRL_WRITE 0x00000001 /* write registers */
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#define SYSCTRL_SYSRESET 0x00000002 /* perform system reset */
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#define SYSCTRL_CORERESET 0x00000004 /* perform core reset */
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#define SYSCTRL_SOFTRESET 0x00000006 /* perform core and system reset */
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#define SYSCTRL_VRCTL 0x00000010 /* read/write VR_CTL register */
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#define SYSCTRL_EXTVOLTAGE 0x00000020 /* VDDINT supplied externally */
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#define SYSCTRL_INTVOLTAGE 0x00000000 /* VDDINT generated by on-chip regulator */
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#define SYSCTRL_OTPVOLTAGE 0x00000040 /* For Factory Purposes Only */
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#define SYSCTRL_PLLCTL 0x00000100 /* read/write PLL_CTL register */
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#define SYSCTRL_PLLDIV 0x00000200 /* read/write PLL_DIV register */
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#define SYSCTRL_LOCKCNT 0x00000400 /* read/write PLL_LOCKCNT register */
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#define SYSCTRL_PLLSTAT 0x00000800 /* read/write PLL_STAT register */
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#define SYSCTRL_COLDBOOT 0x40000000 /* when called at cold boot */
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#define SYSCTRL_PREBOOT 0x80000000 /* when called from preboot */
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typedef struct ADI_SYSCTRL_VALUES {
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uint16_t uwVrCtl;
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uint16_t uwPllCtl;
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uint16_t uwPllDiv;
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uint16_t uwPllLockCnt;
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uint16_t uwPllStat;
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} ADI_SYSCTRL_VALUES;
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static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)0xEF000038;
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/* We need a dedicated function since we need to screw with the stack pointer
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* when resetting. The on-chip ROM will save/restore registers on the stack
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* when doing a system reset, so the stack cannot be outside of the chip.
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*/
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__attribute__((__noreturn__))
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static inline void bfrom_SoftReset(void *new_stack)
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{
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while (1)
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/*
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* We don't declare the SP as clobbered on purpose, since
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* it confuses the heck out of the compiler, and this function
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* never returns
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*/
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__asm__ __volatile__(
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"sp = %[stack];"
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"jump (%[bfrom_syscontrol]);"
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: : [bfrom_syscontrol] "p"(bfrom_SysControl),
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"q0"(SYSCTRL_SOFTRESET),
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"q1"(0),
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"q2"(NULL),
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[stack] "p"(new_stack)
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);
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}
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/* OTP Functions */
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static uint32_t (* const bfrom_OtpCommand)(uint32_t command, uint32_t value) = (void *)0xEF000018;
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static uint32_t (* const bfrom_OtpRead)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001A;
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static uint32_t (* const bfrom_OtpWrite)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001C;
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/* otp command: defines for "command" */
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#define OTP_INIT 0x00000001
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#define OTP_CLOSE 0x00000002
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/* otp read/write: defines for "flags" */
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#define OTP_LOWER_HALF 0x00000000 /* select upper/lower 64-bit half (bit 0) */
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#define OTP_UPPER_HALF 0x00000001
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#define OTP_NO_ECC 0x00000010 /* do not use ECC */
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#define OTP_LOCK 0x00000020 /* sets page protection bit for page */
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#define OTP_CHECK_FOR_PREV_WRITE 0x00000080
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/* ******************************************************************************************* */
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/* */
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/* Return Codes for OtpCommand, OtpRead and OtpWrite() routines */
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/* */
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/* ******************************************************************************************* */
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/* Error codes */
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#define OTP_SUCCESS 0x0000
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/* Error Bits */
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#define OTP_MASTER_ERROR 0
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#define OTP_WRITE_ERROR 1
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#define OTP_READ_ERROR 2
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#define OTP_ACC_VIO_ERROR 3
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#define OTP_DATA_MULT_ERROR 4
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#define OTP_ECC_MULT_ERROR 5
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#define OTP_PREV_WR_ERROR 6
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#define OTP_SB_DEFECT_ERROR 7
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/* Warning Bits */
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#define OTP_DATA_SB_WARN 8
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#define OTP_ECC_SB_WARN 9
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/* ******************************************************************************************* */
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/* */
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/* Boot block header's bit fields */
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/* */
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/* ******************************************************************************************* */
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#define HDRSGN 0xFF000000
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#define HDRCHK 0x00FF0000
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#define DMACODE 0x0000000F
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/* ******************************************************************************************* */
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/* */
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/* Boot Flags (part of block header's block code field) */
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/* */
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/* ******************************************************************************************* */
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#define BFLAG_FINAL 0x00008000 /* final block in stream */
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#define BFLAG_FIRST 0x00004000 /* first block in stream */
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#define BFLAG_INDIRECT 0x00002000 /* load data via intermediate buffer */
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#define BFLAG_IGNORE 0x00001000 /* ignore block payload */
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#define BFLAG_INIT 0x00000800 /* call initcode routine */
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#define BFLAG_CALLBACK 0x00000400 /* call callback routine */
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#define BFLAG_QUICKBOOT 0x00000200 /* boot block only when BFLAG_WAKEUP=0 */
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#define BFLAG_FILL 0x00000100 /* fill memory with 32-bit argument value */
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#define BFLAG_AUX 0x00000020 /* load auxiliary header -- reserved */
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#define BFLAG_SAVE 0x00000010 /* save block on power down -- reserved */
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/* ******************************************************************************************* */
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/* */
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/* Boot Flags (global flags for pFlag word) */
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/* */
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/* ******************************************************************************************* */
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#define BFLAG_NORESTORE 0x80000000 /* do not restore MMR register when done */
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#define BFLAG_RESET 0x40000000 /* issue system reset when done */
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#define BFLAG_RETURN 0x20000000 /* issue RTS instead of jumping to EVT1 vector */
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#define BFLAG_NEXTDXE 0x10000000 /* parse stream via Next DXE pointer */
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#define BFLAG_WAKEUP 0x08000000 /* WURESET bit was a '1', enable quickboot */
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#define BFLAG_SLAVE 0x04000000 /* boot mode is a slave mode */
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#define BFLAG_PERIPHERAL 0x02000000 /* boot mode is a peripheral mode */
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#define BFLAG_NOAUTO 0x01000000 /* skip automatic device detection */
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#define BFLAG_ALTERNATE 0x00800000 /* use alternate boot source */
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#define BFLAG_FASTREAD 0x00400000 /* use 0xB command in SPI master mode */
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#define BFLAG_TYPE 0x00100000 /* device type (number of address bytes) */
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#define BFLAG_TYPE1 0x00000000 /* device type (1 SPI/TWI address bytes, Small Page NAND Flash) */
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#define BFLAG_TYPE2 0x00100000 /* device type (2 SPI/TWI address bytes, Large Page NAND Flash) */
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#define BFLAG_TYPE3 0x00200000 /* device type (3 SPI/TWI address bytes, NAND reserved) */
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#define BFLAG_TYPE4 0x00300000 /* device type (4 SPI/TWI address bytes, NAND reserved) */
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#define BFLAG_HDRINDIRECT 0x00080000 /* boot block headers via intermediate buffer */
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#define BFLAG_HOOK 0x00040000 /* call hook routine after initialization */
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#define BFLAG_TEST 0x00020000 /* factory testing */
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/* ******************************************************************************************* */
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/* */
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/* Callback Flags */
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/* */
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/* ******************************************************************************************* */
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#define CBFLAG_FINAL 0x00000008
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#define CBFLAG_FIRST 0x00000004
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#define CBFLAG_DIRECT 0x00000001
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/* ******************************************************************************************* */
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/* */
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/* Boot ROM Jump Table Entries */
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/* */
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/* ******************************************************************************************* */
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#define BFROM_FINALINIT 0xEF000002
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#define BFROM_PDMA 0xEF000004
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#define BFROM_MDMA 0xEF000006
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#define BFROM_MEMBOOT 0xEF000008
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#define BFROM_SPIBOOT 0xEF00000A
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#define BFROM_TWIBOOT 0xEF00000C
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#define BFROM_OTPBOOT 0xEF00000E
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#define BFROM_NANDBOOT 0xEF000010
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#define BFROM_SECURE_ENTRY 0xEF000014
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#define BFROM_OTP_ECC 0xEF000016
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#define BFROM_OTP_COMMAND 0xEF000018
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#define BFROM_OTP_READ 0xEF00001A
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#define BFROM_OTP_WRITE 0xEF00001C
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#define BFROM_ECC_LUTADDR 0xEF00001E
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#define BFROM_BOOTKERNEL 0xEF000020
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#define BFROM_GETPORT 0xEF000022
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#define BFROM_NMI 0xEF000024
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#define BFROM_HWERROR 0xEF000026
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#define BFROM_EXCEPTION 0xEF000028
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#define BFROM_EMUENTRY 0xEF00002A
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#define BFROM_CRC32 0xEF000030
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#define BFROM_CRC32POLY 0xEF000032
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#define BFROM_CRC32CALLBACK 0xEF000034
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#define BFROM_CRC32INITCODE 0xEF000036
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#define BFROM_SYSCONTROL 0xEF000038
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#if defined(__ADSPBF50x__)
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#define BFROM_FLASHPROTECT 0xEF00003A
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#define BFROM_FLASHPROTECTINITCODE 0xEF00003C
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#endif
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/* ******************************************************************************************* */
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/* */
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/* Flags and Argument for BFROM_FLASHPROTECT routine */
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/* */
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/* ******************************************************************************************* */
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#if defined(__ADSPBF50x__)
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#define FLASH_LOCK_CONTROL 0x80000000 /* Controls locking of the upper byte of the FLASH_CONTROL register */
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#define FLASH_PROTECT_ENABLE 0x20000000 /* Controls the Vpp Flash Protect signal */
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#define FLASH_PROTECT_DISABLE 0x10000000 /* Controls the Vpp Flash Protect signal */
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#define FLASH_RESET_DISABLE 0x02000000 /* Controls the Flash Reset signal */
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#define FLASH_RESET_ENABLE 0x01000000 /* Controls the Flash Reset signal */
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#define FLASH_LOCKDOWN_ENABLE 0x00010000 /* Enables the block lockdown feature */
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#define FLASH_LOCKDOWN_START_BLOCK 0x000000FF /* Block number to start the lockdown */
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#define FLASH_LOCKDOWN_NUM_BLOCKS 0x0000FF00 /* Number of block to lockdown */
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#define FLASH_BLOCK_SHIFT_VAL 0x00000010 /* shift value for FLASH_LOCKDOWN_START_BLOCK to generate the byte address */
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#define FLASH_MAIN_BLOCK_SIZE 0x00010000 /* Size in bytes of a main block */
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#endif
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/* ******************************************************************************************* */
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/* */
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/* Boot ROM Data Constants with Bit Fields */
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/* */
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/* ******************************************************************************************* */
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#define BK_REVISION 0xEF000040
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#define BK_ZEROS 0xEF000048
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#define BK_ONES 0xEF00004C
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#define BK_DATECODE 0xEF000050
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#if defined (_LANGUAGE_C)
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# define pBK_REVISION ((const unsigned long *)BK_REVISION)
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# define pBK_ZEROS ((const unsigned long *)BK_ZEROS)
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# define pBK_ONES ((const unsigned long *)BK_ONES)
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# define pBK_DATECODE ((const unsigned long *)BK_DATECODE)
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#endif /* _LANGUAGE_C */
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#define BK_ID 0xFF000000
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#define BK_PROJECT 0x00FF0000
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#define BK_VERSION 0x0000FF00
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#define BK_UPDATE 0x000000FF
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#define BK_YEAR 0xFFFF0000
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#define BK_MONTH 0x0000FF00
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#define BK_DAY 0x000000FF
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/* ******************************************************************************************* */
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/* */
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/* Predefined OTP Pages to be used with bfrom_OtpRead() */
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/* */
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/* ******************************************************************************************* */
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#define FPS00 0x0004
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#define FPS01 0x0005
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#define FPS02 0x0006
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#define FPS03 0x0007
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#define FPS04 0x0008
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#define FPS05 0x0009
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#define FPS06 0x000A
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#define FPS07 0x000B
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#define FPS08 0x000C
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#define FPS09 0x000D
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#define FPS10 0x000E
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#define FPS11 0x000F
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#define CPS00 0x0010
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#define CPS01 0x0011
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#define CPS02 0x0012
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#define CPS03 0x0013
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#define CPS04 0x0014
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#define CPS05 0x0015
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#define CPS06 0x0016
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#define CPS07 0x0017
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#define PBS00 0x0018
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#define PBS01 0x0019
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#define PBS02 0x001A
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#define PBS03 0x001B
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/* ******************************************************************************************* */
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/* */
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/* Bit Fields in OTP Half Page PBS00L */
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/* */
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/* ******************************************************************************************* */
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#define OTP_VR_CTL_P 0
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#define OTP_VR_CTL_M 0x0000FFFF /* lower 32-bit word */
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#define OTP_PLL_CTL_P 16
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#define OTP_PLL_CTL_M 0xFFFF0000 /* lower 32-bit word */
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#define OTP_PLL_DIV_P 32
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#define OTP_PLL_DIV_M 0x000000FF /* upper 32-bit word */
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#define OTP_SPI_BAUD_P 40
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#define OTP_SPI_BAUD_M 0x00000700 /* upper 32-bit word */
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#define OTP_SPI_FASTREAD_P 43
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#define OTP_SPI_FASTREAD_M 0x00000800 /* upper 32-bit word */
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#define OTP_TWI_CLKDIV_P 44
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#define OTP_TWI_CLKDIV_M 0x00001000 /* upper 32-bit word */
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#define OTP_TWI_PRESCALE_P 45
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#define OTP_TWI_PRESCALE_M 0x0000E000 /* upper 32-bit word */
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#define OTP_TWI_TYPE_P 48
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#define OTP_TWI_TYPE_M 0x00030000 /* upper 32-bit word */
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#define OTP_SET_PLL_P 50
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#define OTP_SET_PLL_M 0x00040000 /* upper 32-bit word */
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#define OTP_SET_VR_P 51
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#define OTP_SET_VR_M 0x00080000 /* upper 32-bit word */
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#define OTP_RESETOUT_HWAIT_P 52
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#define OTP_RESETOUT_HWAIT_M 0x00100000 /* upper 32-bit word */
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#if defined(__ADSPBF54x__)
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#define OTP_ALTERNATE_HWAIT_P 53
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#define OTP_ALTERNATE_HWAIT_M 0x00200000 /* upper 32-bit word */
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/* bit 54 reserved */
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#elif defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
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/* bits 53 to 54 reserved */
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#endif
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#define OTP_LOAD_PBS00H_P 55
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#define OTP_LOAD_PBS00H_M 0x00800000 /* upper 32-bit word */
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#define OTP_LOAD_PBS01L_P 56
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#define OTP_LOAD_PBS01L_M 0x01000000 /* upper 32-bit word */
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#define OTP_LOAD_PBS01H_P 57
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#define OTP_LOAD_PBS01H_M 0x02000000 /* upper 32-bit word */
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#define OTP_LOAD_PBS02L_P 58
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#define OTP_LOAD_PBS02L_M 0x04000000 /* upper 32-bit word */
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#define OTP_LOAD_PBS02H_P 59
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#define OTP_LOAD_PBS02H_M 0x08000000 /* upper 32-bit word */
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#define OTP_LOAD_PBS03L_P 60
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#define OTP_LOAD_PBS03L_M 0x10000000 /* upper 32-bit word */
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#define OTP_LOAD_PBS03H_P 61
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#define OTP_LOAD_PBS03H_M 0x20000000 /* upper 32-bit word */
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#define OTP_INVALID_P 62
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#define OTP_INVALID_M 0xC0000000 /* upper 32-bit word */
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/* ******************************************************************************************* */
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/* */
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/* Bit Fields in OTP Half Page PBS00H */
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/* */
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/* ******************************************************************************************* */
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#define OTP_EBIU_AMBCTL_P 0
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#define OTP_EBIU_AMBCTL_M 0x0000FFFF /* lower 32-bit word */
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#if defined(__ADSPBF54x__)
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#define OTP_EBIU_FCTL_P 16
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#define OTP_EBIU_FCTL_M 0xFFFF0000 /* lower 32-bit word */
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#define OTP_EBIU_MODE_P 32
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#define OTP_EBIU_MODE_M 0x000000FF /* upper 32-bit word */
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#elif defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
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/* bits 16 to 39 reserved */
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#endif
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#define OTP_EBIU_AMG_P 40
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#define OTP_EBIU_AMG_M 0x00000F00 /* upper 32-bit word */
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#if defined(__ADSPBF54x__)
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#define OTP_EBIU_DEVSEQ_P 44
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#define OTP_EBIU_DEVSEQ_M 0x0000F000 /* upper 32-bit word */
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#define OTP_EBIU_DEVCFG_P 48
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#define OTP_EBIU_DEVCFG_M 0xFFFF0000 /* upper 32-bit word */
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#elif defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
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/* bits 16 to 63 reserved */
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#endif
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/* ******************************************************************************************* */
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/* */
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/* Bit Fields in OTP Half Page PBS01L */
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/* */
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/* ******************************************************************************************* */
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/* bits 0 to 63 reserved */
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/* ******************************************************************************************* */
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/* */
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/* Bit Fields in OTP Half Page PBS01H */
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/* */
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/* ******************************************************************************************* */
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#define OTP_BMODE00_DIS_P 0
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#define OTP_BMODE00_DIS_M 0x00000001 /* lower 32-bit word */
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#define OTP_BMODE01_DIS_P 1
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#define OTP_BMODE01_DIS_M 0x00000002 /* lower 32-bit word */
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#define OTP_BMODE02_DIS_P 2
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#define OTP_BMODE02_DIS_M 0x00000004 /* lower 32-bit word */
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#define OTP_BMODE03_DIS_P 3
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#define OTP_BMODE03_DIS_M 0x00000008 /* lower 32-bit word */
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#define OTP_BMODE04_DIS_P 4
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#define OTP_BMODE04_DIS_M 0x00000010 /* lower 32-bit word */
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#define OTP_BMODE05_DIS_P 5
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#define OTP_BMODE05_DIS_M 0x00000020 /* lower 32-bit word */
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#define OTP_BMODE06_DIS_P 6
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#define OTP_BMODE06_DIS_M 0x00000040 /* lower 32-bit word */
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#define OTP_BMODE07_DIS_P 7
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#define OTP_BMODE07_DIS_M 0x00000080 /* lower 32-bit word */
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#define OTP_BMODE08_DIS_P 8
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#define OTP_BMODE08_DIS_M 0x00000100 /* lower 32-bit word */
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#define OTP_BMODE09_DIS_P 9
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#define OTP_BMODE09_DIS_M 0x00000200 /* lower 32-bit word */
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#define OTP_BMODE10_DIS_P 10
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#define OTP_BMODE10_DIS_M 0x00000400 /* lower 32-bit word */
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#define OTP_BMODE11_DIS_P 11
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#define OTP_BMODE11_DIS_M 0x00000800 /* lower 32-bit word */
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#define OTP_BMODE12_DIS_P 12
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#define OTP_BMODE12_DIS_M 0x00001000 /* lower 32-bit word */
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#define OTP_BMODE13_DIS_P 13
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#define OTP_BMODE13_DIS_M 0x00002000 /* lower 32-bit word */
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#define OTP_BMODE14_DIS_P 14
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#define OTP_BMODE14_DIS_M 0x00004000 /* lower 32-bit word */
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#define OTP_BMODE15_DIS_P 15
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#define OTP_BMODE15_DIS_M 0x00008000 /* lower 32-bit word */
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#define OTP_NFC_CTL_P 16
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#define OTP_NFC_CTL_M 0x00FF0000 /* lower 32-bit word */
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#define OTP_START_PAGE_P 24
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#define OTP_START_PAGE_M 0xFF000000 /* lower 32-bit word */
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/* bits 32 to 63 reserved */
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/* ******************************************************************************************* */
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/* */
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/* Bit Fields in OTP Half Page PBS02L */
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/* */
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/* ******************************************************************************************* */
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#if defined(__ADSPBF54x__)
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#define OTP_EBIU_DDRCTL0_P 0
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#define OTP_EBIU_DDRCTL0_M 0xFFFFFFFF /* lower 32-bit word */
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#define OTP_EBIU_DDRCTL1_P 32
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#define OTP_EBIU_DDRCTL1_M 0xFFFFFFFF /* upper 32-bit word */
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#elif defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
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#define OTP_EBIU_SDGCTL_P 0
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#define OTP_EBIU_SDGCTL_M 0xFFFFFFFF /* lower 32-bit word */
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#define OTP_EBIU_SDBCTL_P 32
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#define OTP_EBIU_SDBCTL_M 0x0000FFFF /* upper 32-bit word */
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#define OTP_EBIU_SDRCC_P 48
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#define OTP_EBIU_SDRCC_M 0x0FFF0000 /* upper 32-bit word */
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/* bits 60 to 62 reserved */
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#define OTP_EBIU_POWERON_DUMMY_WRITE_P 63
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#define OTP_EBIU_POWERON_DUMMY_WRITE_M 0x80000000 /* upper 32-bit word */
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#endif
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/* ******************************************************************************************* */
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/* */
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/* Bit Fields in OTP Half Page PBS02H */
|
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/* */
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/* ******************************************************************************************* */
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#if defined(__ADSPBF54x__)
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#define OTP_EBIU_DDRCTL2L_P 0
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#define OTP_EBIU_DDRCTL2L_M 0x0000FFFF /* lower 32-bit word */
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#define OTP_EBIU_DDRCTL3L_P 16
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#define OTP_EBIU_DDRCTL3L_M 0xFFFF0000 /* lower 32-bit word */
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#define OTP_EBIU_DDRQUEL_P 32
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#define OTP_EBIU_DDRQUEL_M 0x0000FFFF /* upper 32-bit word */
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|
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/* bits 48 to 63 reserved */
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#elif defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
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/* bits 0 to 63 reserved */
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#endif
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|
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/* ******************************************************************************************* */
|
|
/* */
|
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/* Bit Fields in OTP Half Page PBS03L */
|
|
/* */
|
|
/* ******************************************************************************************* */
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|
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/* bits 0 to 63 reserved */
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|
|
|
|
|
/* ******************************************************************************************* */
|
|
/* */
|
|
/* Bit Fields in OTP Half Page PBS03H */
|
|
/* */
|
|
/* ******************************************************************************************* */
|
|
|
|
|
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/* bits 0 to 63 reserved */
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|
|
|
|
|
/* ******************************************************************************************* */
|
|
/* */
|
|
/* Macros to be used along with _P versions of above bit fields */
|
|
/* */
|
|
/* ******************************************************************************************* */
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|
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#define OTP_OFFSET(x) (((x)>>5)<<2)
|
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#define OTP_BITPOS(x) ((x)&0x1F)
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|
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|
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/* ******************************************************************************************* */
|
|
/* */
|
|
/* Block Cipher Modes of Operation */
|
|
/* */
|
|
/* ******************************************************************************************* */
|
|
|
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|
|
#define BLOCK_CIPHER_MODE_ECB 0
|
|
#define BLOCK_CIPHER_MODE_CBC 1
|
|
#define BLOCK_CIPHER_MODE_OFB 2
|
|
#define BLOCK_CIPHER_MODE_CTR 3
|
|
|
|
|
|
|
|
|
|
/* ******************************************************************************************* */
|
|
/* */
|
|
/* Flags for AesInit() routines */
|
|
/* */
|
|
/* ******************************************************************************************* */
|
|
|
|
|
|
#define AES_ENCRYPTION (0x01)
|
|
#define AES_DECRYPTION (0x02)
|
|
#define AES_BOTH (AES_ENCRYPTION | AES_DECRYPTION)
|
|
|
|
|
|
|
|
/* ******************************************************************************************* */
|
|
/* */
|
|
/* Return Codes for AES routines */
|
|
/* */
|
|
/* ******************************************************************************************* */
|
|
|
|
|
|
#define AES_SUCCESS 0
|
|
#define AES_INVALID_KEY_SIZE -1
|
|
#define AES_INVALID_MODE -2
|
|
|
|
|
|
|
|
/* ******************************************************************************************* */
|
|
/* */
|
|
/* Size definitions used in SHA-1 */
|
|
/* */
|
|
/* ******************************************************************************************* */
|
|
|
|
|
|
#define SHA1_SCRATCH_BUFFER_SIZE 184
|
|
#define SHA1_HASH_SIZE 20
|
|
|
|
|
|
|
|
/* ******************************************************************************************* */
|
|
/* */
|
|
/* Instruction ROM Jump Table Entries */
|
|
/* */
|
|
/* ******************************************************************************************* */
|
|
|
|
#if defined(__ADSPBF54x__)
|
|
|
|
#if defined(__SILICON_REVISION__) && (__SILICON_REVISION__==0x1)
|
|
|
|
#define BFROM_ARC4_INIT 0xFFA14018
|
|
#define BFROM_ARC4_CIPHER 0xFFA1401C
|
|
|
|
#define BFROM_AES_CIPHER 0xFFA14020
|
|
#define BFROM_AES_INV_CIPHER 0xFFA14024
|
|
#define BFROM_AES_INIT 0xFFA14028
|
|
#define BFROM_AES_KEYEXP 0xFFA1402C
|
|
#define BFROM_AES_INV_KEYEXP 0xFFA14030
|
|
|
|
#define BFROM_SHA1_INIT 0xFFA14860
|
|
#define BFROM_SHA1_HASH 0xFFA14B6C
|
|
|
|
#elif defined(__SILICON_REVISION__) && ((__SILICON_REVISION__==0x2) || (__SILICON_REVISION__==0x3) || (__SILICON_REVISION__==0x4))
|
|
|
|
#define BFROM_ARC4_INIT 0xFFA14018
|
|
#define BFROM_ARC4_CIPHER 0xFFA1401C
|
|
|
|
#define BFROM_AES_CIPHER 0xFFA14020
|
|
#define BFROM_AES_INV_CIPHER 0xFFA14024
|
|
#define BFROM_AES_INIT 0xFFA14028
|
|
#define BFROM_AES_KEYEXP 0xFFA1402C
|
|
#define BFROM_AES_INV_KEYEXP 0xFFA14030
|
|
|
|
#define BFROM_SHA1_INIT 0xFFA14990
|
|
#define BFROM_SHA1_HASH 0xFFA14C9C
|
|
|
|
#else
|
|
|
|
#define BFROM_ARC4_INIT __arc4_init
|
|
#define BFROM_ARC4_CIPHER __arc4_cipher
|
|
|
|
#define BFROM_AES_CIPHER __aes_cipher
|
|
#define BFROM_AES_INV_CIPHER __aes_inv_cipher
|
|
#define BFROM_AES_INIT __aes_init
|
|
#define BFROM_AES_KEYEXP __aes_keyexp
|
|
#define BFROM_AES_INV_KEYEXP __aes_inv_keyexp
|
|
|
|
#define BFROM_SHA1_INIT __sha1_init
|
|
#define BFROM_SHA1_HASH __sha1_hash
|
|
|
|
#endif /* __SILICON_REVISION__ */
|
|
|
|
#elif defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
|
|
|
|
#if defined(__SILICON_REVISION__) && (__SILICON_REVISION__==0x1)
|
|
|
|
#define BFROM_SHA1_INIT 0xEF001748
|
|
#define BFROM_SHA1_HASH 0xEF001A54
|
|
|
|
#elif defined(__SILICON_REVISION__) && (__SILICON_REVISION__==0x2)
|
|
|
|
#define BFROM_SHA1_INIT 0xEF001878
|
|
#define BFROM_SHA1_HASH 0xEF001B84
|
|
|
|
#else
|
|
|
|
#define BFROM_SHA1_INIT __sha1_init
|
|
#define BFROM_SHA1_HASH __sha1_hash
|
|
|
|
#endif /* __SILICON_REVISION__ */
|
|
|
|
#elif defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
|
|
|
|
#if defined(__SILICON_REVISION__) && (__SILICON_REVISION__==0x0)
|
|
|
|
#define BFROM_SHA1_INIT 0xEF001748
|
|
#define BFROM_SHA1_HASH 0xEF001A54
|
|
|
|
#elif defined(__SILICON_REVISION__) && ((__SILICON_REVISION__==0x1) || (__SILICON_REVISION__==0x2))
|
|
|
|
#define BFROM_SHA1_INIT 0xEF001878
|
|
#define BFROM_SHA1_HASH 0xEF001B84
|
|
|
|
#else
|
|
|
|
#define BFROM_SHA1_INIT __sha1_init
|
|
#define BFROM_SHA1_HASH __sha1_hash
|
|
|
|
#endif /* __SILICON_REVISION__ */
|
|
|
|
#elif defined(__ADSPBF51x__)
|
|
|
|
#if defined(__SILICON_REVISION__) && ((__SILICON_REVISION__==0x0) || (__SILICON_REVISION__==0x1) || (__SILICON_REVISION__==0x2))
|
|
|
|
#define BFROM_SHA1_INIT 0xEF001878
|
|
#define BFROM_SHA1_HASH 0xEF001B84
|
|
|
|
#else
|
|
|
|
#define BFROM_SHA1_INIT __sha1_init
|
|
#define BFROM_SHA1_HASH __sha1_hash
|
|
|
|
#endif /* __SILICON_REVISION__ */
|
|
|
|
#endif /* __ADSPBF5xx__ */
|
|
|
|
|
|
#endif
|