ChTheo/E502_ADC_BFfirmware
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ChTheo
2025-06-27 15:12:44 +03:00
commit c73ead2643
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build/release/.dep/l502-bf_basiccrt.o.d
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build/release/objs/l502-bf_basiccrt.o: gcc/l502-bf_basiccrt.s \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/platform.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/_adi_platform.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/defBF523.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/def_LPBlackfin.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/defBF52x_base.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cplb.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/anomaly_macros_rtl.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/defBF533.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/defBF532.h
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/platform.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/_adi_platform.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/defBF523.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/def_LPBlackfin.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/defBF52x_base.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cplb.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/anomaly_macros_rtl.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/defBF533.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/defBF532.h:
build/release/.dep/l502_async.o.d
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build/release/objs/l502_async.o: src/l502_async.c \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/stdlib.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/ieeefp.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/_ansi.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/newlib.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/config.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/features.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/include/stddef.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/reent.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/_ansi.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/_types.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/_types.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/_default_types.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/lock.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/stdlib.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/alloca.h \
src/l502_cmd.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/stdint.h \
src/l502_bf_cmd_defs.h src/l502_global.h src/l502_fpga.h \
src/l502_fpga_regs.h src/l502_defs.h src/l502_async.h
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/stdlib.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/ieeefp.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/_ansi.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/newlib.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/config.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/features.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/include/stddef.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/reent.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/_ansi.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/_types.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/_types.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/_default_types.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/lock.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/stdlib.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/alloca.h:
src/l502_cmd.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/stdint.h:
src/l502_bf_cmd_defs.h:
src/l502_global.h:
src/l502_fpga.h:
src/l502_fpga_regs.h:
src/l502_defs.h:
src/l502_async.h:
build/release/.dep/l502_cmd.o.d
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build/release/objs/l502_cmd.o: src/l502_cmd.c src/l502_global.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/stdint.h \
src/l502_bf_cmd_defs.h src/l502_cmd.h src/l502_stream.h \
src/l502_params.h src/l502_defs.h src/l502_user_process.h \
src/l502_async.h src/l502_sport_tx.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/string.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/_ansi.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/newlib.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/config.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/ieeefp.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/features.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/reent.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/_ansi.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/_types.h \
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/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/defBF523.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/def_LPBlackfin.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/defBF52x_base.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cdef_LPBlackfin.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cdefBF52x_base.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/exception.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/ccblkfn.h \
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/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/stdlib.h \
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/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/anomaly_macros_rtl.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/mc_typedef.h \
src/l502_fpga.h src/l502_fpga_regs.h
src/l502_global.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/stdint.h:
src/l502_bf_cmd_defs.h:
src/l502_cmd.h:
src/l502_stream.h:
src/l502_params.h:
src/l502_defs.h:
src/l502_user_process.h:
src/l502_async.h:
src/l502_sport_tx.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/string.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/_ansi.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/newlib.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/config.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/ieeefp.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/features.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/reent.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/_ansi.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/_types.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/_types.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/_default_types.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/lock.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/include/stddef.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/string.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cdefBF523.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/defBF523.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/def_LPBlackfin.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/defBF52x_base.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cdef_LPBlackfin.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cdefBF52x_base.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/exception.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/ccblkfn.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/stdlib.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/stdlib.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/alloca.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/builtins.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/anomaly_macros_rtl.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/mc_typedef.h:
src/l502_fpga.h:
src/l502_fpga_regs.h:
build/release/.dep/l502_fpga.o.d
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@@ -0,0 +1,28 @@
build/release/objs/l502_fpga.o: src/l502_fpga.c \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cdefBF523.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/defBF523.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/def_LPBlackfin.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/defBF52x_base.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cdef_LPBlackfin.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cdefBF52x_base.h \
src/l502_fpga.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/stdint.h \
src/l502_fpga_regs.h
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cdefBF523.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/defBF523.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/def_LPBlackfin.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/defBF52x_base.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cdef_LPBlackfin.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cdefBF52x_base.h:
src/l502_fpga.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/stdint.h:
src/l502_fpga_regs.h:
build/release/.dep/l502_hdma.o.d
+91
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@@ -0,0 +1,91 @@
build/release/objs/l502_hdma.o: src/l502_hdma.c src/l502_global.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/stdint.h \
src/l502_bf_cmd_defs.h src/l502_cdefs.h src/l502_cmd.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cdefBF523.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/defBF523.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/def_LPBlackfin.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/defBF52x_base.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cdef_LPBlackfin.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cdefBF52x_base.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/exception.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/ccblkfn.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/stdlib.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/ieeefp.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/_ansi.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/newlib.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/config.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/features.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/include/stddef.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/reent.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/_ansi.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/_types.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/_types.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/_default_types.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/lock.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/stdlib.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/alloca.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/builtins.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/anomaly_macros_rtl.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/mc_typedef.h
src/l502_global.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/stdint.h:
src/l502_bf_cmd_defs.h:
src/l502_cdefs.h:
src/l502_cmd.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cdefBF523.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/defBF523.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/def_LPBlackfin.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/defBF52x_base.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cdef_LPBlackfin.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cdefBF52x_base.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/exception.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/ccblkfn.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/stdlib.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/ieeefp.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/_ansi.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/newlib.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/config.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/features.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/include/stddef.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/reent.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/_ansi.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/_types.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/_types.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/_default_types.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/lock.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/stdlib.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/alloca.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/builtins.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/anomaly_macros_rtl.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/mc_typedef.h:
build/release/.dep/l502_init.o.d
+94
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@@ -0,0 +1,94 @@
build/release/objs/l502_init.o: src/l502_init.c \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cdefBF523.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/defBF523.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/def_LPBlackfin.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/defBF52x_base.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cdef_LPBlackfin.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cdefBF52x_base.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/ccblkfn.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/stdlib.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/machine/ieeefp.h \
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/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/newlib.h \
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/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/include/stddef.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/reent.h \
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/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/lock.h \
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/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/sys/mc_typedef.h \
gcc/bfrom.h \
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/stdint.h \
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src/l502_cdefs.h src/l502_fpga.h src/l502_fpga_regs.h src/l502_hdma.h
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cdefBF523.h:
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/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/def_LPBlackfin.h:
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/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/cdef_LPBlackfin.h:
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/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/ccblkfn.h:
/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/stdlib.h:
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/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib/gcc/bfin-elf/4.3.5/../../../../bfin-elf/include/_ansi.h:
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gcc/bfrom.h:
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src/l502_cdefs.h:
src/l502_fpga.h:
src/l502_fpga_regs.h:
src/l502_hdma.h:
build/release/.dep/l502_params.o.d
+68
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build/release/objs/l502_params.o: src/l502_params.c \
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+99
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build/release/objs/l502_sport_tx.o: src/l502_sport_tx.c \
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src/l502_stream.h
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+112
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build/release/objs/l502_stream.o: src/l502_stream.c \
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src/l502_sport_rx.h gcc/l502_sdram_noinit.h
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params_set_din_freq_div build/release/objs/l502_params.o
build/release/objs/l502_cmd.o
params_set_lch build/release/objs/l502_params.o
build/release/objs/l502_cmd.o
params_set_lch_cnt build/release/objs/l502_params.o
build/release/objs/l502_cmd.o
params_set_ref_freq build/release/objs/l502_params.o
build/release/objs/l502_cmd.o
params_set_sync_mode build/release/objs/l502_params.o
build/release/objs/l502_cmd.o
params_set_sync_start_mode build/release/objs/l502_params.o
build/release/objs/l502_cmd.o
sport_in_buffer_size build/release/objs/l502_stream.o
build/release/objs/l502_cmd.o
sport_in_set_step_size build/release/objs/l502_stream.o
build/release/objs/l502_cmd.o
sport_rx_start build/release/objs/l502_stream.o
sport_rx_stop build/release/objs/l502_stream.o
sport_tx_done build/release/objs/l502_user_process.o
build/release/objs/l502_sport_tx.o
sport_tx_init build/release/objs/l502_sport_tx.o
build/release/objs/l502_stream.o
sport_tx_out_status build/release/objs/l502_sport_tx.o
build/release/objs/l502_cmd.o
sport_tx_req_rdy build/release/objs/l502_sport_tx.o
build/release/objs/l502_user_process.o
sport_tx_start_req build/release/objs/l502_sport_tx.o
build/release/objs/l502_user_process.o
sport_tx_stop build/release/objs/l502_sport_tx.o
build/release/objs/l502_stream.o
stream_disable build/release/objs/l502_stream.o
build/release/objs/l502_cmd.o
stream_enable build/release/objs/l502_stream.o
build/release/objs/l502_cmd.o
stream_in_buf_free build/release/objs/l502_stream.o
build/release/objs/l502_user_process.o
stream_out_buf_free build/release/objs/l502_stream.o
build/release/objs/l502_user_process.o
stream_out_preload build/release/objs/l502_stream.o
build/release/objs/l502_cmd.o
stream_proc build/release/objs/l502_stream.o
build/release/objs/main.o
streams_start build/release/objs/l502_stream.o
build/release/objs/l502_cmd.o
streams_stop build/release/objs/l502_stream.o
build/release/objs/l502_cmd.o
usr_cmd_process build/release/objs/l502_user_process.o
build/release/objs/l502_cmd.o
usr_in_proc_data build/release/objs/l502_user_process.o
build/release/objs/l502_stream.o
usr_out_proc_data build/release/objs/l502_user_process.o
build/release/objs/l502_stream.o
build/release/lst/l502-bf_basiccrt.lst
+354
View File
@@ -0,0 +1,354 @@
BFIN GAS /tmp/ccIa7aFy.s page 1
1 # 1 "gcc/l502-bf_basiccrt.s"
1 #include <sys/platform.h>
1 ...
0
0
1 /*
2 * Copyright (C) 2012 Analog Devices Inc. All rights reserved.
3 *
4 * Licensed under the Clear BSD license.
5 * Please see COPYING.LIBGLOSS for details.
6 */
7
8 #ifndef _PLATFORM_H
9 #define _PLATFORM_H
10 /* Generic Wrapper for platform specific header file.
11 */
12 #include <sys/_adi_platform.h>
1 /*
2 * Copyright (C) 2012 Analog Devices Inc. All rights reserved.
3 *
4 * Licensed under the Clear BSD license.
5 * Please see COPYING.LIBGLOSS for details.
6 */
7
8 /*
9 ** Include appropriate header file for platform.
10 */
11
12 #ifndef __ADI_PLATFORM_H
13 #define __ADI_PLATFORM_H
14
15 #ifndef __ASSEMBLER__
16
17 #if defined (__ADSPBF531__)
18 #include <cdefBF531.h>
19 #elif defined (__ADSPBF532__)
20 #include <cdefBF532.h>
21 #elif defined (__ADSPBF533__)
22 #include <cdefBF533.h>
23 #elif defined (__ADSPBF534__)
24 #include <cdefBF534.h>
25 #elif defined (__ADSPBF535__)
26 #include <cdefBF535.h>
27 #elif defined (__ADSPBF536__)
28 #include <cdefBF536.h>
29 #elif defined (__ADSPBF537__)
30 #include <cdefBF537.h>
31 #elif defined (__ADSPBF538__)
32 #include <cdefBF538.h>
33 #elif defined (__ADSPBF539__)
34 #include <cdefBF539.h>
35 #elif defined (__ADSPBF561__)
36 #include <cdefBF561.h>
37 #elif defined (__AD6531__)
38 #include <cdefAD6531.h>
39 #elif defined (__AD6532__)
40 #include <cdefAD6532.h>
BFIN GAS /tmp/ccIa7aFy.s page 2
41 #elif defined (__AD6723__)
42 #include <cdefAD6723.h>
43 #elif defined (__AD6900__)
44 #include <cdefAD6900.h>
45 #elif defined (__AD6901__)
46 #include <cdefAD6901.h>
47 #elif defined (__AD6902__)
48 #include <cdefAD6902.h>
49 #elif defined (__AD6903__)
50 #include <cdefAD6903.h>
51 #elif defined (__AD6904__)
52 #include <cdefAD6904.h>
53 #elif defined (__AD6905__)
54 #include <cdefAD6905.h>
55 #elif defined (__MT6906__)
56 #include <cdefMT6906.h>
57 #elif defined (__ADSPBF504__)
58 #include <cdefBF504.h>
59 #elif defined (__ADSPBF504F__)
60 #include <cdefBF504F.h>
61 #elif defined (__ADSPBF506__) || defined (__ADSPBF506F__)
62 #include <cdefBF506F.h>
63 #elif defined (__ADSPBF512__)
64 #include <cdefBF512.h>
65 #elif defined (__ADSPBF514__)
66 #include <cdefBF514.h>
67 #elif defined (__ADSPBF516__)
68 #include <cdefBF516.h>
69 #elif defined (__ADSPBF518__)
70 #include <cdefBF518.h>
71 #elif defined (__ADSPBF522__)
72 #include <cdefBF522.h>
73 #elif defined (__ADSPBF523__)
74 #include <cdefBF523.h>
75 #elif defined (__ADSPBF524__)
76 #include <cdefBF524.h>
77 #elif defined (__ADSPBF525__)
78 #include <cdefBF525.h>
79 #elif defined (__ADSPBF526__)
80 #include <cdefBF526.h>
81 #elif defined (__ADSPBF527__)
82 #include <cdefBF527.h>
83 #elif defined (__ADSPBF542__)
84 #include <cdefBF542.h>
85 #elif defined (__ADSPBF542M__)
86 #include <cdefBF542M.h>
87 #elif defined (__ADSPBF544__)
88 #include <cdefBF544.h>
89 #elif defined (__ADSPBF544M__)
90 #include <cdefBF544M.h>
91 #elif defined (__ADSPBF547__)
92 #include <cdefBF547.h>
93 #elif defined (__ADSPBF547M__)
94 #include <cdefBF547M.h>
95 #elif defined (__ADSPBF548__)
96 #include <cdefBF548.h>
97 #elif defined (__ADSPBF548M__)
BFIN GAS /tmp/ccIa7aFy.s page 3
98 #include <cdefBF548M.h>
99 #elif defined (__ADSPBF549__)
100 #include <cdefBF549.h>
101 #elif defined (__ADSPBF549M__)
102 #include <cdefBF549M.h>
103 #elif defined (__ADSPBF592A__)
104 #include <cdefBF592-A.h>
105 #elif defined (__ADSPBF606__)
106 #include <cdefBF606.h>
107 #elif defined (__ADSPBF607__)
108 #include <cdefBF607.h>
109 #elif defined (__ADSPBF608__)
110 #include <cdefBF608.h>
111 #elif defined (__ADSPBF609__)
112 #include <cdefBF609.h>
113 #else
114 #error Processor Type Not Supported
115 #endif
116
117
118 #else
119
120 #if defined (__ADSPBF531__)
121 #include <defBF531.h>
122 #elif defined (__ADSPBF532__)
123 #include <defBF532.h>
124 #elif defined (__ADSPBF533__)
125 #include <defBF533.h>
126 #elif defined (__ADSPBF534__)
127 #include <defBF534.h>
128 #elif defined (__ADSPBF535__)
129 #include <defBF535.h>
130 #elif defined (__ADSPBF536__)
131 #include <defBF536.h>
132 #elif defined (__ADSPBF537__)
133 #include <defBF537.h>
134 #elif defined (__ADSPBF538__)
135 #include <defBF538.h>
136 #elif defined (__ADSPBF539__)
137 #include <defBF539.h>
138 #elif defined (__ADSPBF561__)
139 #include <defBF561.h>
140 #elif defined (__AD6531__)
141 #include <defAD6531.h>
142 #elif defined (__AD6532__)
143 #include <defAD6532.h>
144 #elif defined (__AD6723__)
145 #include <defAD6723.h>
146 #elif defined (__AD6900__)
147 #include <defAD6900.h>
148 #elif defined (__AD6901__)
149 #include <defAD6901.h>
150 #elif defined (__AD6902__)
151 #include <defAD6902.h>
152 #elif defined (__AD6903__)
153 #include <defAD6903.h>
154 #elif defined (__AD6904__)
BFIN GAS /tmp/ccIa7aFy.s page 4
155 #include <defAD6904.h>
156 #elif defined (__AD6905__)
157 #include <defAD6905.h>
158 #elif defined (__MT6906__)
159 #include <defMT6906.h>
160 #elif defined (__ADSPBF504__)
161 #include <defBF504.h>
162 #elif defined (__ADSPBF504F__)
163 #include <defBF504F.h>
164 #elif defined (__ADSPBF506__) || defined (__ADSPBF506F__)
165 #include <defBF506F.h>
166 #elif defined (__ADSPBF512__)
167 #include <defBF512.h>
168 #elif defined (__ADSPBF514__)
169 #include <defBF514.h>
170 #elif defined (__ADSPBF516__)
171 #include <defBF516.h>
172 #elif defined (__ADSPBF518__)
173 #include <defBF518.h>
174 #elif defined (__ADSPBF522__)
175 #include <defBF522.h>
176 #elif defined (__ADSPBF523__)
177 #include <defBF523.h>
1 /*
2 * Copyright (C) 2012 Analog Devices Inc. All rights reserved.
3 *
4 * Licensed under the Clear BSD license.
5 * Please see COPYING.LIBGLOSS for details.
6 */
7
8 /*
9 ************************************************************************************
10 **
11 ** This include file contains a list of macro "defines" to enable the programmer
12 ** to use symbolic names for register-access and bit-manipulation.
13 **
14 **/
15 #ifndef _DEF_BF523_H
16 #define _DEF_BF523_H
17
18 /* Include all Core registers and bit definitions */
19 #include <def_LPBlackfin.h>
1 /*
20
21 /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF523 */
22
23 /* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
24 #include <defBF52x_base.h>
1 /*
25
178 #elif defined (__ADSPBF524__)
13 #endif
2 #include <cplb.h>
1 /*
3 #include <sys/anomaly_macros_rtl.h>
1 /*
4 #include <defBF533.h>
BFIN GAS /tmp/ccIa7aFy.s page 5
1 /*
2 * Copyright (C) 2012 Analog Devices Inc. All rights reserved.
3 *
4 * Licensed under the Clear BSD license.
5 * Please see COPYING.LIBGLOSS for details.
6 */
7
8 /************************************************************************
9 *
10 * defBF533.h
11 *
12 ************************************************************************/
13
14 #ifndef _DEFBF533_H
15 #define _DEFBF533_H
16
17 #include <defBF532.h>
1 /*
18
5 #include <def_LPBlackfin.h>
6
7 .text;
8 .align 2;
9 .global __start;
10 .extern _main;
11 .type __start, STT_FUNC;
12 __start:
13
14 0000 0760 R7 = 0;
15 0002 073C LC0 = R7;
16 0004 1F3C LC1 = R7;
17 0006 2736 L0 = R7;
18 0008 2F36 L1 = R7;
19 000a 3736 L2 = R7;
20 000c 3F36 L3 = R7;
21 000e 10E10013 I0.L = (ITEST_COMMAND & 0xFFFF);
22 0012 50E1E0FF I0.H = (ITEST_COMMAND >> 16);
23 0016 11E10003 I1.L = (DTEST_COMMAND & 0xFFFF);
24 001a 51E1E0FF I1.H = (DTEST_COMMAND >> 16);
25 001e 0760 R7 = 0;
26 0020 079F [I0] = R7;
27 0022 0F9F [I1] = R7;
28
29 0024 2300 CSYNC;
30
31 0026 0EE1F4FF SP.L=__stack_end - 12;
32 002a 4EE1FFFF SP.H=__stack_end - 12;
33 002e 7E32 FP = SP;
34 0030 A66F SP += -12;
35
36 // Zero bss memory
37 0032 00E10000 R0.L = __bss_start;
38 0036 40E10000 R0.H = __bss_start;
39 003a 01E10000 R1.L = __bss_end;
40 003e 41E10000 R1.H = __bss_end;
41 0042 8152 R2 = R1 - R0;
42 0044 0160 R1 = 0;
BFIN GAS /tmp/ccIa7aFy.s page 6
43 0046 FFE3DDFF CALL.X _memset;
44
45
46 ///////////////from PRM/////////////////////////////////////
47 004a 08E13C20 P0.L = (EVT15 & 0xFFFF) ; /* Point to IVG15 in Event Vector Table */
48 004e 48E1E0FF P0.H = ((EVT15 >> 16) & 0xFFFF) ;
49 0052 09E17A00 P1.L = START; /* Point to start of User code */
50 0056 49E10000 P1.H = START;
51 005a 4193 [P0] = P1 ; /* Place the address of START in IVG15 of EVT */
52 005c 08E10421 P0.L = (IMASK & 0xFFFF) ;
53 0060 0091 R0 = [P0] ;
54 0062 01E10080 R1.L = (EVT_IVG15 & 0xFFFF) ;
55 0066 0856 R0 = R0 | R1 ;
56 0068 0093 [P0] = R0 ; /* Set (enable) IVG15 bit in IMASK register */
57 006a 9F00 RAISE 15 ; /* Invoke IVG15 interrupt */
58 006c 08E17800 P0.L = WAIT_HERE ;
59 0070 48E10000 P0.H = WAIT_HERE ;
60 0074 583E RETI = P0 ; /* RETI loaded with return address */
61 0076 1100 RTI ; /* Return from Reset Event */
62 WAIT_HERE : /* Wait here till IVG15 interrupt is serviced */
63 0078 0020 JUMP WAIT_HERE ;
64 START: /* IVG15 vectors here */
65 /* Enables interrupts and saves return address to stack */
66 007a 7B01 [--SP] = RETI ;
67 ///////////////from PRM/////////////////////////////////////
68
69 007c 4001 [--SP]=R0;
70 007e 4001 [--SP]=R0;
71 0080 7E32 FP = SP;
72 0082 A66F SP += -12;
73
74 0084 FFE3BEFF CALL.X _main;
75 0088 0000 NOP;
76 __end:
77 008a 2000 IDLE;
78 008c FF2F0000 JUMP __end;
BFIN GAS /tmp/ccIa7aFy.s page 7
DEFINED SYMBOLS
gcc/l502-bf_basiccrt.s:12 .text:0000000000000000 __start
gcc/l502-bf_basiccrt.s:64 .text:000000000000007a START
gcc/l502-bf_basiccrt.s:62 .text:0000000000000078 WAIT_HERE
gcc/l502-bf_basiccrt.s:76 .text:000000000000008a __end
UNDEFINED SYMBOLS
__stack_end
__bss_start
__bss_end
_memset
_main
build/release/lst/l502_async.lst
+810
View File
@@ -0,0 +1,810 @@
BFIN GAS /tmp/ccCtLplV.s page 1
1 .file "src/l502_async.c";
2 .section .debug_abbrev,"",@progbits
3 .Ldebug_abbrev0:
4 .section .debug_info,"",@progbits
5 .Ldebug_info0:
6 .section .debug_line,"",@progbits
7 .Ldebug_line0:
8 0000 FB000000 .text;
8 0200CC00
8 00000101
8 FB0E0D00
8 01010101
9 .Ltext0:
10 .align 4
11 .global _async_dout;
12 .type _async_dout, STT_FUNC;
13 _async_dout:
14 .LFB3:
15 .file 1 "src/l502_async.c"
1:src/l502_async.c **** /***************************************************************************//**
2:src/l502_async.c **** @addtogroup async_io
3:src/l502_async.c **** @{
4:src/l502_async.c **** @file l502_async.c
5:src/l502_async.c **** Ôàéë ñîäåðæèò ðåàëèçàöèþ ôóíêöèé äëÿ àñèíõðîííîãî ââîäà/âûâîäà
6:src/l502_async.c **** (ïîêà òîëüêî âûâîäà)
7:src/l502_async.c **** ******************************************************************************/
8:src/l502_async.c **** #include <stdlib.h>
9:src/l502_async.c ****
10:src/l502_async.c **** #include "l502_cmd.h"
11:src/l502_async.c **** #include "l502_global.h"
12:src/l502_async.c **** #include "l502_fpga.h"
13:src/l502_async.c **** #include "l502_defs.h"
14:src/l502_async.c **** #include "l502_async.h"
15:src/l502_async.c **** #include "l502_fpga_regs.h"
16:src/l502_async.c ****
17:src/l502_async.c ****
18:src/l502_async.c ****
19:src/l502_async.c ****
20:src/l502_async.c **** void async_dac_out(uint8_t ch, int32_t val) {
21:src/l502_async.c **** val &= 0xFFFF;
22:src/l502_async.c **** if (ch==L502_DAC_CH1) {
23:src/l502_async.c **** val |= L502_STREAM_OUT_WORD_TYPE_DAC1;
24:src/l502_async.c **** } else {
25:src/l502_async.c **** val |= L502_STREAM_OUT_WORD_TYPE_DAC2;
26:src/l502_async.c **** }
27:src/l502_async.c **** fpga_reg_write(L502_REGS_IOHARD_ASYNC_OUT, val);
28:src/l502_async.c **** }
29:src/l502_async.c ****
30:src/l502_async.c ****
31:src/l502_async.c **** void async_dout(uint32_t val, uint32_t msk) {
16 .loc 1 31 0
17 .LVL0:
18 0000 FD05 [--sp] = ( r7:7, p5:5 );
19
20 .LCFI0:
21 0002 00E80300 LINK 12;
22 .LCFI1:
BFIN GAS /tmp/ccCtLplV.s page 2
23 .loc 1 31 0
24 0006 1130 R2 = R1;
32:src/l502_async.c **** static uint32_t last_out = L502_DIGOUT_WORD_DIS_H | L502_DIGOUT_WORD_DIS_L;
33:src/l502_async.c **** if (msk != 0) {
25 .loc 1 33 0
26 0008 010C cc =R1==0;
27 000a 1518 if cc jump .L7;
34:src/l502_async.c **** val &= ~msk;
28 .loc 1 34 0
29 000c C943 R1 = ~R1;
30 .LVL1:
35:src/l502_async.c **** val |= last_out & msk;
31 .loc 1 35 0
32 000e 4DE10000 P5.H = _last_out.2066;
34:src/l502_async.c **** val &= ~msk;
33 .loc 1 34 0
34 0012 4154 R1 = R1 & R0;
35 .LVL2:
36 .loc 1 35 0
37 0014 0DE10000 P5.L = _last_out.2066;
38 0018 2891 R0 = [P5];
39 001a 0254 R0 = R2 & R0;
40 001c 0156 R0 = R1 | R0;
41 .LVL3:
42 .L2:
36:src/l502_async.c **** }
37:src/l502_async.c **** val &= 0xFFFF;
43 .loc 1 37 0
44 001e C742 R7 = R0.L (Z);
45 .LVL4:
38:src/l502_async.c ****
39:src/l502_async.c **** fpga_reg_write(L502_REGS_IOHARD_ASYNC_OUT, val);
46 .loc 1 39 0
47 0020 0F30 R1 = R7;
48 0022 20E11203 R0 = 786 (X);
49 0026 FFE3EDFF call _fpga_reg_write;
50 .LVL5:
40:src/l502_async.c **** last_out = val;
51 .loc 1 40 0
52 002a 2F93 [P5] = R7;
41:src/l502_async.c **** }
53 .loc 1 41 0
54 002c 01E80000 UNLINK;
55 0030 BD05 ( r7:7, p5:5 ) = [sp++];
56
57 .LCFI2:
58 .LVL6:
59 0032 1000 rts;
60 .LVL7:
61 .L7:
62 0034 4DE10000 P5.H = _last_out.2066;
63 0038 0DE10000 P5.L = _last_out.2066;
64 003c F12F jump.s .L2;
65 .LFE3:
66 .size _async_dout, .-_async_dout
67 003e 0000 .align 4
68 .global _async_dac_out;
BFIN GAS /tmp/ccCtLplV.s page 3
69 .type _async_dac_out, STT_FUNC;
70 _async_dac_out:
71 .LFB2:
20:src/l502_async.c **** void async_dac_out(uint8_t ch, int32_t val) {
72 .loc 1 20 0
73 .LVL8:
22:src/l502_async.c **** if (ch==L502_DAC_CH1) {
74 .loc 1 22 0
75 0040 4043 R0 = R0.B (Z);
76 .LVL9:
20:src/l502_async.c **** void async_dac_out(uint8_t ch, int32_t val) {
77 .loc 1 20 0
78 0042 00E80000 LINK 0;
79 .LCFI3:
21:src/l502_async.c **** val &= 0xFFFF;
80 .loc 1 21 0
81 0046 C942 R1 = R1.L (Z);
82 .LVL10:
22:src/l502_async.c **** if (ch==L502_DAC_CH1) {
83 .loc 1 22 0
84 0048 000C cc =R0==0;
85 004a 0818 if cc jump .L12;
25:src/l502_async.c **** val |= L502_STREAM_OUT_WORD_TYPE_DAC2;
86 .loc 1 25 0
87 004c F94A BITSET (R1, 31);
88 .LVL11:
27:src/l502_async.c **** fpga_reg_write(L502_REGS_IOHARD_ASYNC_OUT, val);
89 .loc 1 27 0
90 004e 20E11203 R0 = 786 (X);
91 .LVL12:
28:src/l502_async.c **** }
92 .loc 1 28 0
93 0052 01E80000 UNLINK;
27:src/l502_async.c **** fpga_reg_write(L502_REGS_IOHARD_ASYNC_OUT, val);
94 .loc 1 27 0
95 0056 FFE2D5FF jump.l _fpga_reg_write;
96 .LVL13:
97 .L12:
23:src/l502_async.c **** val |= L502_STREAM_OUT_WORD_TYPE_DAC1;
98 .loc 1 23 0
99 005a F14A BITSET (R1, 30);
100 .LVL14:
27:src/l502_async.c **** fpga_reg_write(L502_REGS_IOHARD_ASYNC_OUT, val);
101 .loc 1 27 0
102 005c 20E11203 R0 = 786 (X);
103 .LVL15:
28:src/l502_async.c **** }
104 .loc 1 28 0
105 0060 01E80000 UNLINK;
27:src/l502_async.c **** fpga_reg_write(L502_REGS_IOHARD_ASYNC_OUT, val);
106 .loc 1 27 0
107 0064 FFE2CEFF jump.l _fpga_reg_write;
108 .LVL16:
109 .LFE2:
110 .size _async_dac_out, .-_async_dac_out
111 .data;
112 .align 4
BFIN GAS /tmp/ccCtLplV.s page 4
113 .type _last_out.2066, @object
114 .size _last_out.2066, 4
115 _last_out.2066:
116 0000 00000300 .long 196608
117 .section .debug_frame,"",@progbits
118 .Lframe0:
119 0000 0C000000 .4byte .LECIE0-.LSCIE0
120 .LSCIE0:
121 0004 FFFFFFFF .4byte 0xffffffff
122 0008 01 .byte 0x1
123 0009 00 .string ""
124 000a 01 .uleb128 0x1
125 000b 7C .sleb128 -4
126 000c 23 .byte 0x23
127 000d 0C .byte 0xc
128 000e 0E .uleb128 0xe
129 000f 00 .uleb128 0x0
130 .align 4
131 .LECIE0:
132 .LSFDE0:
133 0010 1C000000 .4byte .LEFDE0-.LASFDE0
134 .LASFDE0:
135 0014 00000000 .4byte .Lframe0
136 0018 00000000 .4byte .LFB3
137 001c 3E000000 .4byte .LFE3-.LFB3
138 0020 42 .byte 0x4
139 .4byte .LCFI0-.LFB3
140 0021 0E .byte 0xe
141 0022 08 .uleb128 0x8
142 0023 44 .byte 0x4
143 .4byte .LCFI1-.LCFI0
144 0024 0C .byte 0xc
145 0025 0F .uleb128 0xf
146 0026 10 .uleb128 0x10
147 0027 8F .byte 0x8f
148 0028 04 .uleb128 0x4
149 0029 A3 .byte 0xa3
150 002a 03 .uleb128 0x3
151 002b 8D .byte 0x8d
152 002c 02 .uleb128 0x2
153 002d 87 .byte 0x87
154 002e 01 .uleb128 0x1
155 002f 00 .align 4
156 .LEFDE0:
157 .LSFDE2:
158 0030 14000000 .4byte .LEFDE2-.LASFDE2
159 .LASFDE2:
160 0034 00000000 .4byte .Lframe0
161 0038 40000000 .4byte .LFB2
162 003c 28000000 .4byte .LFE2-.LFB2
163 0040 46 .byte 0x4
164 .4byte .LCFI3-.LFB2
165 0041 0C .byte 0xc
166 0042 0F .uleb128 0xf
167 0043 08 .uleb128 0x8
168 0044 8F .byte 0x8f
169 0045 02 .uleb128 0x2
BFIN GAS /tmp/ccCtLplV.s page 5
170 0046 A3 .byte 0xa3
171 0047 01 .uleb128 0x1
172 .align 4
173 .LEFDE2:
174 .text;
175 .Letext0:
176 .section .debug_loc,"",@progbits
177 .Ldebug_loc0:
178 .LLST0:
179 0000 00000000 .4byte .LFB3-.Ltext0
180 0004 02000000 .4byte .LCFI0-.Ltext0
181 0008 0100 .2byte 0x1
182 000a 5E .byte 0x5e
183 000b 02000000 .4byte .LCFI0-.Ltext0
184 000f 06000000 .4byte .LCFI1-.Ltext0
185 0013 0200 .2byte 0x2
186 0015 7E .byte 0x7e
187 0016 08 .sleb128 8
188 0017 06000000 .4byte .LCFI1-.Ltext0
189 001b 3E000000 .4byte .LFE3-.Ltext0
190 001f 0200 .2byte 0x2
191 0021 7F .byte 0x7f
192 0022 10 .sleb128 16
193 0023 00000000 .4byte 0x0
194 0027 00000000 .4byte 0x0
195 .LLST1:
196 002b 00000000 .4byte .LVL0-.Ltext0
197 002f 14000000 .4byte .LVL2-.Ltext0
198 0033 0100 .2byte 0x1
199 0035 50 .byte 0x50
200 0036 14000000 .4byte .LVL2-.Ltext0
201 003a 1E000000 .4byte .LVL3-.Ltext0
202 003e 0100 .2byte 0x1
203 0040 51 .byte 0x51
204 0041 1E000000 .4byte .LVL3-.Ltext0
205 0045 20000000 .4byte .LVL4-.Ltext0
206 0049 0100 .2byte 0x1
207 004b 50 .byte 0x50
208 004c 20000000 .4byte .LVL4-.Ltext0
209 0050 32000000 .4byte .LVL6-.Ltext0
210 0054 0100 .2byte 0x1
211 0056 57 .byte 0x57
212 0057 34000000 .4byte .LVL7-.Ltext0
213 005b 3E000000 .4byte .LFE3-.Ltext0
214 005f 0100 .2byte 0x1
215 0061 50 .byte 0x50
216 0062 00000000 .4byte 0x0
217 0066 00000000 .4byte 0x0
218 .LLST2:
219 006a 00000000 .4byte .LVL0-.Ltext0
220 006e 0E000000 .4byte .LVL1-.Ltext0
221 0072 0100 .2byte 0x1
222 0074 51 .byte 0x51
223 0075 0E000000 .4byte .LVL1-.Ltext0
224 0079 2A000000 .4byte .LVL5-.Ltext0
225 007d 0100 .2byte 0x1
226 007f 52 .byte 0x52
BFIN GAS /tmp/ccCtLplV.s page 6
227 0080 34000000 .4byte .LVL7-.Ltext0
228 0084 3E000000 .4byte .LFE3-.Ltext0
229 0088 0100 .2byte 0x1
230 008a 51 .byte 0x51
231 008b 00000000 .4byte 0x0
232 008f 00000000 .4byte 0x0
233 .LLST3:
234 0093 40000000 .4byte .LFB2-.Ltext0
235 0097 46000000 .4byte .LCFI3-.Ltext0
236 009b 0100 .2byte 0x1
237 009d 5E .byte 0x5e
238 009e 46000000 .4byte .LCFI3-.Ltext0
239 00a2 68000000 .4byte .LFE2-.Ltext0
240 00a6 0200 .2byte 0x2
241 00a8 7F .byte 0x7f
242 00a9 08 .sleb128 8
243 00aa 00000000 .4byte 0x0
244 00ae 00000000 .4byte 0x0
245 .LLST4:
246 00b2 40000000 .4byte .LVL8-.Ltext0
247 00b6 52000000 .4byte .LVL12-.Ltext0
248 00ba 0100 .2byte 0x1
249 00bc 50 .byte 0x50
250 00bd 5A000000 .4byte .LVL13-.Ltext0
251 00c1 60000000 .4byte .LVL15-.Ltext0
252 00c5 0100 .2byte 0x1
253 00c7 50 .byte 0x50
254 00c8 00000000 .4byte 0x0
255 00cc 00000000 .4byte 0x0
256 .LLST5:
257 00d0 40000000 .4byte .LVL8-.Ltext0
258 00d4 5A000000 .4byte .LVL13-.Ltext0
259 00d8 0100 .2byte 0x1
260 00da 51 .byte 0x51
261 00db 5A000000 .4byte .LVL13-.Ltext0
262 00df 68000000 .4byte .LVL16-.Ltext0
263 00e3 0100 .2byte 0x1
264 00e5 51 .byte 0x51
265 00e6 00000000 .4byte 0x0
266 00ea 00000000 .4byte 0x0
267 .file 2 "/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib
268 .file 3 "src/l502_defs.h"
269 .section .debug_info
270 0000 28010000 .4byte 0x128
271 0004 0200 .2byte 0x2
272 0006 00000000 .4byte .Ldebug_abbrev0
273 000a 04 .byte 0x4
274 000b 01 .uleb128 0x1
275 000c 48010000 .4byte .LASF15
276 0010 01 .byte 0x1
277 0011 9F000000 .4byte .LASF16
278 0015 55000000 .4byte .LASF17
279 0019 00000000 .4byte .Ltext0
280 001d 68000000 .4byte .Letext0
281 0021 00000000 .4byte .Ldebug_line0
282 0025 02 .uleb128 0x2
283 0026 04 .byte 0x4
BFIN GAS /tmp/ccCtLplV.s page 7
284 0027 07 .byte 0x7
285 0028 23000000 .4byte .LASF0
286 002c 03 .uleb128 0x3
287 002d 04 .byte 0x4
288 002e 05 .byte 0x5
289 002f 696E7400 .string "int"
290 0033 02 .uleb128 0x2
291 0034 01 .byte 0x1
292 0035 06 .byte 0x6
293 0036 24010000 .4byte .LASF1
294 003a 02 .uleb128 0x2
295 003b 01 .byte 0x1
296 003c 08 .byte 0x8
297 003d B8000000 .4byte .LASF2
298 0041 02 .uleb128 0x2
299 0042 02 .byte 0x2
300 0043 05 .byte 0x5
301 0044 3E010000 .4byte .LASF3
302 0048 02 .uleb128 0x2
303 0049 02 .byte 0x2
304 004a 07 .byte 0x7
305 004b 11010000 .4byte .LASF4
306 004f 02 .uleb128 0x2
307 0050 04 .byte 0x4
308 0051 07 .byte 0x7
309 0052 0E000000 .4byte .LASF5
310 0056 02 .uleb128 0x2
311 0057 08 .byte 0x8
312 0058 05 .byte 0x5
313 0059 00000000 .4byte .LASF6
314 005d 02 .uleb128 0x2
315 005e 08 .byte 0x8
316 005f 07 .byte 0x7
317 0060 3E000000 .4byte .LASF7
318 0064 02 .uleb128 0x2
319 0065 04 .byte 0x4
320 0066 05 .byte 0x5
321 0067 F1000000 .4byte .LASF8
322 006b 04 .uleb128 0x4
323 006c 04 .byte 0x4
324 006d 07 .byte 0x7
325 006e 02 .uleb128 0x2
326 006f 01 .byte 0x1
327 0070 06 .byte 0x6
328 0071 54010000 .4byte .LASF9
329 0075 05 .uleb128 0x5
330 0076 B0000000 .4byte .LASF10
331 007a 02 .byte 0x2
332 007b 2A .byte 0x2a
333 007c 3A000000 .4byte 0x3a
334 0080 05 .uleb128 0x5
335 0081 1B000000 .4byte .LASF11
336 0085 02 .byte 0x2
337 0086 4F .byte 0x4f
338 0087 64000000 .4byte 0x64
339 008b 05 .uleb128 0x5
340 008c E8000000 .4byte .LASF12
BFIN GAS /tmp/ccCtLplV.s page 8
341 0090 02 .byte 0x2
342 0091 50 .byte 0x50
343 0092 25000000 .4byte 0x25
344 0096 06 .uleb128 0x6
345 0097 04 .byte 0x4
346 0098 03 .byte 0x3
347 0099 45 .byte 0x45
348 009a AF000000 .4byte 0xaf
349 009e 07 .uleb128 0x7
350 009f D1000000 .4byte .LASF13
351 00a3 808008 .sleb128 131072
352 00a6 07 .uleb128 0x7
353 00a7 FA000000 .4byte .LASF14
354 00ab 808004 .sleb128 65536
355 00ae 00 .byte 0x0
356 00af 08 .uleb128 0x8
357 00b0 01 .byte 0x1
358 00b1 C6000000 .4byte .LASF18
359 00b5 01 .byte 0x1
360 00b6 1F .byte 0x1f
361 00b7 01 .byte 0x1
362 00b8 00000000 .4byte .LFB3
363 00bc 3E000000 .4byte .LFE3
364 00c0 00000000 .4byte .LLST0
365 00c4 F8000000 .4byte 0xf8
366 00c8 09 .uleb128 0x9
367 00c9 76616C00 .string "val"
368 00cd 01 .byte 0x1
369 00ce 1F .byte 0x1f
370 00cf 8B000000 .4byte 0x8b
371 00d3 2B000000 .4byte .LLST1
372 00d7 09 .uleb128 0x9
373 00d8 6D736B00 .string "msk"
374 00dc 01 .byte 0x1
375 00dd 1F .byte 0x1f
376 00de 8B000000 .4byte 0x8b
377 00e2 6A000000 .4byte .LLST2
378 00e6 0A .uleb128 0xa
379 00e7 35000000 .4byte .LASF19
380 00eb 01 .byte 0x1
381 00ec 20 .byte 0x20
382 00ed 8B000000 .4byte 0x8b
383 00f1 05 .byte 0x5
384 00f2 03 .byte 0x3
385 00f3 00000000 .4byte _last_out.2066
386 00f7 00 .byte 0x0
387 00f8 0B .uleb128 0xb
388 00f9 01 .byte 0x1
389 00fa 30010000 .4byte .LASF20
390 00fe 01 .byte 0x1
391 00ff 14 .byte 0x14
392 0100 01 .byte 0x1
393 0101 40000000 .4byte .LFB2
394 0105 68000000 .4byte .LFE2
395 0109 93000000 .4byte .LLST3
396 010d 09 .uleb128 0x9
397 010e 636800 .string "ch"
BFIN GAS /tmp/ccCtLplV.s page 9
398 0111 01 .byte 0x1
399 0112 14 .byte 0x14
400 0113 75000000 .4byte 0x75
401 0117 B2000000 .4byte .LLST4
402 011b 09 .uleb128 0x9
403 011c 76616C00 .string "val"
404 0120 01 .byte 0x1
405 0121 14 .byte 0x14
406 0122 80000000 .4byte 0x80
407 0126 D0000000 .4byte .LLST5
408 012a 00 .byte 0x0
409 012b 00 .byte 0x0
410 .section .debug_abbrev
411 0000 01 .uleb128 0x1
412 0001 11 .uleb128 0x11
413 0002 01 .byte 0x1
414 0003 25 .uleb128 0x25
415 0004 0E .uleb128 0xe
416 0005 13 .uleb128 0x13
417 0006 0B .uleb128 0xb
418 0007 03 .uleb128 0x3
419 0008 0E .uleb128 0xe
420 0009 1B .uleb128 0x1b
421 000a 0E .uleb128 0xe
422 000b 11 .uleb128 0x11
423 000c 01 .uleb128 0x1
424 000d 12 .uleb128 0x12
425 000e 01 .uleb128 0x1
426 000f 10 .uleb128 0x10
427 0010 06 .uleb128 0x6
428 0011 00 .byte 0x0
429 0012 00 .byte 0x0
430 0013 02 .uleb128 0x2
431 0014 24 .uleb128 0x24
432 0015 00 .byte 0x0
433 0016 0B .uleb128 0xb
434 0017 0B .uleb128 0xb
435 0018 3E .uleb128 0x3e
436 0019 0B .uleb128 0xb
437 001a 03 .uleb128 0x3
438 001b 0E .uleb128 0xe
439 001c 00 .byte 0x0
440 001d 00 .byte 0x0
441 001e 03 .uleb128 0x3
442 001f 24 .uleb128 0x24
443 0020 00 .byte 0x0
444 0021 0B .uleb128 0xb
445 0022 0B .uleb128 0xb
446 0023 3E .uleb128 0x3e
447 0024 0B .uleb128 0xb
448 0025 03 .uleb128 0x3
449 0026 08 .uleb128 0x8
450 0027 00 .byte 0x0
451 0028 00 .byte 0x0
452 0029 04 .uleb128 0x4
453 002a 24 .uleb128 0x24
454 002b 00 .byte 0x0
BFIN GAS /tmp/ccCtLplV.s page 10
455 002c 0B .uleb128 0xb
456 002d 0B .uleb128 0xb
457 002e 3E .uleb128 0x3e
458 002f 0B .uleb128 0xb
459 0030 00 .byte 0x0
460 0031 00 .byte 0x0
461 0032 05 .uleb128 0x5
462 0033 16 .uleb128 0x16
463 0034 00 .byte 0x0
464 0035 03 .uleb128 0x3
465 0036 0E .uleb128 0xe
466 0037 3A .uleb128 0x3a
467 0038 0B .uleb128 0xb
468 0039 3B .uleb128 0x3b
469 003a 0B .uleb128 0xb
470 003b 49 .uleb128 0x49
471 003c 13 .uleb128 0x13
472 003d 00 .byte 0x0
473 003e 00 .byte 0x0
474 003f 06 .uleb128 0x6
475 0040 04 .uleb128 0x4
476 0041 01 .byte 0x1
477 0042 0B .uleb128 0xb
478 0043 0B .uleb128 0xb
479 0044 3A .uleb128 0x3a
480 0045 0B .uleb128 0xb
481 0046 3B .uleb128 0x3b
482 0047 0B .uleb128 0xb
483 0048 01 .uleb128 0x1
484 0049 13 .uleb128 0x13
485 004a 00 .byte 0x0
486 004b 00 .byte 0x0
487 004c 07 .uleb128 0x7
488 004d 28 .uleb128 0x28
489 004e 00 .byte 0x0
490 004f 03 .uleb128 0x3
491 0050 0E .uleb128 0xe
492 0051 1C .uleb128 0x1c
493 0052 0D .uleb128 0xd
494 0053 00 .byte 0x0
495 0054 00 .byte 0x0
496 0055 08 .uleb128 0x8
497 0056 2E .uleb128 0x2e
498 0057 01 .byte 0x1
499 0058 3F .uleb128 0x3f
500 0059 0C .uleb128 0xc
501 005a 03 .uleb128 0x3
502 005b 0E .uleb128 0xe
503 005c 3A .uleb128 0x3a
504 005d 0B .uleb128 0xb
505 005e 3B .uleb128 0x3b
506 005f 0B .uleb128 0xb
507 0060 27 .uleb128 0x27
508 0061 0C .uleb128 0xc
509 0062 11 .uleb128 0x11
510 0063 01 .uleb128 0x1
511 0064 12 .uleb128 0x12
BFIN GAS /tmp/ccCtLplV.s page 11
512 0065 01 .uleb128 0x1
513 0066 40 .uleb128 0x40
514 0067 06 .uleb128 0x6
515 0068 01 .uleb128 0x1
516 0069 13 .uleb128 0x13
517 006a 00 .byte 0x0
518 006b 00 .byte 0x0
519 006c 09 .uleb128 0x9
520 006d 05 .uleb128 0x5
521 006e 00 .byte 0x0
522 006f 03 .uleb128 0x3
523 0070 08 .uleb128 0x8
524 0071 3A .uleb128 0x3a
525 0072 0B .uleb128 0xb
526 0073 3B .uleb128 0x3b
527 0074 0B .uleb128 0xb
528 0075 49 .uleb128 0x49
529 0076 13 .uleb128 0x13
530 0077 02 .uleb128 0x2
531 0078 06 .uleb128 0x6
532 0079 00 .byte 0x0
533 007a 00 .byte 0x0
534 007b 0A .uleb128 0xa
535 007c 34 .uleb128 0x34
536 007d 00 .byte 0x0
537 007e 03 .uleb128 0x3
538 007f 0E .uleb128 0xe
539 0080 3A .uleb128 0x3a
540 0081 0B .uleb128 0xb
541 0082 3B .uleb128 0x3b
542 0083 0B .uleb128 0xb
543 0084 49 .uleb128 0x49
544 0085 13 .uleb128 0x13
545 0086 02 .uleb128 0x2
546 0087 0A .uleb128 0xa
547 0088 00 .byte 0x0
548 0089 00 .byte 0x0
549 008a 0B .uleb128 0xb
550 008b 2E .uleb128 0x2e
551 008c 01 .byte 0x1
552 008d 3F .uleb128 0x3f
553 008e 0C .uleb128 0xc
554 008f 03 .uleb128 0x3
555 0090 0E .uleb128 0xe
556 0091 3A .uleb128 0x3a
557 0092 0B .uleb128 0xb
558 0093 3B .uleb128 0x3b
559 0094 0B .uleb128 0xb
560 0095 27 .uleb128 0x27
561 0096 0C .uleb128 0xc
562 0097 11 .uleb128 0x11
563 0098 01 .uleb128 0x1
564 0099 12 .uleb128 0x12
565 009a 01 .uleb128 0x1
566 009b 40 .uleb128 0x40
567 009c 06 .uleb128 0x6
568 009d 00 .byte 0x0
BFIN GAS /tmp/ccCtLplV.s page 12
569 009e 00 .byte 0x0
570 009f 00 .byte 0x0
571 .section .debug_pubnames,"",@progbits
572 0000 2F000000 .4byte 0x2f
573 0004 0200 .2byte 0x2
574 0006 00000000 .4byte .Ldebug_info0
575 000a 2C010000 .4byte 0x12c
576 000e AF000000 .4byte 0xaf
577 0012 6173796E .string "async_dout"
577 635F646F
577 757400
578 001d F8000000 .4byte 0xf8
579 0021 6173796E .string "async_dac_out"
579 635F6461
579 635F6F75
579 7400
580 002f 00000000 .4byte 0x0
581 .section .debug_aranges,"",@progbits
582 0000 1C000000 .4byte 0x1c
583 0004 0200 .2byte 0x2
584 0006 00000000 .4byte .Ldebug_info0
585 000a 04 .byte 0x4
586 000b 00 .byte 0x0
587 000c 0000 .2byte 0x0
588 000e 0000 .2byte 0x0
589 0010 00000000 .4byte .Ltext0
590 0014 68000000 .4byte .Letext0-.Ltext0
591 0018 00000000 .4byte 0x0
592 001c 00000000 .4byte 0x0
593 .section .debug_str,"MS",@progbits,1
594 .LASF6:
595 0000 6C6F6E67 .string "long long int"
595 206C6F6E
595 6720696E
595 7400
596 .LASF5:
597 000e 756E7369 .string "unsigned int"
597 676E6564
597 20696E74
597 00
598 .LASF11:
599 001b 696E7433 .string "int32_t"
599 325F7400
600 .LASF0:
601 0023 6C6F6E67 .string "long unsigned int"
601 20756E73
601 69676E65
601 6420696E
601 7400
602 .LASF19:
603 0035 6C617374 .string "last_out"
603 5F6F7574
603 00
604 .LASF7:
605 003e 6C6F6E67 .string "long long unsigned int"
605 206C6F6E
605 6720756E
BFIN GAS /tmp/ccCtLplV.s page 13
605 7369676E
605 65642069
606 .LASF17:
607 0055 2F686F6D .string "/home/feda/MIPT/RadioPhotonic_Subserface_radar/ADC_computing/BFfirmware_0"
607 652F6665
607 64612F4D
607 4950542F
607 52616469
608 .LASF16:
609 009f 7372632F .string "src/l502_async.c"
609 6C353032
609 5F617379
609 6E632E63
609 00
610 .LASF10:
611 00b0 75696E74 .string "uint8_t"
611 385F7400
612 .LASF2:
613 00b8 756E7369 .string "unsigned char"
613 676E6564
613 20636861
613 7200
614 .LASF18:
615 00c6 6173796E .string "async_dout"
615 635F646F
615 757400
616 .LASF13:
617 00d1 4C353032 .string "L502_DIGOUT_WORD_DIS_H"
617 5F444947
617 4F55545F
617 574F5244
617 5F444953
618 .LASF12:
619 00e8 75696E74 .string "uint32_t"
619 33325F74
619 00
620 .LASF8:
621 00f1 6C6F6E67 .string "long int"
621 20696E74
621 00
622 .LASF14:
623 00fa 4C353032 .string "L502_DIGOUT_WORD_DIS_L"
623 5F444947
623 4F55545F
623 574F5244
623 5F444953
624 .LASF4:
625 0111 73686F72 .string "short unsigned int"
625 7420756E
625 7369676E
625 65642069
625 6E7400
626 .LASF1:
627 0124 7369676E .string "signed char"
627 65642063
627 68617200
628 .LASF20:
BFIN GAS /tmp/ccCtLplV.s page 14
629 0130 6173796E .string "async_dac_out"
629 635F6461
629 635F6F75
629 7400
630 .LASF3:
631 013e 73686F72 .string "short int"
631 7420696E
631 7400
632 .LASF15:
633 0148 474E5520 .string "GNU C 4.3.5"
633 4320342E
633 332E3500
634 .LASF9:
635 0154 63686172 .string "char"
635 00
636 .ident "GCC: (ADI-2014R1-RC2) 4.3.5"
BFIN GAS /tmp/ccCtLplV.s page 15
DEFINED SYMBOLS
*ABS*:0000000000000000 src/l502_async.c
/tmp/ccCtLplV.s:13 .text:0000000000000000 _async_dout
/tmp/ccCtLplV.s:115 .data:0000000000000000 _last_out.2066
/tmp/ccCtLplV.s:70 .text:0000000000000040 _async_dac_out
UNDEFINED SYMBOLS
_fpga_reg_write
build/release/lst/l502_cmd.lst
+6679
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build/release/lst/l502_fpga.lst
+2421
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build/release/lst/l502_hdma.lst
+4627
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build/release/lst/l502_init.lst
+3093
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build/release/lst/l502_params.lst
+3006
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build/release/lst/l502_sport_tx.lst
+3317
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build/release/lst/l502_stream.lst
+6583
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build/release/lst/l502_tests.lst
+4270
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build/release/lst/l502_user_process.lst
+1500
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build/release/lst/main.lst
+901
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@@ -0,0 +1,901 @@
BFIN GAS /tmp/ccQKVwPF.s page 1
1 .file "src/main.c";
2 .section .debug_abbrev,"",@progbits
3 .Ldebug_abbrev0:
4 .section .debug_info,"",@progbits
5 .Ldebug_info0:
6 .section .debug_line,"",@progbits
7 .Ldebug_line0:
8 0000 F6000000 .text;
8 0200DE00
8 00000101
8 FB0E0D00
8 01010101
9 .Ltext0:
10 .align 4
11 .global _main;
12 .type _main, STT_FUNC;
13 _main:
14 .LFB2:
15 .file 1 "src/main.c"
1:src/main.c **** /*****************************************************************************
2:src/main.c **** * NewProject.c
3:src/main.c **** *****************************************************************************/
4:src/main.c ****
5:src/main.c **** #include "l502_cdefs.h"
6:src/main.c **** void l502_init(void);
7:src/main.c **** #include "l502_global.h"
8:src/main.c **** #include "l502_cmd.h"
9:src/main.c ****
10:src/main.c **** void stream_proc(void);
11:src/main.c ****
12:src/main.c **** /* g_state îïèñûâàåò îáëàñòü ïàìÿòè, ðàñïîëîæåííóþ ïî ôèêñèðîâàííûì àäðåñàì.
13:src/main.c **** * Äëÿ ðàñïîëîæåíèÿ â íà÷àëî áàíêà A äàííûõ èñïîëüçóåì ñïåöèàëüíóþ ñåêöèþ */
14:src/main.c **** SECTION("board_state", volatile t_l502_board_state g_state);
15:src/main.c ****
16:src/main.c ****
17:src/main.c **** int main(void) {
16 .loc 1 17 0
17 0000 00E80300 LINK 12;
18 .LCFI0:
18:src/main.c **** /* Èíèöèàëèçàöèÿ èíòåðôåéñîâ */
19:src/main.c **** l502_init();
19 .loc 1 19 0
20 0004 FFE3FEFF call _l502_init;
21 .L2:
20:src/main.c ****
21:src/main.c **** for (;;) {
22:src/main.c **** /* ïðîâåðÿåì íàëè÷èå êîìàíäû îò ÏÊ è íà÷èíàÿåì
23:src/main.c **** îáðàáîòêó, åñëè îíà åñòü */
24:src/main.c **** l502_cmd_check_req();
22 .loc 1 24 0
23 0008 FFE3FCFF call _l502_cmd_check_req;
25:src/main.c **** /* îáðàáîòêà ïîòîêîâ äàííûõ */
26:src/main.c **** stream_proc();
24 .loc 1 26 0
25 000c FFE3FAFF call _stream_proc;
26 0010 FC2F jump.s .L2;
27 .LFE2:
BFIN GAS /tmp/ccQKVwPF.s page 2
28 .size _main, .-_main
29 .global _g_state;
30 .section board_state,"aw",@progbits
31 .align 4
32 .type _g_state, @object
33 .size _g_state, 6160
34 _g_state:
35 0000 00000000 .zero 6160
35 00000000
35 00000000
35 00000000
35 00000000
36 .section .debug_frame,"",@progbits
37 .Lframe0:
38 0000 0C000000 .4byte .LECIE0-.LSCIE0
39 .LSCIE0:
40 0004 FFFFFFFF .4byte 0xffffffff
41 0008 01 .byte 0x1
42 0009 00 .string ""
43 000a 01 .uleb128 0x1
44 000b 7C .sleb128 -4
45 000c 23 .byte 0x23
46 000d 0C .byte 0xc
47 000e 0E .uleb128 0xe
48 000f 00 .uleb128 0x0
49 .align 4
50 .LECIE0:
51 .LSFDE0:
52 0010 14000000 .4byte .LEFDE0-.LASFDE0
53 .LASFDE0:
54 0014 00000000 .4byte .Lframe0
55 0018 00000000 .4byte .LFB2
56 001c 12000000 .4byte .LFE2-.LFB2
57 0020 44 .byte 0x4
58 .4byte .LCFI0-.LFB2
59 0021 0C .byte 0xc
60 0022 0F .uleb128 0xf
61 0023 08 .uleb128 0x8
62 0024 8F .byte 0x8f
63 0025 02 .uleb128 0x2
64 0026 A3 .byte 0xa3
65 0027 01 .uleb128 0x1
66 .align 4
67 .LEFDE0:
68 .text;
69 .Letext0:
70 0012 0000 .section .debug_loc,"",@progbits
71 .Ldebug_loc0:
72 .LLST0:
73 0000 00000000 .4byte .LFB2-.Ltext0
74 0004 04000000 .4byte .LCFI0-.Ltext0
75 0008 0100 .2byte 0x1
76 000a 5E .byte 0x5e
77 000b 04000000 .4byte .LCFI0-.Ltext0
78 000f 12000000 .4byte .LFE2-.Ltext0
79 0013 0200 .2byte 0x2
80 0015 7F .byte 0x7f
BFIN GAS /tmp/ccQKVwPF.s page 3
81 0016 08 .sleb128 8
82 0017 00000000 .4byte 0x0
83 001b 00000000 .4byte 0x0
84 .file 2 "/home/feda/MIPT/RadioPhotonic_Subserface_radar/BlackFin/toolchain_off/bfin-elf/bin/../lib
85 .file 3 "src/l502_bf_cmd_defs.h"
86 .file 4 "src/l502_global.h"
87 .section .debug_info
88 0000 75020000 .4byte 0x275
89 0004 0200 .2byte 0x2
90 0006 00000000 .4byte .Ldebug_abbrev0
91 000a 04 .byte 0x4
92 000b 01 .uleb128 0x1
93 000c 0D000000 .4byte .LASF35
94 0010 01 .byte 0x1
95 0011 C1010000 .4byte .LASF36
96 0015 34010000 .4byte .LASF37
97 0019 00000000 .4byte .Ltext0
98 001d 12000000 .4byte .Letext0
99 0021 00000000 .4byte .Ldebug_line0
100 0025 02 .uleb128 0x2
101 0026 01 .byte 0x1
102 0027 06 .byte 0x6
103 0028 94000000 .4byte .LASF0
104 002c 02 .uleb128 0x2
105 002d 01 .byte 0x1
106 002e 08 .byte 0x8
107 002f 86000000 .4byte .LASF1
108 0033 02 .uleb128 0x2
109 0034 02 .byte 0x2
110 0035 05 .byte 0x5
111 0036 19000000 .4byte .LASF2
112 003a 03 .uleb128 0x3
113 003b D3000000 .4byte .LASF4
114 003f 02 .byte 0x2
115 0040 36 .byte 0x36
116 0041 45000000 .4byte 0x45
117 0045 02 .uleb128 0x2
118 0046 02 .byte 0x2
119 0047 07 .byte 0x7
120 0048 F8000000 .4byte .LASF3
121 004c 03 .uleb128 0x3
122 004d 1D010000 .4byte .LASF5
123 0051 02 .byte 0x2
124 0052 4F .byte 0x4f
125 0053 57000000 .4byte 0x57
126 0057 02 .uleb128 0x2
127 0058 04 .byte 0x4
128 0059 05 .byte 0x5
129 005a 4E000000 .4byte .LASF6
130 005e 03 .uleb128 0x3
131 005f BD000000 .4byte .LASF7
132 0063 02 .byte 0x2
133 0064 50 .byte 0x50
134 0065 69000000 .4byte 0x69
135 0069 02 .uleb128 0x2
136 006a 04 .byte 0x4
137 006b 07 .byte 0x7
BFIN GAS /tmp/ccQKVwPF.s page 4
138 006c 92010000 .4byte .LASF8
139 0070 02 .uleb128 0x2
140 0071 08 .byte 0x8
141 0072 05 .byte 0x5
142 0073 40000000 .4byte .LASF9
143 0077 02 .uleb128 0x2
144 0078 08 .byte 0x8
145 0079 07 .byte 0x7
146 007a A6000000 .4byte .LASF10
147 007e 04 .uleb128 0x4
148 007f 04 .byte 0x4
149 0080 05 .byte 0x5
150 0081 696E7400 .string "int"
151 0085 02 .uleb128 0x2
152 0086 04 .byte 0x4
153 0087 07 .byte 0x7
154 0088 C6000000 .4byte .LASF11
155 008c 05 .uleb128 0x5
156 008d 1010 .2byte 0x1010
157 008f 03 .byte 0x3
158 0090 8B .byte 0x8b
159 0091 EA000000 .4byte 0xea
160 0095 06 .uleb128 0x6
161 0096 ED000000 .4byte .LASF12
162 009a 03 .byte 0x3
163 009b 8C .byte 0x8c
164 009c 3A000000 .4byte 0x3a
165 00a0 02 .byte 0x2
166 00a1 23 .byte 0x23
167 00a2 00 .uleb128 0x0
168 00a3 06 .uleb128 0x6
169 00a4 0B010000 .4byte .LASF13
170 00a8 03 .byte 0x3
171 00a9 8D .byte 0x8d
172 00aa 3A000000 .4byte 0x3a
173 00ae 02 .byte 0x2
174 00af 23 .byte 0x23
175 00b0 02 .uleb128 0x2
176 00b1 06 .uleb128 0x6
177 00b2 F2000000 .4byte .LASF14
178 00b6 03 .byte 0x3
179 00b7 8E .byte 0x8e
180 00b8 5E000000 .4byte 0x5e
181 00bc 02 .byte 0x2
182 00bd 23 .byte 0x23
183 00be 04 .uleb128 0x4
184 00bf 06 .uleb128 0x6
185 00c0 06000000 .4byte .LASF15
186 00c4 03 .byte 0x3
187 00c5 8F .byte 0x8f
188 00c6 4C000000 .4byte 0x4c
189 00ca 02 .byte 0x2
190 00cb 23 .byte 0x23
191 00cc 08 .uleb128 0x8
192 00cd 06 .uleb128 0x6
193 00ce 7C000000 .4byte .LASF16
194 00d2 03 .byte 0x3
BFIN GAS /tmp/ccQKVwPF.s page 5
195 00d3 90 .byte 0x90
196 00d4 5E000000 .4byte 0x5e
197 00d8 02 .byte 0x2
198 00d9 23 .byte 0x23
199 00da 0C .uleb128 0xc
200 00db 06 .uleb128 0x6
201 00dc 2A010000 .4byte .LASF17
202 00e0 03 .byte 0x3
203 00e1 91 .byte 0x91
204 00e2 EA000000 .4byte 0xea
205 00e6 02 .byte 0x2
206 00e7 23 .byte 0x23
207 00e8 10 .uleb128 0x10
208 00e9 00 .byte 0x0
209 00ea 07 .uleb128 0x7
210 00eb 5E000000 .4byte 0x5e
211 00ef FB000000 .4byte 0xfb
212 00f3 08 .uleb128 0x8
213 00f4 FB000000 .4byte 0xfb
214 00f8 FF03 .2byte 0x3ff
215 00fa 00 .byte 0x0
216 00fb 09 .uleb128 0x9
217 00fc 04 .byte 0x4
218 00fd 07 .byte 0x7
219 00fe 03 .uleb128 0x3
220 00ff 6E000000 .4byte .LASF18
221 0103 03 .byte 0x3
222 0104 92 .byte 0x92
223 0105 8C000000 .4byte 0x8c
224 0109 0A .uleb128 0xa
225 010a 20 .byte 0x20
226 010b 04 .byte 0x4
227 010c 1C .byte 0x1c
228 010d AB010000 .4byte 0x1ab
229 0111 06 .uleb128 0x6
230 0112 A0000000 .4byte .LASF19
231 0116 04 .byte 0x4
232 0117 1D .byte 0x1d
233 0118 5E000000 .4byte 0x5e
234 011c 02 .byte 0x2
235 011d 23 .byte 0x23
236 011e 00 .uleb128 0x0
237 011f 06 .uleb128 0x6
238 0120 36000000 .4byte .LASF20
239 0124 04 .byte 0x4
240 0125 1E .byte 0x1e
241 0126 5E000000 .4byte 0x5e
242 012a 02 .byte 0x2
243 012b 23 .byte 0x23
244 012c 04 .uleb128 0x4
245 012d 06 .uleb128 0x6
246 012e 5E000000 .4byte .LASF21
247 0132 04 .byte 0x4
248 0133 1F .byte 0x1f
249 0134 AB010000 .4byte 0x1ab
250 0138 02 .byte 0x2
251 0139 23 .byte 0x23
BFIN GAS /tmp/ccQKVwPF.s page 6
252 013a 08 .uleb128 0x8
253 013b 06 .uleb128 0x6
254 013c 18010000 .4byte .LASF22
255 0140 04 .byte 0x4
256 0141 20 .byte 0x20
257 0142 3A000000 .4byte 0x3a
258 0146 02 .byte 0x2
259 0147 23 .byte 0x23
260 0148 0C .uleb128 0xc
261 0149 06 .uleb128 0x6
262 014a 25010000 .4byte .LASF23
263 014e 04 .byte 0x4
264 014f 21 .byte 0x21
265 0150 3A000000 .4byte 0x3a
266 0154 02 .byte 0x2
267 0155 23 .byte 0x23
268 0156 0E .uleb128 0xe
269 0157 06 .uleb128 0x6
270 0158 A4010000 .4byte .LASF24
271 015c 04 .byte 0x4
272 015d 22 .byte 0x22
273 015e 3A000000 .4byte 0x3a
274 0162 02 .byte 0x2
275 0163 23 .byte 0x23
276 0164 10 .uleb128 0x10
277 0165 06 .uleb128 0x6
278 0166 BC010000 .4byte .LASF25
279 016a 04 .byte 0x4
280 016b 23 .byte 0x23
281 016c 3A000000 .4byte 0x3a
282 0170 02 .byte 0x2
283 0171 23 .byte 0x23
284 0172 12 .uleb128 0x12
285 0173 06 .uleb128 0x6
286 0174 63000000 .4byte .LASF26
287 0178 04 .byte 0x4
288 0179 24 .byte 0x24
289 017a AB010000 .4byte 0x1ab
290 017e 02 .byte 0x2
291 017f 23 .byte 0x23
292 0180 14 .uleb128 0x14
293 0181 0B .uleb128 0xb
294 0182 696400 .string "id"
295 0185 04 .byte 0x4
296 0186 25 .byte 0x25
297 0187 3A000000 .4byte 0x3a
298 018b 02 .byte 0x2
299 018c 23 .byte 0x23
300 018d 18 .uleb128 0x18
301 018e 06 .uleb128 0x6
302 018f 00000000 .4byte .LASF27
303 0193 04 .byte 0x4
304 0194 26 .byte 0x26
305 0195 3A000000 .4byte 0x3a
306 0199 02 .byte 0x2
307 019a 23 .byte 0x23
308 019b 1A .uleb128 0x1a
BFIN GAS /tmp/ccQKVwPF.s page 7
309 019c 06 .uleb128 0x6
310 019d 12010000 .4byte .LASF28
311 01a1 04 .byte 0x4
312 01a2 27 .byte 0x27
313 01a3 5E000000 .4byte 0x5e
314 01a7 02 .byte 0x2
315 01a8 23 .byte 0x23
316 01a9 1C .uleb128 0x1c
317 01aa 00 .byte 0x0
318 01ab 0C .uleb128 0xc
319 01ac 04 .byte 0x4
320 01ad 03 .uleb128 0x3
321 01ae 7E010000 .4byte .LASF29
322 01b2 04 .byte 0x4
323 01b3 28 .byte 0x28
324 01b4 09010000 .4byte 0x109
325 01b8 05 .uleb128 0x5
326 01b9 0008 .2byte 0x800
327 01bb 04 .byte 0x4
328 01bc 36 .byte 0x36
329 01bd FB010000 .4byte 0x1fb
330 01c1 06 .uleb128 0x6
331 01c2 23000000 .4byte .LASF30
332 01c6 04 .byte 0x4
333 01c7 37 .byte 0x37
334 01c8 AD010000 .4byte 0x1ad
335 01cc 02 .byte 0x2
336 01cd 23 .byte 0x23
337 01ce 00 .uleb128 0x0
338 01cf 0B .uleb128 0xb
339 01d0 696E00 .string "in"
340 01d3 04 .byte 0x4
341 01d4 38 .byte 0x38
342 01d5 FB010000 .4byte 0x1fb
343 01d9 02 .byte 0x2
344 01da 23 .byte 0x23
345 01db 20 .uleb128 0x20
346 01dc 06 .uleb128 0x6
347 01dd 57000000 .4byte .LASF31
348 01e1 04 .byte 0x4
349 01e2 39 .byte 0x39
350 01e3 AD010000 .4byte 0x1ad
351 01e7 03 .byte 0x3
352 01e8 23 .byte 0x23
353 01e9 8008 .uleb128 0x400
354 01eb 0B .uleb128 0xb
355 01ec 6F757400 .string "out"
356 01f0 04 .byte 0x4
357 01f1 3A .byte 0x3a
358 01f2 FB010000 .4byte 0x1fb
359 01f6 03 .byte 0x3
360 01f7 23 .byte 0x23
361 01f8 A008 .uleb128 0x420
362 01fa 00 .byte 0x0
363 01fb 07 .uleb128 0x7
364 01fc AD010000 .4byte 0x1ad
365 0200 0B020000 .4byte 0x20b
BFIN GAS /tmp/ccQKVwPF.s page 8
366 0204 0D .uleb128 0xd
367 0205 FB000000 .4byte 0xfb
368 0209 1E .byte 0x1e
369 020a 00 .byte 0x0
370 020b 03 .uleb128 0x3
371 020c DC000000 .4byte .LASF32
372 0210 04 .byte 0x4
373 0211 3B .byte 0x3b
374 0212 B8010000 .4byte 0x1b8
375 0216 05 .uleb128 0x5
376 0217 1018 .2byte 0x1810
377 0219 04 .byte 0x4
378 021a 42 .byte 0x42
379 021b 3D020000 .4byte 0x23d
380 021f 06 .uleb128 0x6
381 0220 2F010000 .4byte .LASF33
382 0224 04 .byte 0x4
383 0225 43 .byte 0x43
384 0226 0B020000 .4byte 0x20b
385 022a 02 .byte 0x2
386 022b 23 .byte 0x23
387 022c 00 .uleb128 0x0
388 022d 0B .uleb128 0xb
389 022e 636D6400 .string "cmd"
390 0232 04 .byte 0x4
391 0233 44 .byte 0x44
392 0234 FE000000 .4byte 0xfe
393 0238 03 .byte 0x3
394 0239 23 .byte 0x23
395 023a 8010 .uleb128 0x800
396 023c 00 .byte 0x0
397 023d 03 .uleb128 0x3
398 023e A9010000 .4byte .LASF34
399 0242 04 .byte 0x4
400 0243 45 .byte 0x45
401 0244 16020000 .4byte 0x216
402 0248 0E .uleb128 0xe
403 0249 01 .byte 0x1
404 024a 29000000 .4byte .LASF38
405 024e 01 .byte 0x1
406 024f 11 .byte 0x11
407 0250 01 .byte 0x1
408 0251 7E000000 .4byte 0x7e
409 0255 00000000 .4byte .LFB2
410 0259 12000000 .4byte .LFE2
411 025d 00000000 .4byte .LLST0
412 0261 0F .uleb128 0xf
413 0262 2E000000 .4byte .LASF39
414 0266 01 .byte 0x1
415 0267 0E .byte 0xe
416 0268 73020000 .4byte 0x273
417 026c 01 .byte 0x1
418 026d 05 .byte 0x5
419 026e 03 .byte 0x3
420 026f 00000000 .4byte _g_state
421 0273 10 .uleb128 0x10
422 0274 3D020000 .4byte 0x23d
BFIN GAS /tmp/ccQKVwPF.s page 9
423 0278 00 .byte 0x0
424 .section .debug_abbrev
425 0000 01 .uleb128 0x1
426 0001 11 .uleb128 0x11
427 0002 01 .byte 0x1
428 0003 25 .uleb128 0x25
429 0004 0E .uleb128 0xe
430 0005 13 .uleb128 0x13
431 0006 0B .uleb128 0xb
432 0007 03 .uleb128 0x3
433 0008 0E .uleb128 0xe
434 0009 1B .uleb128 0x1b
435 000a 0E .uleb128 0xe
436 000b 11 .uleb128 0x11
437 000c 01 .uleb128 0x1
438 000d 12 .uleb128 0x12
439 000e 01 .uleb128 0x1
440 000f 10 .uleb128 0x10
441 0010 06 .uleb128 0x6
442 0011 00 .byte 0x0
443 0012 00 .byte 0x0
444 0013 02 .uleb128 0x2
445 0014 24 .uleb128 0x24
446 0015 00 .byte 0x0
447 0016 0B .uleb128 0xb
448 0017 0B .uleb128 0xb
449 0018 3E .uleb128 0x3e
450 0019 0B .uleb128 0xb
451 001a 03 .uleb128 0x3
452 001b 0E .uleb128 0xe
453 001c 00 .byte 0x0
454 001d 00 .byte 0x0
455 001e 03 .uleb128 0x3
456 001f 16 .uleb128 0x16
457 0020 00 .byte 0x0
458 0021 03 .uleb128 0x3
459 0022 0E .uleb128 0xe
460 0023 3A .uleb128 0x3a
461 0024 0B .uleb128 0xb
462 0025 3B .uleb128 0x3b
463 0026 0B .uleb128 0xb
464 0027 49 .uleb128 0x49
465 0028 13 .uleb128 0x13
466 0029 00 .byte 0x0
467 002a 00 .byte 0x0
468 002b 04 .uleb128 0x4
469 002c 24 .uleb128 0x24
470 002d 00 .byte 0x0
471 002e 0B .uleb128 0xb
472 002f 0B .uleb128 0xb
473 0030 3E .uleb128 0x3e
474 0031 0B .uleb128 0xb
475 0032 03 .uleb128 0x3
476 0033 08 .uleb128 0x8
477 0034 00 .byte 0x0
478 0035 00 .byte 0x0
479 0036 05 .uleb128 0x5
BFIN GAS /tmp/ccQKVwPF.s page 10
480 0037 13 .uleb128 0x13
481 0038 01 .byte 0x1
482 0039 0B .uleb128 0xb
483 003a 05 .uleb128 0x5
484 003b 3A .uleb128 0x3a
485 003c 0B .uleb128 0xb
486 003d 3B .uleb128 0x3b
487 003e 0B .uleb128 0xb
488 003f 01 .uleb128 0x1
489 0040 13 .uleb128 0x13
490 0041 00 .byte 0x0
491 0042 00 .byte 0x0
492 0043 06 .uleb128 0x6
493 0044 0D .uleb128 0xd
494 0045 00 .byte 0x0
495 0046 03 .uleb128 0x3
496 0047 0E .uleb128 0xe
497 0048 3A .uleb128 0x3a
498 0049 0B .uleb128 0xb
499 004a 3B .uleb128 0x3b
500 004b 0B .uleb128 0xb
501 004c 49 .uleb128 0x49
502 004d 13 .uleb128 0x13
503 004e 38 .uleb128 0x38
504 004f 0A .uleb128 0xa
505 0050 00 .byte 0x0
506 0051 00 .byte 0x0
507 0052 07 .uleb128 0x7
508 0053 01 .uleb128 0x1
509 0054 01 .byte 0x1
510 0055 49 .uleb128 0x49
511 0056 13 .uleb128 0x13
512 0057 01 .uleb128 0x1
513 0058 13 .uleb128 0x13
514 0059 00 .byte 0x0
515 005a 00 .byte 0x0
516 005b 08 .uleb128 0x8
517 005c 21 .uleb128 0x21
518 005d 00 .byte 0x0
519 005e 49 .uleb128 0x49
520 005f 13 .uleb128 0x13
521 0060 2F .uleb128 0x2f
522 0061 05 .uleb128 0x5
523 0062 00 .byte 0x0
524 0063 00 .byte 0x0
525 0064 09 .uleb128 0x9
526 0065 24 .uleb128 0x24
527 0066 00 .byte 0x0
528 0067 0B .uleb128 0xb
529 0068 0B .uleb128 0xb
530 0069 3E .uleb128 0x3e
531 006a 0B .uleb128 0xb
532 006b 00 .byte 0x0
533 006c 00 .byte 0x0
534 006d 0A .uleb128 0xa
535 006e 13 .uleb128 0x13
536 006f 01 .byte 0x1
BFIN GAS /tmp/ccQKVwPF.s page 11
537 0070 0B .uleb128 0xb
538 0071 0B .uleb128 0xb
539 0072 3A .uleb128 0x3a
540 0073 0B .uleb128 0xb
541 0074 3B .uleb128 0x3b
542 0075 0B .uleb128 0xb
543 0076 01 .uleb128 0x1
544 0077 13 .uleb128 0x13
545 0078 00 .byte 0x0
546 0079 00 .byte 0x0
547 007a 0B .uleb128 0xb
548 007b 0D .uleb128 0xd
549 007c 00 .byte 0x0
550 007d 03 .uleb128 0x3
551 007e 08 .uleb128 0x8
552 007f 3A .uleb128 0x3a
553 0080 0B .uleb128 0xb
554 0081 3B .uleb128 0x3b
555 0082 0B .uleb128 0xb
556 0083 49 .uleb128 0x49
557 0084 13 .uleb128 0x13
558 0085 38 .uleb128 0x38
559 0086 0A .uleb128 0xa
560 0087 00 .byte 0x0
561 0088 00 .byte 0x0
562 0089 0C .uleb128 0xc
563 008a 0F .uleb128 0xf
564 008b 00 .byte 0x0
565 008c 0B .uleb128 0xb
566 008d 0B .uleb128 0xb
567 008e 00 .byte 0x0
568 008f 00 .byte 0x0
569 0090 0D .uleb128 0xd
570 0091 21 .uleb128 0x21
571 0092 00 .byte 0x0
572 0093 49 .uleb128 0x49
573 0094 13 .uleb128 0x13
574 0095 2F .uleb128 0x2f
575 0096 0B .uleb128 0xb
576 0097 00 .byte 0x0
577 0098 00 .byte 0x0
578 0099 0E .uleb128 0xe
579 009a 2E .uleb128 0x2e
580 009b 00 .byte 0x0
581 009c 3F .uleb128 0x3f
582 009d 0C .uleb128 0xc
583 009e 03 .uleb128 0x3
584 009f 0E .uleb128 0xe
585 00a0 3A .uleb128 0x3a
586 00a1 0B .uleb128 0xb
587 00a2 3B .uleb128 0x3b
588 00a3 0B .uleb128 0xb
589 00a4 27 .uleb128 0x27
590 00a5 0C .uleb128 0xc
591 00a6 49 .uleb128 0x49
592 00a7 13 .uleb128 0x13
593 00a8 11 .uleb128 0x11
BFIN GAS /tmp/ccQKVwPF.s page 12
594 00a9 01 .uleb128 0x1
595 00aa 12 .uleb128 0x12
596 00ab 01 .uleb128 0x1
597 00ac 40 .uleb128 0x40
598 00ad 06 .uleb128 0x6
599 00ae 00 .byte 0x0
600 00af 00 .byte 0x0
601 00b0 0F .uleb128 0xf
602 00b1 34 .uleb128 0x34
603 00b2 00 .byte 0x0
604 00b3 03 .uleb128 0x3
605 00b4 0E .uleb128 0xe
606 00b5 3A .uleb128 0x3a
607 00b6 0B .uleb128 0xb
608 00b7 3B .uleb128 0x3b
609 00b8 0B .uleb128 0xb
610 00b9 49 .uleb128 0x49
611 00ba 13 .uleb128 0x13
612 00bb 3F .uleb128 0x3f
613 00bc 0C .uleb128 0xc
614 00bd 02 .uleb128 0x2
615 00be 0A .uleb128 0xa
616 00bf 00 .byte 0x0
617 00c0 00 .byte 0x0
618 00c1 10 .uleb128 0x10
619 00c2 35 .uleb128 0x35
620 00c3 00 .byte 0x0
621 00c4 49 .uleb128 0x49
622 00c5 13 .uleb128 0x13
623 00c6 00 .byte 0x0
624 00c7 00 .byte 0x0
625 00c8 00 .byte 0x0
626 .section .debug_pubnames,"",@progbits
627 0000 23000000 .4byte 0x23
628 0004 0200 .2byte 0x2
629 0006 00000000 .4byte .Ldebug_info0
630 000a 79020000 .4byte 0x279
631 000e 48020000 .4byte 0x248
632 0012 6D61696E .string "main"
632 00
633 0017 61020000 .4byte 0x261
634 001b 675F7374 .string "g_state"
634 61746500
635 0023 00000000 .4byte 0x0
636 .section .debug_aranges,"",@progbits
637 0000 1C000000 .4byte 0x1c
638 0004 0200 .2byte 0x2
639 0006 00000000 .4byte .Ldebug_info0
640 000a 04 .byte 0x4
641 000b 00 .byte 0x0
642 000c 0000 .2byte 0x0
643 000e 0000 .2byte 0x0
644 0010 00000000 .4byte .Ltext0
645 0014 12000000 .4byte .Letext0-.Ltext0
646 0018 00000000 .4byte 0x0
647 001c 00000000 .4byte 0x0
648 .section .debug_str,"MS",@progbits,1
BFIN GAS /tmp/ccQKVwPF.s page 13
649 .LASF27:
650 0000 76616C69 .string "valid"
650 6400
651 .LASF15:
652 0006 72657375 .string "result"
652 6C7400
653 .LASF35:
654 000d 474E5520 .string "GNU C 4.3.5"
654 4320342E
654 332E3500
655 .LASF2:
656 0019 73686F72 .string "short int"
656 7420696E
656 7400
657 .LASF30:
658 0023 696E5F6C .string "in_lb"
658 6200
659 .LASF38:
660 0029 6D61696E .string "main"
660 00
661 .LASF39:
662 002e 675F7374 .string "g_state"
662 61746500
663 .LASF20:
664 0036 66756C6C .string "full_size"
664 5F73697A
664 6500
665 .LASF9:
666 0040 6C6F6E67 .string "long long int"
666 206C6F6E
666 6720696E
666 7400
667 .LASF6:
668 004e 6C6F6E67 .string "long int"
668 20696E74
668 00
669 .LASF31:
670 0057 6F75745F .string "out_lb"
670 6C6200
671 .LASF21:
672 005e 61646472 .string "addr"
672 00
673 .LASF26:
674 0063 6E657874 .string "next_descr"
674 5F646573
674 637200
675 .LASF18:
676 006e 745F6C35 .string "t_l502_bf_cmd"
676 30325F62
676 665F636D
676 6400
677 .LASF16:
678 007c 64617461 .string "data_size"
678 5F73697A
678 6500
679 .LASF1:
680 0086 756E7369 .string "unsigned char"
BFIN GAS /tmp/ccQKVwPF.s page 14
680 676E6564
680 20636861
680 7200
681 .LASF0:
682 0094 7369676E .string "signed char"
682 65642063
682 68617200
683 .LASF19:
684 00a0 666C6167 .string "flags"
684 7300
685 .LASF10:
686 00a6 6C6F6E67 .string "long long unsigned int"
686 206C6F6E
686 6720756E
686 7369676E
686 65642069
687 .LASF7:
688 00bd 75696E74 .string "uint32_t"
688 33325F74
688 00
689 .LASF11:
690 00c6 756E7369 .string "unsigned int"
690 676E6564
690 20696E74
690 00
691 .LASF4:
692 00d3 75696E74 .string "uint16_t"
692 31365F74
692 00
693 .LASF32:
694 00dc 745F6864 .string "t_hdma_descr_arr"
694 6D615F64
694 65736372
694 5F617272
694 00
695 .LASF12:
696 00ed 636F6465 .string "code"
696 00
697 .LASF14:
698 00f2 70617261 .string "param"
698 6D00
699 .LASF3:
700 00f8 73686F72 .string "short unsigned int"
700 7420756E
700 7369676E
700 65642069
700 6E7400
701 .LASF13:
702 010b 73746174 .string "status"
702 757300
703 .LASF28:
704 0112 75646174 .string "udata"
704 6100
705 .LASF22:
706 0118 78636E74 .string "xcnt"
706 00
707 .LASF5:
BFIN GAS /tmp/ccQKVwPF.s page 15
708 011d 696E7433 .string "int32_t"
708 325F7400
709 .LASF23:
710 0125 786D6F64 .string "xmod"
710 00
711 .LASF17:
712 012a 64617461 .string "data"
712 00
713 .LASF33:
714 012f 68646D61 .string "hdma"
714 00
715 .LASF37:
716 0134 2F686F6D .string "/home/feda/MIPT/RadioPhotonic_Subserface_radar/ADC_computing/BFfirmware_0"
716 652F6665
716 64612F4D
716 4950542F
716 52616469
717 .LASF29:
718 017e 745F6864 .string "t_hdma_stream_descr"
718 6D615F73
718 74726561
718 6D5F6465
718 73637200
719 .LASF8:
720 0192 6C6F6E67 .string "long unsigned int"
720 20756E73
720 69676E65
720 6420696E
720 7400
721 .LASF24:
722 01a4 79636E74 .string "ycnt"
722 00
723 .LASF34:
724 01a9 745F6C35 .string "t_l502_board_state"
724 30325F62
724 6F617264
724 5F737461
724 746500
725 .LASF25:
726 01bc 796D6F64 .string "ymod"
726 00
727 .LASF36:
728 01c1 7372632F .string "src/main.c"
728 6D61696E
728 2E6300
729 .ident "GCC: (ADI-2014R1-RC2) 4.3.5"
BFIN GAS /tmp/ccQKVwPF.s page 16
DEFINED SYMBOLS
*ABS*:0000000000000000 src/main.c
/tmp/ccQKVwPF.s:13 .text:0000000000000000 _main
/tmp/ccQKVwPF.s:34 board_state:0000000000000000 _g_state
UNDEFINED SYMBOLS
_l502_init
_l502_cmd_check_req
_stream_proc
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/* Blackfin on-chip ROM API
*
* Copyright 2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __BFROM_H__
#define __BFROM_H__
#include <stdint.h>
/* Possible syscontrol action flags */
#define SYSCTRL_READ 0x00000000 /* read registers */
#define SYSCTRL_WRITE 0x00000001 /* write registers */
#define SYSCTRL_SYSRESET 0x00000002 /* perform system reset */
#define SYSCTRL_CORERESET 0x00000004 /* perform core reset */
#define SYSCTRL_SOFTRESET 0x00000006 /* perform core and system reset */
#define SYSCTRL_VRCTL 0x00000010 /* read/write VR_CTL register */
#define SYSCTRL_EXTVOLTAGE 0x00000020 /* VDDINT supplied externally */
#define SYSCTRL_INTVOLTAGE 0x00000000 /* VDDINT generated by on-chip regulator */
#define SYSCTRL_OTPVOLTAGE 0x00000040 /* For Factory Purposes Only */
#define SYSCTRL_PLLCTL 0x00000100 /* read/write PLL_CTL register */
#define SYSCTRL_PLLDIV 0x00000200 /* read/write PLL_DIV register */
#define SYSCTRL_LOCKCNT 0x00000400 /* read/write PLL_LOCKCNT register */
#define SYSCTRL_PLLSTAT 0x00000800 /* read/write PLL_STAT register */
#define SYSCTRL_COLDBOOT 0x40000000 /* when called at cold boot */
#define SYSCTRL_PREBOOT 0x80000000 /* when called from preboot */
typedef struct ADI_SYSCTRL_VALUES {
uint16_t uwVrCtl;
uint16_t uwPllCtl;
uint16_t uwPllDiv;
uint16_t uwPllLockCnt;
uint16_t uwPllStat;
} ADI_SYSCTRL_VALUES;
static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)0xEF000038;
/* We need a dedicated function since we need to screw with the stack pointer
* when resetting. The on-chip ROM will save/restore registers on the stack
* when doing a system reset, so the stack cannot be outside of the chip.
*/
__attribute__((__noreturn__))
static inline void bfrom_SoftReset(void *new_stack)
{
while (1)
/*
* We don't declare the SP as clobbered on purpose, since
* it confuses the heck out of the compiler, and this function
* never returns
*/
__asm__ __volatile__(
"sp = %[stack];"
"jump (%[bfrom_syscontrol]);"
: : [bfrom_syscontrol] "p"(bfrom_SysControl),
"q0"(SYSCTRL_SOFTRESET),
"q1"(0),
"q2"(NULL),
[stack] "p"(new_stack)
);
}
/* OTP Functions */
static uint32_t (* const bfrom_OtpCommand)(uint32_t command, uint32_t value) = (void *)0xEF000018;
static uint32_t (* const bfrom_OtpRead)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001A;
static uint32_t (* const bfrom_OtpWrite)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001C;
/* otp command: defines for "command" */
#define OTP_INIT 0x00000001
#define OTP_CLOSE 0x00000002
/* otp read/write: defines for "flags" */
#define OTP_LOWER_HALF 0x00000000 /* select upper/lower 64-bit half (bit 0) */
#define OTP_UPPER_HALF 0x00000001
#define OTP_NO_ECC 0x00000010 /* do not use ECC */
#define OTP_LOCK 0x00000020 /* sets page protection bit for page */
#define OTP_CHECK_FOR_PREV_WRITE 0x00000080
/* ******************************************************************************************* */
/* */
/* Return Codes for OtpCommand, OtpRead and OtpWrite() routines */
/* */
/* ******************************************************************************************* */
/* Error codes */
#define OTP_SUCCESS 0x0000
/* Error Bits */
#define OTP_MASTER_ERROR 0
#define OTP_WRITE_ERROR 1
#define OTP_READ_ERROR 2
#define OTP_ACC_VIO_ERROR 3
#define OTP_DATA_MULT_ERROR 4
#define OTP_ECC_MULT_ERROR 5
#define OTP_PREV_WR_ERROR 6
#define OTP_SB_DEFECT_ERROR 7
/* Warning Bits */
#define OTP_DATA_SB_WARN 8
#define OTP_ECC_SB_WARN 9
/* ******************************************************************************************* */
/* */
/* Boot block header's bit fields */
/* */
/* ******************************************************************************************* */
#define HDRSGN 0xFF000000
#define HDRCHK 0x00FF0000
#define DMACODE 0x0000000F
/* ******************************************************************************************* */
/* */
/* Boot Flags (part of block header's block code field) */
/* */
/* ******************************************************************************************* */
#define BFLAG_FINAL 0x00008000 /* final block in stream */
#define BFLAG_FIRST 0x00004000 /* first block in stream */
#define BFLAG_INDIRECT 0x00002000 /* load data via intermediate buffer */
#define BFLAG_IGNORE 0x00001000 /* ignore block payload */
#define BFLAG_INIT 0x00000800 /* call initcode routine */
#define BFLAG_CALLBACK 0x00000400 /* call callback routine */
#define BFLAG_QUICKBOOT 0x00000200 /* boot block only when BFLAG_WAKEUP=0 */
#define BFLAG_FILL 0x00000100 /* fill memory with 32-bit argument value */
#define BFLAG_AUX 0x00000020 /* load auxiliary header -- reserved */
#define BFLAG_SAVE 0x00000010 /* save block on power down -- reserved */
/* ******************************************************************************************* */
/* */
/* Boot Flags (global flags for pFlag word) */
/* */
/* ******************************************************************************************* */
#define BFLAG_NORESTORE 0x80000000 /* do not restore MMR register when done */
#define BFLAG_RESET 0x40000000 /* issue system reset when done */
#define BFLAG_RETURN 0x20000000 /* issue RTS instead of jumping to EVT1 vector */
#define BFLAG_NEXTDXE 0x10000000 /* parse stream via Next DXE pointer */
#define BFLAG_WAKEUP 0x08000000 /* WURESET bit was a '1', enable quickboot */
#define BFLAG_SLAVE 0x04000000 /* boot mode is a slave mode */
#define BFLAG_PERIPHERAL 0x02000000 /* boot mode is a peripheral mode */
#define BFLAG_NOAUTO 0x01000000 /* skip automatic device detection */
#define BFLAG_ALTERNATE 0x00800000 /* use alternate boot source */
#define BFLAG_FASTREAD 0x00400000 /* use 0xB command in SPI master mode */
#define BFLAG_TYPE 0x00100000 /* device type (number of address bytes) */
#define BFLAG_TYPE1 0x00000000 /* device type (1 SPI/TWI address bytes, Small Page NAND Flash) */
#define BFLAG_TYPE2 0x00100000 /* device type (2 SPI/TWI address bytes, Large Page NAND Flash) */
#define BFLAG_TYPE3 0x00200000 /* device type (3 SPI/TWI address bytes, NAND reserved) */
#define BFLAG_TYPE4 0x00300000 /* device type (4 SPI/TWI address bytes, NAND reserved) */
#define BFLAG_HDRINDIRECT 0x00080000 /* boot block headers via intermediate buffer */
#define BFLAG_HOOK 0x00040000 /* call hook routine after initialization */
#define BFLAG_TEST 0x00020000 /* factory testing */
/* ******************************************************************************************* */
/* */
/* Callback Flags */
/* */
/* ******************************************************************************************* */
#define CBFLAG_FINAL 0x00000008
#define CBFLAG_FIRST 0x00000004
#define CBFLAG_DIRECT 0x00000001
/* ******************************************************************************************* */
/* */
/* Boot ROM Jump Table Entries */
/* */
/* ******************************************************************************************* */
#define BFROM_FINALINIT 0xEF000002
#define BFROM_PDMA 0xEF000004
#define BFROM_MDMA 0xEF000006
#define BFROM_MEMBOOT 0xEF000008
#define BFROM_SPIBOOT 0xEF00000A
#define BFROM_TWIBOOT 0xEF00000C
#define BFROM_OTPBOOT 0xEF00000E
#define BFROM_NANDBOOT 0xEF000010
#define BFROM_SECURE_ENTRY 0xEF000014
#define BFROM_OTP_ECC 0xEF000016
#define BFROM_OTP_COMMAND 0xEF000018
#define BFROM_OTP_READ 0xEF00001A
#define BFROM_OTP_WRITE 0xEF00001C
#define BFROM_ECC_LUTADDR 0xEF00001E
#define BFROM_BOOTKERNEL 0xEF000020
#define BFROM_GETPORT 0xEF000022
#define BFROM_NMI 0xEF000024
#define BFROM_HWERROR 0xEF000026
#define BFROM_EXCEPTION 0xEF000028
#define BFROM_EMUENTRY 0xEF00002A
#define BFROM_CRC32 0xEF000030
#define BFROM_CRC32POLY 0xEF000032
#define BFROM_CRC32CALLBACK 0xEF000034
#define BFROM_CRC32INITCODE 0xEF000036
#define BFROM_SYSCONTROL 0xEF000038
#if defined(__ADSPBF50x__)
#define BFROM_FLASHPROTECT 0xEF00003A
#define BFROM_FLASHPROTECTINITCODE 0xEF00003C
#endif
/* ******************************************************************************************* */
/* */
/* Flags and Argument for BFROM_FLASHPROTECT routine */
/* */
/* ******************************************************************************************* */
#if defined(__ADSPBF50x__)
#define FLASH_LOCK_CONTROL 0x80000000 /* Controls locking of the upper byte of the FLASH_CONTROL register */
#define FLASH_PROTECT_ENABLE 0x20000000 /* Controls the Vpp Flash Protect signal */
#define FLASH_PROTECT_DISABLE 0x10000000 /* Controls the Vpp Flash Protect signal */
#define FLASH_RESET_DISABLE 0x02000000 /* Controls the Flash Reset signal */
#define FLASH_RESET_ENABLE 0x01000000 /* Controls the Flash Reset signal */
#define FLASH_LOCKDOWN_ENABLE 0x00010000 /* Enables the block lockdown feature */
#define FLASH_LOCKDOWN_START_BLOCK 0x000000FF /* Block number to start the lockdown */
#define FLASH_LOCKDOWN_NUM_BLOCKS 0x0000FF00 /* Number of block to lockdown */
#define FLASH_BLOCK_SHIFT_VAL 0x00000010 /* shift value for FLASH_LOCKDOWN_START_BLOCK to generate the byte address */
#define FLASH_MAIN_BLOCK_SIZE 0x00010000 /* Size in bytes of a main block */
#endif
/* ******************************************************************************************* */
/* */
/* Boot ROM Data Constants with Bit Fields */
/* */
/* ******************************************************************************************* */
#define BK_REVISION 0xEF000040
#define BK_ZEROS 0xEF000048
#define BK_ONES 0xEF00004C
#define BK_DATECODE 0xEF000050
#if defined (_LANGUAGE_C)
# define pBK_REVISION ((const unsigned long *)BK_REVISION)
# define pBK_ZEROS ((const unsigned long *)BK_ZEROS)
# define pBK_ONES ((const unsigned long *)BK_ONES)
# define pBK_DATECODE ((const unsigned long *)BK_DATECODE)
#endif /* _LANGUAGE_C */
#define BK_ID 0xFF000000
#define BK_PROJECT 0x00FF0000
#define BK_VERSION 0x0000FF00
#define BK_UPDATE 0x000000FF
#define BK_YEAR 0xFFFF0000
#define BK_MONTH 0x0000FF00
#define BK_DAY 0x000000FF
/* ******************************************************************************************* */
/* */
/* Predefined OTP Pages to be used with bfrom_OtpRead() */
/* */
/* ******************************************************************************************* */
#define FPS00 0x0004
#define FPS01 0x0005
#define FPS02 0x0006
#define FPS03 0x0007
#define FPS04 0x0008
#define FPS05 0x0009
#define FPS06 0x000A
#define FPS07 0x000B
#define FPS08 0x000C
#define FPS09 0x000D
#define FPS10 0x000E
#define FPS11 0x000F
#define CPS00 0x0010
#define CPS01 0x0011
#define CPS02 0x0012
#define CPS03 0x0013
#define CPS04 0x0014
#define CPS05 0x0015
#define CPS06 0x0016
#define CPS07 0x0017
#define PBS00 0x0018
#define PBS01 0x0019
#define PBS02 0x001A
#define PBS03 0x001B
/* ******************************************************************************************* */
/* */
/* Bit Fields in OTP Half Page PBS00L */
/* */
/* ******************************************************************************************* */
#define OTP_VR_CTL_P 0
#define OTP_VR_CTL_M 0x0000FFFF /* lower 32-bit word */
#define OTP_PLL_CTL_P 16
#define OTP_PLL_CTL_M 0xFFFF0000 /* lower 32-bit word */
#define OTP_PLL_DIV_P 32
#define OTP_PLL_DIV_M 0x000000FF /* upper 32-bit word */
#define OTP_SPI_BAUD_P 40
#define OTP_SPI_BAUD_M 0x00000700 /* upper 32-bit word */
#define OTP_SPI_FASTREAD_P 43
#define OTP_SPI_FASTREAD_M 0x00000800 /* upper 32-bit word */
#define OTP_TWI_CLKDIV_P 44
#define OTP_TWI_CLKDIV_M 0x00001000 /* upper 32-bit word */
#define OTP_TWI_PRESCALE_P 45
#define OTP_TWI_PRESCALE_M 0x0000E000 /* upper 32-bit word */
#define OTP_TWI_TYPE_P 48
#define OTP_TWI_TYPE_M 0x00030000 /* upper 32-bit word */
#define OTP_SET_PLL_P 50
#define OTP_SET_PLL_M 0x00040000 /* upper 32-bit word */
#define OTP_SET_VR_P 51
#define OTP_SET_VR_M 0x00080000 /* upper 32-bit word */
#define OTP_RESETOUT_HWAIT_P 52
#define OTP_RESETOUT_HWAIT_M 0x00100000 /* upper 32-bit word */
#if defined(__ADSPBF54x__)
#define OTP_ALTERNATE_HWAIT_P 53
#define OTP_ALTERNATE_HWAIT_M 0x00200000 /* upper 32-bit word */
/* bit 54 reserved */
#elif defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
/* bits 53 to 54 reserved */
#endif
#define OTP_LOAD_PBS00H_P 55
#define OTP_LOAD_PBS00H_M 0x00800000 /* upper 32-bit word */
#define OTP_LOAD_PBS01L_P 56
#define OTP_LOAD_PBS01L_M 0x01000000 /* upper 32-bit word */
#define OTP_LOAD_PBS01H_P 57
#define OTP_LOAD_PBS01H_M 0x02000000 /* upper 32-bit word */
#define OTP_LOAD_PBS02L_P 58
#define OTP_LOAD_PBS02L_M 0x04000000 /* upper 32-bit word */
#define OTP_LOAD_PBS02H_P 59
#define OTP_LOAD_PBS02H_M 0x08000000 /* upper 32-bit word */
#define OTP_LOAD_PBS03L_P 60
#define OTP_LOAD_PBS03L_M 0x10000000 /* upper 32-bit word */
#define OTP_LOAD_PBS03H_P 61
#define OTP_LOAD_PBS03H_M 0x20000000 /* upper 32-bit word */
#define OTP_INVALID_P 62
#define OTP_INVALID_M 0xC0000000 /* upper 32-bit word */
/* ******************************************************************************************* */
/* */
/* Bit Fields in OTP Half Page PBS00H */
/* */
/* ******************************************************************************************* */
#define OTP_EBIU_AMBCTL_P 0
#define OTP_EBIU_AMBCTL_M 0x0000FFFF /* lower 32-bit word */
#if defined(__ADSPBF54x__)
#define OTP_EBIU_FCTL_P 16
#define OTP_EBIU_FCTL_M 0xFFFF0000 /* lower 32-bit word */
#define OTP_EBIU_MODE_P 32
#define OTP_EBIU_MODE_M 0x000000FF /* upper 32-bit word */
#elif defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
/* bits 16 to 39 reserved */
#endif
#define OTP_EBIU_AMG_P 40
#define OTP_EBIU_AMG_M 0x00000F00 /* upper 32-bit word */
#if defined(__ADSPBF54x__)
#define OTP_EBIU_DEVSEQ_P 44
#define OTP_EBIU_DEVSEQ_M 0x0000F000 /* upper 32-bit word */
#define OTP_EBIU_DEVCFG_P 48
#define OTP_EBIU_DEVCFG_M 0xFFFF0000 /* upper 32-bit word */
#elif defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
/* bits 16 to 63 reserved */
#endif
/* ******************************************************************************************* */
/* */
/* Bit Fields in OTP Half Page PBS01L */
/* */
/* ******************************************************************************************* */
/* bits 0 to 63 reserved */
/* ******************************************************************************************* */
/* */
/* Bit Fields in OTP Half Page PBS01H */
/* */
/* ******************************************************************************************* */
#define OTP_BMODE00_DIS_P 0
#define OTP_BMODE00_DIS_M 0x00000001 /* lower 32-bit word */
#define OTP_BMODE01_DIS_P 1
#define OTP_BMODE01_DIS_M 0x00000002 /* lower 32-bit word */
#define OTP_BMODE02_DIS_P 2
#define OTP_BMODE02_DIS_M 0x00000004 /* lower 32-bit word */
#define OTP_BMODE03_DIS_P 3
#define OTP_BMODE03_DIS_M 0x00000008 /* lower 32-bit word */
#define OTP_BMODE04_DIS_P 4
#define OTP_BMODE04_DIS_M 0x00000010 /* lower 32-bit word */
#define OTP_BMODE05_DIS_P 5
#define OTP_BMODE05_DIS_M 0x00000020 /* lower 32-bit word */
#define OTP_BMODE06_DIS_P 6
#define OTP_BMODE06_DIS_M 0x00000040 /* lower 32-bit word */
#define OTP_BMODE07_DIS_P 7
#define OTP_BMODE07_DIS_M 0x00000080 /* lower 32-bit word */
#define OTP_BMODE08_DIS_P 8
#define OTP_BMODE08_DIS_M 0x00000100 /* lower 32-bit word */
#define OTP_BMODE09_DIS_P 9
#define OTP_BMODE09_DIS_M 0x00000200 /* lower 32-bit word */
#define OTP_BMODE10_DIS_P 10
#define OTP_BMODE10_DIS_M 0x00000400 /* lower 32-bit word */
#define OTP_BMODE11_DIS_P 11
#define OTP_BMODE11_DIS_M 0x00000800 /* lower 32-bit word */
#define OTP_BMODE12_DIS_P 12
#define OTP_BMODE12_DIS_M 0x00001000 /* lower 32-bit word */
#define OTP_BMODE13_DIS_P 13
#define OTP_BMODE13_DIS_M 0x00002000 /* lower 32-bit word */
#define OTP_BMODE14_DIS_P 14
#define OTP_BMODE14_DIS_M 0x00004000 /* lower 32-bit word */
#define OTP_BMODE15_DIS_P 15
#define OTP_BMODE15_DIS_M 0x00008000 /* lower 32-bit word */
#define OTP_NFC_CTL_P 16
#define OTP_NFC_CTL_M 0x00FF0000 /* lower 32-bit word */
#define OTP_START_PAGE_P 24
#define OTP_START_PAGE_M 0xFF000000 /* lower 32-bit word */
/* bits 32 to 63 reserved */
/* ******************************************************************************************* */
/* */
/* Bit Fields in OTP Half Page PBS02L */
/* */
/* ******************************************************************************************* */
#if defined(__ADSPBF54x__)
#define OTP_EBIU_DDRCTL0_P 0
#define OTP_EBIU_DDRCTL0_M 0xFFFFFFFF /* lower 32-bit word */
#define OTP_EBIU_DDRCTL1_P 32
#define OTP_EBIU_DDRCTL1_M 0xFFFFFFFF /* upper 32-bit word */
#elif defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
#define OTP_EBIU_SDGCTL_P 0
#define OTP_EBIU_SDGCTL_M 0xFFFFFFFF /* lower 32-bit word */
#define OTP_EBIU_SDBCTL_P 32
#define OTP_EBIU_SDBCTL_M 0x0000FFFF /* upper 32-bit word */
#define OTP_EBIU_SDRCC_P 48
#define OTP_EBIU_SDRCC_M 0x0FFF0000 /* upper 32-bit word */
/* bits 60 to 62 reserved */
#define OTP_EBIU_POWERON_DUMMY_WRITE_P 63
#define OTP_EBIU_POWERON_DUMMY_WRITE_M 0x80000000 /* upper 32-bit word */
#endif
/* ******************************************************************************************* */
/* */
/* Bit Fields in OTP Half Page PBS02H */
/* */
/* ******************************************************************************************* */
#if defined(__ADSPBF54x__)
#define OTP_EBIU_DDRCTL2L_P 0
#define OTP_EBIU_DDRCTL2L_M 0x0000FFFF /* lower 32-bit word */
#define OTP_EBIU_DDRCTL3L_P 16
#define OTP_EBIU_DDRCTL3L_M 0xFFFF0000 /* lower 32-bit word */
#define OTP_EBIU_DDRQUEL_P 32
#define OTP_EBIU_DDRQUEL_M 0x0000FFFF /* upper 32-bit word */
/* bits 48 to 63 reserved */
#elif defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
/* bits 0 to 63 reserved */
#endif
/* ******************************************************************************************* */
/* */
/* Bit Fields in OTP Half Page PBS03L */
/* */
/* ******************************************************************************************* */
/* bits 0 to 63 reserved */
/* ******************************************************************************************* */
/* */
/* Bit Fields in OTP Half Page PBS03H */
/* */
/* ******************************************************************************************* */
/* bits 0 to 63 reserved */
/* ******************************************************************************************* */
/* */
/* Macros to be used along with _P versions of above bit fields */
/* */
/* ******************************************************************************************* */
#define OTP_OFFSET(x) (((x)>>5)<<2)
#define OTP_BITPOS(x) ((x)&0x1F)
/* ******************************************************************************************* */
/* */
/* Block Cipher Modes of Operation */
/* */
/* ******************************************************************************************* */
#define BLOCK_CIPHER_MODE_ECB 0
#define BLOCK_CIPHER_MODE_CBC 1
#define BLOCK_CIPHER_MODE_OFB 2
#define BLOCK_CIPHER_MODE_CTR 3
/* ******************************************************************************************* */
/* */
/* Flags for AesInit() routines */
/* */
/* ******************************************************************************************* */
#define AES_ENCRYPTION (0x01)
#define AES_DECRYPTION (0x02)
#define AES_BOTH (AES_ENCRYPTION | AES_DECRYPTION)
/* ******************************************************************************************* */
/* */
/* Return Codes for AES routines */
/* */
/* ******************************************************************************************* */
#define AES_SUCCESS 0
#define AES_INVALID_KEY_SIZE -1
#define AES_INVALID_MODE -2
/* ******************************************************************************************* */
/* */
/* Size definitions used in SHA-1 */
/* */
/* ******************************************************************************************* */
#define SHA1_SCRATCH_BUFFER_SIZE 184
#define SHA1_HASH_SIZE 20
/* ******************************************************************************************* */
/* */
/* Instruction ROM Jump Table Entries */
/* */
/* ******************************************************************************************* */
#if defined(__ADSPBF54x__)
#if defined(__SILICON_REVISION__) && (__SILICON_REVISION__==0x1)
#define BFROM_ARC4_INIT 0xFFA14018
#define BFROM_ARC4_CIPHER 0xFFA1401C
#define BFROM_AES_CIPHER 0xFFA14020
#define BFROM_AES_INV_CIPHER 0xFFA14024
#define BFROM_AES_INIT 0xFFA14028
#define BFROM_AES_KEYEXP 0xFFA1402C
#define BFROM_AES_INV_KEYEXP 0xFFA14030
#define BFROM_SHA1_INIT 0xFFA14860
#define BFROM_SHA1_HASH 0xFFA14B6C
#elif defined(__SILICON_REVISION__) && ((__SILICON_REVISION__==0x2) || (__SILICON_REVISION__==0x3) || (__SILICON_REVISION__==0x4))
#define BFROM_ARC4_INIT 0xFFA14018
#define BFROM_ARC4_CIPHER 0xFFA1401C
#define BFROM_AES_CIPHER 0xFFA14020
#define BFROM_AES_INV_CIPHER 0xFFA14024
#define BFROM_AES_INIT 0xFFA14028
#define BFROM_AES_KEYEXP 0xFFA1402C
#define BFROM_AES_INV_KEYEXP 0xFFA14030
#define BFROM_SHA1_INIT 0xFFA14990
#define BFROM_SHA1_HASH 0xFFA14C9C
#else
#define BFROM_ARC4_INIT __arc4_init
#define BFROM_ARC4_CIPHER __arc4_cipher
#define BFROM_AES_CIPHER __aes_cipher
#define BFROM_AES_INV_CIPHER __aes_inv_cipher
#define BFROM_AES_INIT __aes_init
#define BFROM_AES_KEYEXP __aes_keyexp
#define BFROM_AES_INV_KEYEXP __aes_inv_keyexp
#define BFROM_SHA1_INIT __sha1_init
#define BFROM_SHA1_HASH __sha1_hash
#endif /* __SILICON_REVISION__ */
#elif defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
#if defined(__SILICON_REVISION__) && (__SILICON_REVISION__==0x1)
#define BFROM_SHA1_INIT 0xEF001748
#define BFROM_SHA1_HASH 0xEF001A54
#elif defined(__SILICON_REVISION__) && (__SILICON_REVISION__==0x2)
#define BFROM_SHA1_INIT 0xEF001878
#define BFROM_SHA1_HASH 0xEF001B84
#else
#define BFROM_SHA1_INIT __sha1_init
#define BFROM_SHA1_HASH __sha1_hash
#endif /* __SILICON_REVISION__ */
#elif defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
#if defined(__SILICON_REVISION__) && (__SILICON_REVISION__==0x0)
#define BFROM_SHA1_INIT 0xEF001748
#define BFROM_SHA1_HASH 0xEF001A54
#elif defined(__SILICON_REVISION__) && ((__SILICON_REVISION__==0x1) || (__SILICON_REVISION__==0x2))
#define BFROM_SHA1_INIT 0xEF001878
#define BFROM_SHA1_HASH 0xEF001B84
#else
#define BFROM_SHA1_INIT __sha1_init
#define BFROM_SHA1_HASH __sha1_hash
#endif /* __SILICON_REVISION__ */
#elif defined(__ADSPBF51x__)
#if defined(__SILICON_REVISION__) && ((__SILICON_REVISION__==0x0) || (__SILICON_REVISION__==0x1) || (__SILICON_REVISION__==0x2))
#define BFROM_SHA1_INIT 0xEF001878
#define BFROM_SHA1_HASH 0xEF001B84
#else
#define BFROM_SHA1_INIT __sha1_init
#define BFROM_SHA1_HASH __sha1_hash
#endif /* __SILICON_REVISION__ */
#endif /* __ADSPBF5xx__ */
#endif
gcc/ice-100b.rules
+2
View File
@@ -0,0 +1,2 @@
SUBSYSTEM=="usb", ATTRS{idVendor}=="064b", ATTRS{idProduct}=="0225", MODE="0666"
SUBSYSTEM=="usb", ATTRS{idVendor}=="064b", ATTRS{idProduct}=="1225", MODE="0666"
gcc/l502-bf Debug.launch
+59
View File
@@ -0,0 +1,59 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<launchConfiguration type="gdb.app.elf.launchConfigurationType">
<stringAttribute key="bad_container_name" value="/gcc/l502-bf"/>
<stringAttribute key="com.analog.gnu.debug.ui.views.mmr.processor" value="ADSP-BF523"/>
<listAttribute key="com.analog.gnu.debug.ui.views.mmr.tables">
<listEntry value="System Interrupt Controller Register File"/>
<listEntry value="SIC_IMASK0"/>
<listEntry value="###"/>
</listAttribute>
<intAttribute key="com.analog.gnu.debug.ui.views.mmr.viewBase" value="16"/>
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="3"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="true"/>
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<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="set remotetimeout 300"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
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<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
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<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
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<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="bfin-elf-gdb"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="bfin-elf-gdb"/>
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList&gt;&lt;content id=&quot;null-stream_proc-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;flags-out_lb-hdma-null-l502_cmd_check_req-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;null-register_handler-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;null-l502_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;sah-f_descrs[0]-null-isr_sport_dma_tx-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;sah-f_descrs[6]-null-isr_sport_dma_tx-(format)&quot; val=&quot;4&quot;/&gt;&lt;/contentList&gt;"/>
<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;globalVariableList/&gt;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList&gt;&#10;&lt;memoryBlockExpressionItem&gt;&#10;&lt;expression text=&quot;0xc3500&quot;/&gt;&#10;&lt;/memoryBlockExpressionItem&gt;&#10;&lt;/memoryBlockExpressionList&gt;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="build/debug/bin/l502-bf.elf"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="l502-bf"/>
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/l502-bf"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
</listAttribute>
</launchConfiguration>
gcc/l502-bf.ld
+278
View File
@@ -0,0 +1,278 @@
MEMORY
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MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0xc000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_SDRAM : ORIGIN = 0x00000000, LENGTH = 32 * 1024 * 1024
}
/* The default linker script, for single core blackfin standalone executables */
OUTPUT_FORMAT("elf32-bfin", "elf32-bfin", "elf32-bfin")
OUTPUT_ARCH(bfin)
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*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections.
FIXME: Why do we need it? When there is no .bss section, we don't
pad the .data section. */
. = ALIGN( 64 );
__bss_end = .;
} > MEM_L1_DATA_A
. = ALIGN( 64 );
__end = .; PROVIDE (_end = .);
.sdram_noinit (NOLOAD) :
{
*(.sdram_noinit, .sdram_noinit.*)
} > MEM_SDRAM
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo .zdebug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames .zdebug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges .zdebug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames .zdebug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.* .zdebug_info) }
.debug_abbrev 0 : { *(.debug_abbrev .zdebug_abbrev) }
.debug_line 0 : { *(.debug_line .zdebug_line) }
.debug_frame 0 : { *(.debug_frame .zdebug_frame) }
.debug_str 0 : { *(.debug_str .zdebug_str) }
.debug_loc 0 : { *(.debug_loc .zdebug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo .zdebug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames .zdebug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames .zdebug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames .zdebug_typenames) }
.debug_varnames 0 : { *(.debug_varnames .zdebug_varnames) }
/* DWARF 3 */
.debug_pubtypes 0 : { *(.debug_pubtypes .zdebug_pubtypes) }
.debug_ranges 0 : { *(.debug_ranges .zdebug_ranges) }
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
__end = .; PROVIDE (_end = .);
__stack_start = ORIGIN(MEM_L1_SCRATCH);
__stack_end = ORIGIN(MEM_L1_SCRATCH) + 0x1000;
}
gcc/l502-bf_basiccrt.s
+78
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@@ -0,0 +1,78 @@
#include <sys/platform.h>
#include <cplb.h>
#include <sys/anomaly_macros_rtl.h>
#include <defBF533.h>
#include <def_LPBlackfin.h>
.text;
.align 2;
.global __start;
.extern _main;
.type __start, STT_FUNC;
__start:
R7 = 0;
LC0 = R7;
LC1 = R7;
L0 = R7;
L1 = R7;
L2 = R7;
L3 = R7;
I0.L = (ITEST_COMMAND & 0xFFFF);
I0.H = (ITEST_COMMAND >> 16);
I1.L = (DTEST_COMMAND & 0xFFFF);
I1.H = (DTEST_COMMAND >> 16);
R7 = 0;
[I0] = R7;
[I1] = R7;
CSYNC;
SP.L=__stack_end - 12;
SP.H=__stack_end - 12;
FP = SP;
SP += -12;
// Zero bss memory
R0.L = __bss_start;
R0.H = __bss_start;
R1.L = __bss_end;
R1.H = __bss_end;
R2 = R1 - R0;
R1 = 0;
CALL.X _memset;
///////////////from PRM/////////////////////////////////////
P0.L = (EVT15 & 0xFFFF) ; /* Point to IVG15 in Event Vector Table */
P0.H = ((EVT15 >> 16) & 0xFFFF) ;
P1.L = START; /* Point to start of User code */
P1.H = START;
[P0] = P1 ; /* Place the address of START in IVG15 of EVT */
P0.L = (IMASK & 0xFFFF) ;
R0 = [P0] ;
R1.L = (EVT_IVG15 & 0xFFFF) ;
R0 = R0 | R1 ;
[P0] = R0 ; /* Set (enable) IVG15 bit in IMASK register */
RAISE 15 ; /* Invoke IVG15 interrupt */
P0.L = WAIT_HERE ;
P0.H = WAIT_HERE ;
RETI = P0 ; /* RETI loaded with return address */
RTI ; /* Return from Reset Event */
WAIT_HERE : /* Wait here till IVG15 interrupt is serviced */
JUMP WAIT_HERE ;
START: /* IVG15 vectors here */
/* Enables interrupts and saves return address to stack */
[--SP] = RETI ;
///////////////from PRM/////////////////////////////////////
[--SP]=R0;
[--SP]=R0;
FP = SP;
SP += -12;
CALL.X _main;
NOP;
__end:
IDLE;
JUMP __end;
gcc/l502_sdram_noinit.h
+1
View File
@@ -0,0 +1 @@
__attribute__((section(".sdram_noinit")))
makefile
+169
View File
@@ -0,0 +1,169 @@
BUILDDIR = build
CONFIG ?= release
CONFIGDIR = $(BUILDDIR)/$(CONFIG)
OBJDIR = $(CONFIGDIR)/objs
LSTDIR = $(CONFIGDIR)/lst
DEPDIR = $(CONFIGDIR)/.dep
TRGT = bfin-elf-
CC = $(TRGT)gcc
CP = $(TRGT)objcopy
AS = $(TRGT)gcc -x assembler-with-cpp
LDR = $(TRGT)ldr
LDRFLAGS = -T BF527
MCU = bf523-0.2
# List all default C defines here, like -D_DEBUG=1
DDEFS =
# List all default ASM defines here, like -D_DEBUG=1
DADEFS =
# List all default directories to look for include files here
DINCDIR =
# List the default directory to look for the libraries here
DLIBDIR =
# List all default libraries here
DLIBS =
#
# End of default section
##############################################################################################
##############################################################################################
# Start of user section
#
# Define project name here
PROJECT = l502-BFfirmware0
# Define linker script file here
LDSCRIPT= gcc/l502-bf.ld
BINDIR = $(CONFIGDIR)/bin
RESULT_FILES = $(BINDIR)/$(PROJECT).elf $(BINDIR)/$(PROJECT).ldr
# List all user C define here, like -D_DEBUG=1
UDEFS = NDEBUG CLOCK_INIT_CB
ifeq ($(CONFIG), debug)
UDEFS += __DEBUG
OPT = -O0
else
OPT = -O3
endif
# List C source files here
SRC = src/main.c \
src/l502_init.c \
src/l502_fpga.c \
src/l502_sport_tx.c \
src/l502_stream.c \
src/l502_async.c \
src/l502_cmd.c \
src/l502_hdma.c \
src/l502_params.c \
src/l502_tests.c \
src/l502_user_process.c
# List ASM source files here
ASRC = gcc/l502-bf_basiccrt.s
# List all user directories here
UINCDIR = src gcc
# List the user directory to look for the libraries here
# List all user libraries here
ULIBS =
#
# End of user defines
##############################################################################################
INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR))
LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
DEFS = $(patsubst %,-D%,$(DDEFS) $(UDEFS)) # = $(DDEFS) $(UDEFS)
ADEFS = $(DADEFS) $(UADEFS)
#OBJS = $(ASRC:.s=.o) $(SRC:.c=.o)
OBJS = $(addprefix $(OBJDIR)/, $(notdir $(sort $(SRC:.c=.o))))
AOBJS = $(addprefix $(OBJDIR)/, $(notdir $(sort $(ASRC:.s=.o))))
LIBS = $(DLIBS) $(ULIBS)
MCFLAGS = -mcpu=$(MCU)
ASFLAGS = $(MCFLAGS) -g -mthumb -gdwarf-2 -Wa,-amhls=$(<:.s=.lst) $(ADEFS)
#-gdwarf-2
ANOMALY_FLAGS = -mspecld-anomaly -mcsync-anomaly
CPFLAGS = $(MCFLAGS) $(OPT) $(ANOMALY_FLAGS) -std=gnu99 -g -Wall -Wstrict-prototypes -Wa,-ahlms=$(addprefix $(LSTDIR)/, $(notdir $(@:.o=.lst))) $(DEFS)
LDFLAGS = $(MCFLAGS) -T$(LDSCRIPT) -nostartfiles -N -Wl,-Map=$(BINDIR)/$(PROJECT).map,--cref,--gc-sections $(LIBDIR) -lm
#
# Generate dependency information
CPFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
#bfin-elf-gcc $(CPFLAGS) -I . $(INCDIR) $(LDFLAGS) $(SRC) -o bf-test.elf
.PHONY: all clean prj dirs
.SECONDEXPANSION:
all: dirs $(RESULT_FILES)
$(OBJS) : $$(filter %/$$(basename $$(notdir $$@)).c, $$(SRC)) ##$$(patsubst %.o,%.c, $$@)
$(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@
$(AOBJS) : $(ASRC)
$(AS) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@
$(BINDIR)/$(PROJECT).elf: $(OBJS) $(AOBJS) $(LDSCRIPT)
$(CC) $(OBJS) $(AOBJS) $(LDFLAGS) $(LIBS) -o $@
$(BINDIR)/$(PROJECT).ldr: $(BINDIR)/$(PROJECT).elf
$(LDR) $(LDRFLAGS) -c $@ $<
dirs: $(BUILDDIR) $(CONFIGDIR) $(DEPDIR) $(OBJDIR) $(LSTDIR) $(BINDIR)
$(BINDIR):
mkdir $(BINDIR)
$(LSTDIR):
mkdir $(LSTDIR)
$(OBJDIR):
mkdir $(OBJDIR)
$(BUILDDIR):
mkdir $(BUILDDIR)
$(CONFIGDIR):
mkdir $(CONFIGDIR)
$(DEPDIR):
mkdir $(DEPDIR)
clean:
-rm -fR $(CONFIGDIR)
-include $(wildcard $(DEPDIR)/*)
src/l502_async.c
+43
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@@ -0,0 +1,43 @@
/***************************************************************************//**
@addtogroup async_io
@{
@file l502_async.c
Ôàéë ñîäåðæèò ðåàëèçàöèþ ôóíêöèé äëÿ àñèíõðîííîãî ââîäà/âûâîäà
(ïîêà òîëüêî âûâîäà)
******************************************************************************/
#include <stdlib.h>
#include "l502_cmd.h"
#include "l502_global.h"
#include "l502_fpga.h"
#include "l502_defs.h"
#include "l502_async.h"
#include "l502_fpga_regs.h"
void async_dac_out(uint8_t ch, int32_t val) {
val &= 0xFFFF;
if (ch==L502_DAC_CH1) {
val |= L502_STREAM_OUT_WORD_TYPE_DAC1;
} else {
val |= L502_STREAM_OUT_WORD_TYPE_DAC2;
}
fpga_reg_write(L502_REGS_IOHARD_ASYNC_OUT, val);
}
void async_dout(uint32_t val, uint32_t msk) {
static uint32_t last_out = L502_DIGOUT_WORD_DIS_H | L502_DIGOUT_WORD_DIS_L;
if (msk != 0) {
val &= ~msk;
val |= last_out & msk;
}
val &= 0xFFFF;
fpga_reg_write(L502_REGS_IOHARD_ASYNC_OUT, val);
last_out = val;
}
/** @} */
src/l502_async.h
+46
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@@ -0,0 +1,46 @@
/** @defgroup async_io Асинхронный ввод-вывод */
/***************************************************************************//**
@addtogroup async_io
@{
@file l502_async.h
Файл содержит описания функций асинхронного ввода-вывода
******************************************************************************/
#ifndef L502_ASYNC_H_
#define L502_ASYNC_H_
#include <stdint.h>
/** Первый канал ЦАП при выводе через async_dac_out() */
#define L502_DAC_CH1 0
/** Второй канал ЦАП при выводе через async_dac_out() */
#define L502_DAC_CH2 1
/***************************************************************************//**
@brief Асинхронный вывод на один из каналов ЦАП
Функция выполняет асинхронный вывод кода на ЦАП
@param[in] ch Канал ЦАП (#L502_DAC_CH1 или #L502_DAC_CH2)
@param[in] val Код ЦАП (действительны только младшие 16 бит)
******************************************************************************/
void async_dac_out(uint8_t ch, int32_t val);
/***************************************************************************//**
@brief Асинхронный вывод на цифровые линии
Функция выполняет асинхронный вывод кода на цифровые линии с возможностью указать
линии, которые не должны изменяться
@param[in] val биты 0-15 - значения линий на вывод + возможно перевести
половину портов в 3-е состояние с помощью флагов из
#t_l502_digout_word_flags
@param[in] msk Если в маске установлены некоторые биты, то соответствующие
биты из val не влияют, а сохраняются предыдущие значения
******************************************************************************/
void async_dout(uint32_t val, uint32_t msk);
#endif
/** @} */
src/l502_bf_cmd_defs.h
+167
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@@ -0,0 +1,167 @@
/*********************************************************************//**
@addtogroup cmd_process
@{
@file l502_bf_cmd_defs.h Файл содержит определения,
которые используются для передачи команд от ПК в DSP
(определения команд, их параметров, результатов выполнения)
@date 28.03.2012
@author Borisov Alexey <borisov@lcard.ru>
*************************************************************************/
#ifndef L502_BF_CMD_DEFS_H_
#define L502_BF_CMD_DEFS_H_
/** Максимальный размер данных, передавемых с командой в 32-битных словах */
#define L502_BF_CMD_DATA_SIZE_MAX (1024)
/** Статус команд управления сигнальным процессором */
typedef enum {
L502_BF_CMD_STATUS_IDLE = 0x0, /**< Начальное состояние (команда вообщен не выполнялась) */
L502_BF_CMD_STATUS_REQ = 0x5A01, /**< Передан запрос на обработку команды от ПК*/
L502_BF_CMD_STATUS_PROGRESS = 0x5A02, /**< Сигнальный процессор начал обработку команды */
L502_BF_CMD_STATUS_DONE = 0x5A03 /**< Команда выполнена. Результат выполнения в поле ret_code */
} t_l502_bf_cmd_status;
/** Коды команд управления сигнальным процессором */
typedef enum {
L502_BF_CMD_CODE_TEST = 0x01, /**< Запуск теста (параметр определяет тип теста) */
L502_BF_CMD_CODE_SET_PARAM = 0x02, /**< Установить параметр (код параметра в поле param) */
L502_BF_CMD_CODE_GET_PARAM = 0x03, /**< Прочитать текущее значение параметра */
L502_BF_CMD_CODE_CONFIGURE = 0x04, /**< Сконфигурировать модуль в соответствии с ранее установленными параметрами */
L502_BF_CMD_CODE_STREAM_EN = 0x05, /**< Разрешение потоков ввода/вывода */
L502_BF_CMD_CODE_STREAM_DIS = 0x06, /**< Запрещение потоков ввода/вывода */
L502_BF_CMD_CODE_STREAM_START = 0x07, /**< Запуск потоков ввода/вывода */
L502_BF_CMD_CODE_STREAM_STOP = 0x08, /**< Останов потоков ввода/вывода */
L502_BF_CMD_CODE_PRELOAD = 0x09, /**< Предзагрузка данных на ЦАП */
L502_BF_CMD_CODE_ASYNC_OUT = 0x10, /**< Асинхронный вывод (куда - зависит от параметра) */
L502_BF_CMD_CODE_ASYNC_DIG_IN = 0x11, /**< Асинхронный ввод с цифровых линий */
L502_BF_CMD_CODE_ADC_GET_FRAME = 0x12, /**< Асинхронный ввод карда АЦП */
L502_BF_CMD_CODE_FPGA_REG_WR = 0x13, /**< Запись в регистр FPGA (param --- адрес регистра, data0 --- значение) */
L502_BF_CMD_CODE_FPGA_REG_RD = 0x14, /**< Чтение из регистра FPGA (param --- адрес регистра, ответ: resp0 --- значение) */
L502_BF_CMD_CODE_GET_OUT_STATUS= 0x15, /**< Получение флагов статуса вывода */
} t_l502_bf_cmd_code;
#define L502_BF_CMD_CODE_USER 0x8000U /**< Код, с которого начинаются пользовательские команды */
/** @brief Варианты тестов
Коды тестов, передающиеся в параметре команды #L502_BF_CMD_CODE_TEST */
typedef enum {
L502_BF_CMD_TEST_STOP = 0x00, /**< Останов выполняемого теста */
L502_BF_CMD_TEST_GET_RESULT = 0x01, /**< Получение результата теста */
L502_BF_CMD_TEST_ECHO = 0x10, /**< Тест эхо - возвращает те же данные что передавались */
L502_BF_CMD_TEST_SPORT = 0x11, /**< Тест интерфейса SPORT в кольцевом режиме */
L502_BF_CMD_TEST_SDRAM = 0x12, /**< Тест SDRAM памяти */
L502_BF_CMD_TEST_SPI = 0x13 /**< Тест интерфейса SPI */
} t_l502_bf_test_code;
/** @brief Устанавливаемые параметры
Коды пареметров, устанавливаемых командой #L502_BF_CMD_CODE_SET_PARAM или
получаемых с помщью команды #L502_BF_CMD_CODE_GET_PARAM */
typedef enum {
L502_BF_PARAM_FIRM_VERSION = 0x00, /**< Версия прошивки - 4 байта */
L502_BF_PARAM_STREAM_MODE = 0x01, /**< Режим работы (запущен поток или нет) */
L502_BF_PARAM_ENABLED_STREAMS = 0x02, /**< Какие потоки разрешены */
L502_BF_PARAM_MODULE_INFO = 0x03, /**< Запись информации о модуле */
L502_BF_PARAM_IN_BUF_SIZE = 0x10, /**< Размер буфера на преием */
L502_BF_PARAM_CYCLE_BUF_SIZE = 0x11, /**< Размер буфера для записи циклического сигнала */
L502_BF_PARAM_LCH_CNT = 0x20, /**< Количество логических каналов в таблице */
L502_BF_PARAM_LCH = 0x21, /**< Параметры логического канала */
L502_BF_PARAM_ADC_FREQ_DIV = 0x22, /**< Делитель частоты АЦП */
L502_BF_PARAM_REF_FREQ_SRC = 0x23, /**< Выбор опорной частоты */
L502_BF_PARAM_ADC_FRAME_DELAY = 0x24, /**< Значение межкадровой задержки */
L502_BF_PARAM_SYNC_MODE = 0x25, /**< Режим синхронизации */
L502_BF_PARAM_SYNC_START_MODE = 0x26, /**< Условие запуска синхронных потоков сбора данных */
L502_BF_PARAM_ADC_COEF = 0x27, /**< Установка коэффициентов для заданного диапазона АЦП */
L502_BF_PARAM_DAC_COEF = 0x28, /**< Установка коэффициентов для заданного канала ЦАП */
L502_BF_PARAM_DIN_FREQ_DIV = 0x30, /**< Делитель частоты цифрового ввода */
L502_BF_PARAM_DAC_FREQ_DIV = 0x31, /**< Делитель частоты вывода на ЦАП */
L502_BF_PARAM_IN_STEP_SIZE = 0x32, /**< Шаг для обработки входных данных */
L502_BF_PARAM_IN_STREAM_MODE = 0x100 /**< Режим работы потока на ввод */
} t_l502_bf_params;
/** @brief Тип асинхронного вывода
Код, задающий в параметре команды команды #L502_BF_CMD_CODE_ASYNC_OUT,
куда должно выводится передаваемое значение */
typedef enum {
L502_BF_CMD_ASYNC_TYPE_DOUT = 0x0, /**< Вывод на цифровые линии */
L502_BF_CMD_ASYNC_TYPE_DAC1 = 0x1, /**< Вывод на первый канал ЦАП */
L502_BF_CMD_ASYNC_TYPE_DAC2 = 0x2 /**< Вывод на второй канал ЦАП */
} t_l502_bf_cmd_async_type;
/** Коды завершения команд */
typedef enum {
L502_BF_ERR_SUCCESS = 0, /**< Команда выполнена успешно */
L502_BF_ERR_FIRST_CODE = -512, /**< Код ошибки, с которого начинаются отсальные коды.
Используется, чтобы разделить на верхнем уровне ошибки библиотеки и
возвращенные сигнальным процессором */
L502_BF_ERR_UNSUP_CMD = -512, /**< Неизвестный код команды */
L502_BF_ERR_CMD_OVERRUN = -513, /**< Пришла команда до того, как была завершена предыдущая */
L502_BF_ERR_INVALID_CMD_PARAMS = -514, /**< Неверное значение параметра команды */
L502_BF_ERR_INSUF_CMD_DATA = -515, /**< Недостаточное кол-во данных передано с командой */
L502_BF_ERR_STREAM_RUNNING = -516, /**< Команда не допустима при запущеном сборе, а сбор запущен */
L502_BF_ERR_STREAM_STOPPED = -517, /**< Команда допустима только при запущеном сборе, а сбор остановлен */
L502_BF_ERR_NO_TEST_IN_PROGR = -518, /**< Сейчас не выполняется никакого теста */
L502_BF_ERR_TEST_VALUE = -519 /**< Считано неверное значение при выполнении теста */
} t_l502_bf_err_code;
/** Режим работы сигнального процессора */
typedef enum {
L502_BF_MODE_IDLE = 0, /**< Ждущий режим, поток не запущен */
L502_BF_MODE_STREAM = 1, /**< Запущены потоки ввода-вывода */
L502_BF_MODE_TEST = 2 /**< Тестовый режим */
} t_l502_bf_mode;
/** Возможности, поддерживаемые прошивкой blackfin */
typedef enum {
L502_BF_FEATURE_FPGA_REG_ACCESS = 0x1, /**< Признак, что реализованы команды
прямого доступа к регистрам FPGA */
L502_BF_FEATURE_OUT_STATUS_FLAGS = 0x2 /**< Признак, что реализована команда
#L502_BF_CMD_CODE_GET_OUT_STATUS */
} t_l502_bf_features;
/** @brief Параметры команды
Структура описывает расположение полей в области памяти BlackFin, используемой
для передачи команд между персональным компьютером и сигнальным процессором */
typedef struct {
uint16_t code; /**< Код команды из #t_l502_bf_cmd_code */
uint16_t status; /**< Статус выполнения - в обработчике не изменяется */
uint32_t param; /**< Параметр команды */
int32_t result; /**< Код результата выполнения команды */
uint32_t data_size; /**< Количество данных, переданных с командой или возвращенных с ответом в 32-битных словах */
uint32_t data[L502_BF_CMD_DATA_SIZE_MAX]; /**< Данные, передаваемые с командой и/или в качестве результата */
} t_l502_bf_cmd;
/** @brief Результат выполнения теста
Структура описывает параметры выполняемого теста, возвращаемые в качестве
данных на команду #L502_BF_CMD_CODE_TEST с параметром
#L502_BF_CMD_TEST_GET_RESULT */
typedef struct {
uint32_t test; /**< Номер выполняемого теста */
uint32_t run; /**< Признак, запущен ли сейчас тест */
uint32_t stage; /**< Этап выполнения теста */
uint32_t cntr; /**< Счетчик - сколько раз прошел тест */
int32_t err; /**< Код ошибки выполнения теста */
uint32_t last_addr; /**< Последний используемый адрес */
uint32_t last_wr; /**< Последнее записанное значение */
uint32_t last_rd; /**< Последнее считанное значение */
} t_l502_bf_test_res;
/** @} */
#endif
src/l502_cdefs.h
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/** @file l502_cdefs.h
Ôàéë îïðåäåëÿåò íàáîð ìàêðîñîâ äëÿ âûïîëíåíèÿ îïåðàöèé, çàâèñÿùèé îò
êîìïèëÿòîðà (VisualDSP èëè GCC) */
#ifndef L502_CDEFS_H
#define L502_CDEFS_H
/** Ìàêðîñ äëÿ ïîìåùåíèÿ ïåðåìåííîé èëè ôóíêöèè â îïðåäåëåííóþ ñåêöèþ */
#ifdef __GNUC__
#define SECTION(sect, member) member __attribute__((section(sect)))
#else
#define SECTION(sect, member) section(sect) member
#endif
/** Ìàðîñ äëÿ ïîìåùåíèÿ ïåðåìåííîé â íåèíèöèàëèçèðóåìóþ îáëàñòü SDRAM */
#ifdef __GNUC__
#define MEM_SDRAM_NOINIT(variable) SECTION(".sdram_noinit", variable)
#else
#define MEM_SDRAM_NOINIT(variable) section("sdram_noinit", NO_INIT) variable
#endif
/** Ìàêðîñ äëÿ îïèñàíèÿ îáðàáîò÷èêà ïðåðûâàíèé */
#ifdef __GNUC__
#define ISR(handler) __attribute__((interrupt_handler,nesting)) void handler(void)
#else
#define ISR(handler) EX_INTERRUPT_HANDLER(handler)
#endif
/** Ìàêðîñ äëÿ ðåãèñòðàöèè îáðàáîò÷èêà ïðåðûâàíèé */
#ifdef __GNUC__
#define REGISTER_ISR(ivg, isr) do { \
int i=0; \
ssync(); \
*pEVT##ivg = isr; \
ssync(); \
asm volatile ("cli %0; bitset (%0, %1); sti %0; csync;": "+d"(i) : "i"(ivg)); \
} while(0)
#else
#define REGISTER_ISR(ivg, isr) register_handler(ik_ivg##ivg, isr)
#endif
#endif // L502_CDEFS_H
src/l502_cmd.c
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/***************************************************************************//**
@addtogroup cmd_process
@{
@file l502_cmd.c
Ôàéë ñîäåðæèò ëîãèêó îáðàáîòêè êîìàíä îò ÏÊ, ïåðåäàííûõ ÷åðåç
HostDMA â BlackFin.
Äëÿ êàæäîãî êîäà êîìàíäû â òàáëèöå f_cmd_tbl çàäàíà ôóíêöèÿ äëÿ
îáðàáîòêè êîìàíäû. Åñëè â òàáëèöå êîä êîìàíäû íå íàéäåí,
òî âîçâðàùàåòñÿ îøèáêà. Äëÿ ïîëüçîâàòåëüñêèõ êîìàíä
âñåãäà âûçûâàåòñÿ usr_cmd_process().
*******************************************************************************/
#include "l502_global.h"
#include "l502_cmd.h"
#include "l502_stream.h"
#include "l502_params.h"
#include "l502_user_process.h"
#include "l502_async.h"
#include "l502_sport_tx.h"
#include <string.h>
#include <cdefBF523.h>
#include <sys/exception.h>
#include <ccblkfn.h>
#include "l502_fpga.h"
extern void l502_cmd_test(t_l502_bf_cmd *cmd);
static void f_cmd_set_param(t_l502_bf_cmd *cmd);
static void f_cmd_get_param(t_l502_bf_cmd *cmd);
static void f_cmd_config(t_l502_bf_cmd *cmd);
static void f_cmd_streams_start(t_l502_bf_cmd *cmd);
static void f_cmd_stream_stop(t_l502_bf_cmd *cmd);
static void f_cmd_preload(t_l502_bf_cmd *cmd);
static void f_cmd_stream_enable(t_l502_bf_cmd *cmd);
static void f_cmd_stream_disable(t_l502_bf_cmd *cmd);
static void f_cmd_async_out(t_l502_bf_cmd *cmd);
static void f_cmd_fpga_reg_wr(t_l502_bf_cmd *cmd);
static void f_cmd_fpga_reg_rd(t_l502_bf_cmd *cmd);
static void f_cmd_get_out_status(t_l502_bf_cmd *cmd);
/* Òèï, îïèñûâàþùèé ôóíêöèþ îáðàáîòêè êîíêðåòíîé êîìàíäû */
typedef void (*t_cmd_func)(t_l502_bf_cmd* cmd);
static const uint32_t f_regaddr_k[L502_ADC_RANGE_CNT] = {L502_REGS_IOARITH_K10,
L502_REGS_IOARITH_K5,
L502_REGS_IOARITH_K2,
L502_REGS_IOARITH_K1,
L502_REGS_IOARITH_K05,
L502_REGS_IOARITH_K02};
static const uint32_t f_regaddr_offs[L502_ADC_RANGE_CNT] = {L502_REGS_IOARITH_B10,
L502_REGS_IOARITH_B5,
L502_REGS_IOARITH_B2,
L502_REGS_IOARITH_B1,
L502_REGS_IOARITH_B05,
L502_REGS_IOARITH_B02};
static volatile uint8_t f_cmd_req=0;
/* òàáëèöà ñ ñîîòâåòñòâèåì êîäîâ êîìàíä è ôóíêöèé äëÿ èõ âûïîëíåíèÿ */
static const struct {
uint32_t cmd_code;
t_cmd_func start;
} f_cmd_tbl[] = {
{L502_BF_CMD_CODE_TEST, l502_cmd_test},
{L502_BF_CMD_CODE_SET_PARAM, f_cmd_set_param},
{L502_BF_CMD_CODE_GET_PARAM, f_cmd_get_param},
{L502_BF_CMD_CODE_CONFIGURE, f_cmd_config},
{L502_BF_CMD_CODE_STREAM_START, f_cmd_streams_start},
{L502_BF_CMD_CODE_STREAM_STOP , f_cmd_stream_stop},
{L502_BF_CMD_CODE_PRELOAD, f_cmd_preload},
{L502_BF_CMD_CODE_STREAM_EN, f_cmd_stream_enable},
{L502_BF_CMD_CODE_STREAM_DIS, f_cmd_stream_disable},
{L502_BF_CMD_CODE_ASYNC_OUT, f_cmd_async_out},
{L502_BF_CMD_CODE_FPGA_REG_WR, f_cmd_fpga_reg_wr},
{L502_BF_CMD_CODE_FPGA_REG_RD, f_cmd_fpga_reg_rd},
{L502_BF_CMD_CODE_GET_OUT_STATUS, f_cmd_get_out_status},
};
void l502_cmd_done(int32_t result, uint32_t* data, uint32_t size) {
g_state.cmd.result = result;
g_state.cmd.data_size = size;
if (size && (data!=g_state.cmd.data))
memmove((void*)g_state.cmd.data, data, size*sizeof(data[0]));
g_state.cmd.status = L502_BF_CMD_STATUS_DONE;
}
void l502_cmd_start(t_l502_bf_cmd* cmd) {
uint32_t i, fnd;
if (cmd->code & L502_BF_CMD_CODE_USER) {
usr_cmd_process(cmd);
} else {
for (i=0, fnd=0; !fnd && (i < sizeof(f_cmd_tbl)/sizeof(f_cmd_tbl[0])); i++) {
if (cmd->code == f_cmd_tbl[i].cmd_code) {
fnd = 1;
f_cmd_tbl[i].start(cmd);
}
}
if (!fnd)
l502_cmd_done(L502_BF_ERR_UNSUP_CMD, NULL, 0);
}
}
void l502_cmd_check_req(void) {
if (f_cmd_req == 1) {
f_cmd_req=0;
l502_cmd_start((void*)&g_state.cmd);
}
}
void l502_cmd_set_req(void) {
f_cmd_req = 1;
g_state.cmd.status = L502_BF_CMD_STATUS_PROGRESS;
}
static void f_cmd_streams_start(t_l502_bf_cmd *cmd) {
l502_cmd_done(streams_start(), NULL, 0);
}
static void f_cmd_stream_stop(t_l502_bf_cmd *cmd) {
l502_cmd_done(streams_stop(), NULL, 0);
}
static void f_cmd_config(t_l502_bf_cmd *cmd) {
l502_cmd_done(configure(), NULL, 0);
}
static void f_cmd_preload(t_l502_bf_cmd *cmd) {
l502_cmd_done(stream_out_preload(), NULL, 0);
}
static void f_cmd_stream_enable(t_l502_bf_cmd *cmd) {
l502_cmd_done(stream_enable(cmd->param), NULL, 0);
}
static void f_cmd_stream_disable(t_l502_bf_cmd *cmd) {
l502_cmd_done(stream_disable(cmd->param), NULL, 0);
}
static void f_cmd_async_out(t_l502_bf_cmd *cmd) {
int32_t err = 0;
if (cmd->data_size < 1) {
err = L502_BF_ERR_INSUF_CMD_DATA;
} else {
switch (cmd->param) {
case L502_BF_CMD_ASYNC_TYPE_DOUT:
async_dout(cmd->data[0], cmd->data_size >= 2 ? cmd->data[1] : 0);
break;
case L502_BF_CMD_ASYNC_TYPE_DAC1:
async_dac_out(L502_DAC_CH1, cmd->data[0]);
break;
case L502_BF_CMD_ASYNC_TYPE_DAC2:
async_dac_out(L502_DAC_CH2, cmd->data[0]);
break;
default:
err = L502_BF_ERR_INVALID_CMD_PARAMS;
break;
}
}
l502_cmd_done(err, NULL, 0);
}
static void f_cmd_fpga_reg_wr(t_l502_bf_cmd *cmd) {
int32_t err = 0;
if (cmd->data_size < 1) {
err = L502_BF_ERR_INSUF_CMD_DATA;
} else if ((cmd->param & 0xFFFF0000) != 0) {
err = L502_BF_ERR_INVALID_CMD_PARAMS;
} else {
fpga_reg_write(cmd->param, cmd->data[0]);
}
l502_cmd_done(err, NULL, 0);
}
static void f_cmd_fpga_reg_rd(t_l502_bf_cmd *cmd) {
int32_t err = 0;
uint32_t val;
if ((cmd->param & 0xFFFF0000) != 0) {
err = L502_BF_ERR_INVALID_CMD_PARAMS;
} else {
val = fpga_reg_read(cmd->param);
}
l502_cmd_done(err, &val, 1);
}
static void f_cmd_get_out_status(t_l502_bf_cmd *cmd) {
uint32_t val = sport_tx_out_status();
l502_cmd_done(0, &val, 1);
}
/* Óñòàíîâêà ðàçëè÷íûõ ïàðàìåòðîâ.
Êîä ïàðàìåòðà îïðåäåëÿåòñÿ ïî cmd->param, çíà÷åíèå áåðåòñÿ èç cmd->data
â ñîîòâåòñòâèè ñ ïàðàìåòðîì */
static void f_cmd_set_param(t_l502_bf_cmd *cmd) {
int32_t err = g_mode != L502_BF_MODE_IDLE ? L502_BF_ERR_STREAM_RUNNING :
cmd->data_size < 1 ? L502_BF_ERR_INSUF_CMD_DATA : 0;
if (!err) {
switch (cmd->param) {
case L502_BF_PARAM_MODULE_INFO:
if (cmd->data_size > 0) {
g_module_info.devflags = cmd->data[0];
}
if (cmd->data_size > 1) {
g_module_info.fpga_ver = cmd->data[1] & 0xFFFF;
g_module_info.plda_ver = (cmd->data[1]>>16) & 0xFF;
}
break;
case L502_BF_PARAM_LCH_CNT:
err = params_set_lch_cnt(cmd->data[0]);
break;
case L502_BF_PARAM_LCH:
/* ïàðàìåòðû: 0 - èíäåêñ, 1 - ôèç êàíàë, 2 - ðåæèì, 3 - äèàïàçîí, 4 - óñðåäåíåíèå */
if (cmd->data_size < 5) {
err = L502_BF_ERR_INSUF_CMD_DATA;
} else {
err = params_set_lch(cmd->data[0], cmd->data[1], (t_l502_lch_mode)cmd->data[2],
(t_l502_adc_range)cmd->data[3], cmd->data[4],
cmd->data_size>5 ? cmd->data[5] : 0);
}
break;
case L502_BF_PARAM_ADC_FREQ_DIV:
err = params_set_adc_freq_div(cmd->data[0]);
break;
case L502_BF_PARAM_REF_FREQ_SRC:
err = params_set_ref_freq(cmd->data[0]);
break;
case L502_BF_PARAM_ADC_FRAME_DELAY:
err = params_set_adc_interframe_delay(cmd->data[0]);
break;
case L502_BF_PARAM_SYNC_MODE:
err = params_set_sync_mode((t_l502_sync_mode)cmd->data[0]);
break;
case L502_BF_PARAM_SYNC_START_MODE:
err = params_set_sync_start_mode((t_l502_sync_mode)cmd->data[0]);
break;
case L502_BF_PARAM_DIN_FREQ_DIV:
err = params_set_din_freq_div(cmd->data[0]);
break;
case L502_BF_PARAM_DAC_FREQ_DIV:
err = params_set_dac_freq_div(cmd->data[0]);
break;
case L502_BF_PARAM_IN_STEP_SIZE:
err = sport_in_set_step_size(cmd->data[0]);
break;
case L502_BF_PARAM_ADC_COEF:
if (cmd->data_size < 3) {
err = L502_BF_ERR_INSUF_CMD_DATA;
} else {
uint32_t range = cmd->data[0];
if (range >= L502_ADC_RANGE_CNT) {
err = L502_BF_ERR_INVALID_CMD_PARAMS;
} else {
fpga_reg_write(f_regaddr_k[range], cmd->data[1]);
fpga_reg_write(f_regaddr_offs[range], cmd->data[2]);
}
}
break;
case L502_BF_PARAM_DAC_COEF:
if (cmd->data_size < 3) {
err = L502_BF_ERR_INSUF_CMD_DATA;
} else {
uint32_t ch = cmd->data[0];
if (ch >= L502_DAC_CH_CNT) {
err = L502_BF_ERR_INVALID_CMD_PARAMS;
} else {
float* pk = (float*)&cmd->data[1];
float* po = (float*)&cmd->data[2];
g_module_info.dac_cbr[ch].k = *pk;
g_module_info.dac_cbr[ch].offs = *po;
}
}
break;
default:
err = L502_BF_ERR_INVALID_CMD_PARAMS;
break;
}
}
l502_cmd_done(err, NULL, 0);
}
static void f_cmd_get_param(t_l502_bf_cmd *cmd) {
int32_t err = 0;
uint32_t ret_size = 0;
switch (cmd->param) {
case L502_BF_PARAM_FIRM_VERSION:
cmd->data[0] = L502_BF_FIRM_VERSION;
cmd->data[1] = L502_BF_FIRM_FEATURES;
ret_size = 2;
break;
case L502_BF_PARAM_STREAM_MODE:
cmd->data[0] = g_mode;
ret_size = 1;
break;
case L502_BF_PARAM_ENABLED_STREAMS:
cmd->data[0] = g_streams;
ret_size = 1;
break;
case L502_BF_PARAM_IN_BUF_SIZE:
cmd->data[0] = sport_in_buffer_size();
ret_size = 1;
break;
case L502_BF_PARAM_LCH_CNT:
cmd->data[0] = g_set.lch_cnt;
ret_size = 1;
break;
case L502_BF_PARAM_LCH:
if (cmd->data_size < 1) {
err = L502_BF_ERR_INSUF_CMD_DATA;
} else {
uint32_t index = cmd->data[0];
if (index >= L502_LTABLE_MAX_CH_CNT) {
err = L502_BF_ERR_INVALID_CMD_PARAMS;
} else {
cmd->data[1] = g_set.lch[index].phy_ch;
cmd->data[2] = g_set.lch[index].mode;
cmd->data[3] = g_set.lch[index].range;
cmd->data[4] = g_set.lch[index].avg;
cmd->data[5] = g_set.lch[index].flags;
ret_size = 6;
}
}
break;
case L502_BF_PARAM_ADC_FREQ_DIV:
cmd->data[0] = g_set.adc_freq_div;
ret_size = 1;
break;
case L502_BF_PARAM_REF_FREQ_SRC:
cmd->data[0] = g_set.ref_freq;
ret_size = 1;
break;
case L502_BF_PARAM_ADC_FRAME_DELAY:
cmd->data[0] = g_set.adc_frame_delay;
ret_size = 1;
break;
case L502_BF_PARAM_SYNC_MODE:
cmd->data[0] = g_set.sync_mode;
ret_size = 1;
break;
case L502_BF_PARAM_SYNC_START_MODE:
cmd->data[0] = g_set.sync_start_mode;
ret_size = 1;
break;
case L502_BF_PARAM_DIN_FREQ_DIV:
cmd->data[0] = g_set.din_freq_div;
ret_size = 1;
break;
case L502_BF_PARAM_DAC_FREQ_DIV:
cmd->data[0] = g_set.out_freq_div;
ret_size = 1;
break;
default:
err = L502_BF_ERR_INVALID_CMD_PARAMS;
break;
}
l502_cmd_done(err, cmd->data, ret_size);
}
/** @} */
src/l502_cmd.h
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/** @defgroup cmd_process Обработка команд от ПК */
/***************************************************************************//**
@addtogroup cmd_process
@{
@file l502_cmd.h
Файл содержит описания функций, которые используются для обработки команд
от ПК.
******************************************************************************/
#ifndef L502_BF_CMD_H_
#define L502_BF_CMD_H_
#include <stdint.h>
#include "l502_bf_cmd_defs.h"
/***************************************************************************//**
@brief Запуск обработки команды от ПК.
Функция начинает обработку команды от ПК, переданной по HDMA, вызывая нужный
обработчик по коду команды.
Вызывается из l502_cmd_check_req() при наличии запроса, но можно запустить
и из самой прошивки выполнение команды, заполнив поля в g_state.cmd
и вызвав l502_cmd_start().
Команда считается завершенной, когда будет вызвана l502_cmd_done(), которая
может быть вызвана как из l502_cmd_start(), так и позже из другого места.
@param[in] cmd Структура, описывающая команду
******************************************************************************/
void l502_cmd_start(t_l502_bf_cmd* cmd);
/***************************************************************************//**
@brief Завершение выполнения команды от ПК
Пометить комнду как завершенную, записав ее реультат и возвращаемые данные
в фиксированную область. Если data уже указывает на g_state.cmd.data, т.е.
данные уже находятся в нужной памяти, то они копироваться не будут
@param[in] result Код завершения команды
@param[in] data Данные для ПК, возвращаемые командой
@param[in] size Размер данных, возвращаемых командой (в 32-битных словах)
*******************************************************************************/
void l502_cmd_done(int32_t result, uint32_t* data, uint32_t size);
/***************************************************************************//**
* @brief Проверка наличия команды от ПК
*
* Функция проверяет, есть ли команда от ПК для которой не была начата обработка
* (был вызов l502_cmd_set_req(), но еще не был соответствующий вызов
* l502_cmd_start()).
*
* Если есть необработанная команда, то для нее вызывается l502_cmd_start().
*******************************************************************************/
void l502_cmd_check_req(void);
/***************************************************************************//**
* @brief Установка флага, что есть необработанная команда
*
* Функция вызвается из прерывания от HostDMA в случае, если при этой операции
* HostDMA была записана команда. Функция устанавливает флаг, который будет
* проверен уже из основной программы с помощью l502_cmd_check_req().
******************************************************************************/
void l502_cmd_set_req(void);
#endif
/** @} */
src/l502_defs.h
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/*********************************************************************//**
@addtogroup config_params
@{
@file l502_defs.h Файл содержит определения,
которые используются как программой BF, так и l502api,
и кроме того видны программам, которые используют l502api
@date 28.03.2012
@author Borisov Alexey <borisov@lcard.ru>
*************************************************************************/
#ifndef L502_GLOBAL_DEFS_H_
#define L502_GLOBAL_DEFS_H_
/** Максимальное количество логических каналов в таблице*/
#define L502_LTABLE_MAX_CH_CNT 256
/** Количество диапазон для измерения напряжений */
#define L502_ADC_RANGE_CNT 6
/** Код АЦП, соответствующий максимальному значению шкалы */
#define L502_ADC_SCALE_CODE_MAX 6000000
/** Минимальное значение делителя частоты синхронного вывода */
#define X502_OUT_FREQ_DIV_MIN 2
/** Максимальное значение делителя частоты синхронного вывода */
#define X502_OUT_FREQ_DIV_MAX 1024
/** Значение делителя частоты вывода по умолчанию (которое также всегда
используется в L502 с версией прошивки ПЛИС ниже 0.5) */
#define X502_OUT_FREQ_DIV_DEFAULT 2
/** Максимальное значение для аппаратного устреднения по логическому каналу */
#define L502_LCH_AVG_SIZE_MAX 128
/** Максимальное значения делителя частоты АЦП */
#define L502_ADC_FREQ_DIV_MAX (1024*1024)
/** Максимальное значение делителя частоты синхронного цифрового ввода */
#define L502_DIN_FREQ_DIV_MAX (1024*1024)
/** Максимальное значение межкадровой задержки для АЦП */
#define L502_ADC_INTERFRAME_DELAY_MAX (0x1FFFFF)
/** Диапазон ЦАП в вольтах */
#define L502_DAC_RANGE 5.
/** Количество каналов ЦАП */
#define L502_DAC_CH_CNT 2
/** Слово в потоке, означающее, что произошло переполнение */
#define L502_STREAM_IN_MSG_OVERFLOW 0x01010000
/** Флаги состояния для синхронного вывода */
typedef enum {
/** Флаг указывает, что в настоящее время буфер в модуле на передачу пуст */
X502_OUT_STATUS_FLAG_BUF_IS_EMPTY = 0x01,
/** Флаг указывает, что было опустошение буфера на вывод с начала старта синхронного
ввода-вывода или с момента последнего чтения статуса с помощью
X502_OutGetStatusFlags() (в зависимости от того, что было последним) */
X502_OUT_STATUS_FLAG_BUF_WAS_EMPTY = 0x02
} t_x502_out_status_flags;
/** @brief Флаги для управления цифровыми выходами.
Флаги управления цифровыми выходами. Могут быть объединены через логическое
“ИЛИ” со значениями цифровых выходов при асинхронном выводе с помощью
L502_AsyncOutDig() или переданы в L502_PrepareData() при синхронном выводе.*/
typedef enum {
L502_DIGOUT_WORD_DIS_H = 0x00020000, /**< Запрещение (перевод в третье состояние)
старшей половины цифровых выходов */
L502_DIGOUT_WORD_DIS_L = 0x00010000 /**< Запрещение младшей половины
цифровых выходов */
} t_l502_digout_word_flags;
/** Константы для выбора опорной частоты */
typedef enum {
L502_REF_FREQ_2000KHZ = 2000000, /**< Частота 2МГц */
L502_REF_FREQ_1500KHZ = 1500000 /**< Частота 1.5МГц */
} t_l502_ref_freq;
/** Диапазоны измерения для канала АЦП */
typedef enum {
L502_ADC_RANGE_10 = 0, /**< Диапазон +/-10V */
L502_ADC_RANGE_5 = 1, /**< Диапазон +/-5V */
L502_ADC_RANGE_2 = 2, /**< Диапазон +/-2V */
L502_ADC_RANGE_1 = 3, /**< Диапазон +/-1V */
L502_ADC_RANGE_05 = 4, /**< Диапазон +/-0.5V */
L502_ADC_RANGE_02 = 5 /**< Диапазон +/-0.2V */
} t_l502_adc_range;
/** Режим измерения для логического канала */
typedef enum {
L502_LCH_MODE_COMM = 0, /**< Измерение напряжения относительно общей земли */
L502_LCH_MODE_DIFF = 1, /**< Дифференциальное измерение напряжения */
L502_LCH_MODE_ZERO = 2 /**< Измерение собственного нуля */
} t_l502_lch_mode;
/** @brief Режимы синхронизации.
Режимы задания источника частоты синхронизации и признака начала
синхронного ввода-вывода */
typedef enum {
L502_SYNC_INTERNAL = 0, /**< Внутренний сигнал */
L502_SYNC_EXTERNAL_MASTER = 1, /**< От внешнего мастера по разъему синхронизации */
L502_SYNC_DI_SYN1_RISE = 2, /**< По фронту сигнала DI_SYN1 */
L502_SYNC_DI_SYN2_RISE = 3, /**< По фронту сигнала DI_SYN2 */
L502_SYNC_DI_SYN1_FALL = 6, /**< По спаду сигнала DI_SYN1 */
L502_SYNC_DI_SYN2_FALL = 7 /**< По спаду сигнала DI_SYN2 */
} t_l502_sync_mode;
/** Флаги для обозначения синхронных потоков данных */
typedef enum {
L502_STREAM_ADC = 0x01, /**< Поток данных от АЦП */
L502_STREAM_DIN = 0x02, /**< Поток данных с цифровых входов */
L502_STREAM_DAC1 = 0x10, /**< Поток данных первого канала ЦАП */
L502_STREAM_DAC2 = 0x20, /**< Поток данных второго канала ЦАП */
L502_STREAM_DOUT = 0x40, /**< Поток данных на цифровые выводы */
/** Объединение всех флагов, обозначающих потоки данных на ввод */
L502_STREAM_ALL_IN = L502_STREAM_ADC | L502_STREAM_DIN,
/** Объединение всех флагов, обозначающих потоки данных на вывод */
L502_STREAM_ALL_OUT = L502_STREAM_DAC1 | L502_STREAM_DAC2 | L502_STREAM_DOUT
} t_l502_streams;
#define L502_STREAM_OUT_WORD_TYPE_DOUT 0x0 /**< Тип передаваемого отсчета - цифровой вывод */
#define L502_STREAM_OUT_WORD_TYPE_DAC1 0x40000000 /**< Тип передаваемого отсчета - Код для 1-го канала ЦАП */
#define L502_STREAM_OUT_WORD_TYPE_DAC2 0x80000000 /**< Тип передаваемого отсчета - Код для 2-го канала ЦАП */
/** Режим работы модуля L502 */
typedef enum {
L502_MODE_FPGA = 0, /**< Все потоки данных передаются через ПЛИС минуя
сигнальный процессор BlackFin */
L502_MODE_DSP = 1, /**< Все потоки данных передаются через сигнальный
процессор, который должен быть загружен
прошивкой для обработки этих потоков */
L502_MODE_DEBUG = 2 /**< Отладочный режим */
} t_l502_mode;
/** @brief Номера каналов ЦАП.
Номер каналов ЦАП для указания в L502_AsyncOutDac() */
typedef enum {
L502_DAC_CH1 = 0, /**< Первый канал ЦАП */
L502_DAC_CH2 = 1 /**< Второй канал ЦАП */
} t_l502_dac_ch;
/** Флаги, описывающие модуль */
typedef enum {
/** Признак наличия ЦАП */
L502_DEVFLAGS_DAC_PRESENT = 0x0001,
/** Признак наличия гальваноразвязки */
L502_DEVFLAGS_GAL_PRESENT = 0x0002,
/** Признак наличия сигнального процессора */
L502_DEVFLAGS_BF_PRESENT = 0x0004,
/** Признак, что во Flash-памяти присутствует информация о модуле */
L502_DEVFLAGS_FLASH_DATA_VALID = 0x00010000,
/** Признак, что во Flash-памяти присутствуют действительные калибровочные
коэффициенты АЦП */
L502_DEVFLAGS_FLASH_ADC_CALIBR_VALID = 0x00020000,
/** Признак, что во Flash-памяти присутствуют действительные калибровочные
коэффициенты ЦАП */
L502_DEVFLAGS_FLASH_DAC_CALIBR_VALID = 0x00040000
} t_l502_devinfo_flags;
#endif
/** @} */
src/l502_fpga.c
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/** @addtogroup fpga_regs
@{
@file l502_fpga.c
Ôàéë ñîäåðæèò ëîãèêó ïåðåäà÷è êîìàíä äëÿ ÷òåíèÿ/çàïèñè ðåãèñòðîâ
ÏËÈÑ ïî SPI.
Èçíà÷àëüíî SPI äîëæåí áûòü ïðîèíèöèàëèçèðîâàí ñ ïîìîùüþ fpga_spi_init().
Ïîñëå ýòîãî ìîæíî îñóùåñòâëÿòü çàïèñü ñ ïîìîùüþ fpga_reg_write(), à
÷òåíèå ñ ïîìîùüþ fpga_reg_read(). */
#include <cdefBF523.h>
#include "l502_fpga.h"
#define L502_SPI_BIT_START 0x8000UL
#define L502_SPI_BIT_WR 0x4000UL
#define L502_SPI_MSK_ADDR 0x3FFFUL
static uint16_t f_spi_rw(uint16_t word) {
/* åñëè â áûëî ïðèíÿòî óæå ñëîâî - òî ÷èòàåì åãî, ÷òîáû îñâîáîäèòü áóôåð ïðèåìà */
if (*pSPI_STAT & RXS) {
volatile uint16_t dummy;
dummy = *pSPI_RDBR;
}
*pSPI_TDBR = word;
/* æäåì ïîêà ïðèìåì íîâîå ñëîâî */
while (!(*pSPI_STAT&RXS)) {
continue;
}
return *pSPI_RDBR;
}
void fpga_spi_init(void) {
/* íàñòðîéêà SPI */
*pSPI_BAUD = 2; /* SPI CLK = 132.5/(2*2) = 33.125 */
*pSPI_CTL = SPE | MSTR | SIZE | GM | TDBR_CORE; /* Ìàñòåð, MSB first, 16-bit, CPHA=0, CPOL=0 */
*pSPI_FLG = FLS1;
*pPORTG_MUX = (*pPORTG_MUX & 0xFFFC) | 2;
*pPORTG_FER |= PG1 | PG2 | PG3 | PG4;
fpga_reg_write(L502_REGS_IOHARD_OUTSWAP_BFCTL, 0);
}
void fpga_reg_write(uint16_t addr, uint32_t value) {
f_spi_rw((addr&L502_SPI_MSK_ADDR) | L502_SPI_BIT_START | L502_SPI_BIT_WR);
f_spi_rw((value>>24)&0xFF);
f_spi_rw((value>>16)&0xFF);
f_spi_rw((value>>8)&0xFF);
f_spi_rw(value&0xFF);
}
uint32_t fpga_reg_read(uint16_t addr) {
uint32_t ret = 0;
f_spi_rw((addr&L502_SPI_MSK_ADDR) | L502_SPI_BIT_START);
f_spi_rw(0);
f_spi_rw(0);
ret = f_spi_rw(0);
ret <<= 16;
ret |= f_spi_rw(0);
return ret;
}
/** @} */
src/l502_fpga.h
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/** @defgroup fpga_regs Доступ к регистрам ПЛИС */
/***************************************************************************//**
@addtogroup fpga_regs
@{
@file l502_fpga.h
Файл содержит функции для записи и чтения регистров ПЛИС по интерфейсу АЦП
*******************************************************************************/
#ifndef L502_FPGA_H_
#define L502_FPGA_H_
#include <stdint.h>
#include "l502_fpga_regs.h"
/** Инициализация SPI интерфейса */
void fpga_spi_init(void);
/** Запись регистра в регистр ПЛИС значения по интерфейсу SPI
@param[in] addr Адрес регистра ПЛИС
@param[in] value Записываемое значение */
void fpga_reg_write(uint16_t addr, uint32_t value);
/** Чтение значения из регистра ПЛИС по интерфейсу SPI
@param[in] addr Адрес регистра ПЛИС
@return Прочитанное значение */
uint32_t fpga_reg_read(uint16_t addr);
#endif
/** @} */
src/l502_fpga_regs.h
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#ifndef L5XX_REGS_H
#define L5XX_REGS_H
#define L583_BF_ADDR_ENDPROG (0xFFFFFFFCUL)
#define L502_MAX_PAGES_CNT 252
#define L502_BF_SDRAM_SIZE (32UL*1024*1024)
#define L502_BF_MEMADDR_CMD 0xFF800800
#define L502_BF_CMD_READ 0x0001
#define L502_BF_CMD_WRITE 0x0002
#define L502_BF_CMD_HIRQ 0x0004
#define L502_BF_CMD_HDMA_RST 0x0008
/********************* Àäðåñà ðåãèñòðîâ áëîêà EEPROM *************************/
#define L502_REGS_EEPROM_BLOCK 0x0100
#define L502_REGS_EEPROM_SET_RD_ADDR (L502_REGS_EEPROM_BLOCK + 0)
#define L502_REGS_EEPROM_RD_DWORD (L502_REGS_EEPROM_BLOCK + 1)
#define L502_REGS_EEPROM_RD_STATUS (L502_REGS_EEPROM_BLOCK + 2)
#define L502_REGS_EEPROM_WR_STATUS_EN (L502_REGS_EEPROM_BLOCK + 3)
#define L502_REGS_EEPROM_WR_EN (L502_REGS_EEPROM_BLOCK + 4)
#define L502_REGS_EEPROM_WR_DIS (L502_REGS_EEPROM_BLOCK + 5)
#define L502_REGS_EEPROM_WR_STATUS (L502_REGS_EEPROM_BLOCK + 6)
#define L502_REGS_EEPROM_ERASE_4K (L502_REGS_EEPROM_BLOCK + 7)
#define L502_REGS_EEPROM_ERASE_64K (L502_REGS_EEPROM_BLOCK + 8)
#define L502_REGS_EEPROM_WR_BYTE (L502_REGS_EEPROM_BLOCK + 9)
#define L502_REGS_EEPROM_HARD_WR_STATUS_EN (L502_REGS_EEPROM_BLOCK + 0xF)
#define L502_REGS_HARD_ID (L502_REGS_EEPROM_BLOCK + 0xA)
#define L502_REGS_JEDEC_RD_ID (L502_REGS_EEPROM_BLOCK + 0xB)
/********************* Àäðåñà ðåãèñòðîâ ñ îòëàäî÷íîé èíôîðìàöèåé **************/
#define L502_REGS_DBG_BLOCK 0x0140
#define L502_REGS_DBG_EVENTS (L502_REGS_DBG_BLOCK + 0)
#define L502_REGS_DBG_LAST_ABORT_ADDR (L502_REGS_DBG_BLOCK + 8)
#define L502_REGS_DBG_LAST_NACK_ADDR (L502_REGS_DBG_BLOCK + 9)
#define L502_REGS_DBG_LINK_REPLAY_CNT (L502_REGS_DBG_BLOCK + 10)
/********************* Àäðåñà ðåãèñòðîâ áëîêà IOHARD **************************/
#define L502_REGS_IOHARD_BLOCK 0x0200
//Àäðåñ Control Table
#define L502_REGS_IOHARD_LTABLE (L502_REGS_IOHARD_BLOCK+0)
#define L502_REGS_IOHARD_LTABLE_MAX_SIZE 0x100 // Ìàêñèìàëüíûé ðàçìåð Control Table
#define L502_REGS_IOHARD_LCH_CNT (L502_REGS_IOHARD_BLOCK+0x100)
#define L502_REGS_IOHARD_ADC_FREQ_DIV (L502_REGS_IOHARD_BLOCK+0x102)
#define L502_REGS_IOHARD_ADC_FRAME_DELAY (L502_REGS_IOHARD_BLOCK+0x104)
#define L502_REGS_IOHARD_DIGIN_FREQ_DIV (L502_REGS_IOHARD_BLOCK+0x106)
#define L502_REGS_IOHARD_IO_MODE (L502_REGS_IOHARD_BLOCK+0x108)
#define L502_REGS_IOHARD_GO_SYNC_IO (L502_REGS_IOHARD_BLOCK+0x10A)
#define L502_REGS_IOHARD_PRELOAD_ADC (L502_REGS_IOHARD_BLOCK+0x10C)
#define L502_REGS_IOHARD_ASYNC_OUT (L502_REGS_IOHARD_BLOCK+0x112)
#define L502_REGS_IOHARD_LED (L502_REGS_IOHARD_BLOCK+0x114)
#define L502_REGS_IOHARD_DIGIN_PULLUP (L502_REGS_IOHARD_BLOCK+0x116)
#define L502_REGS_IOHARD_OUTSWAP_BFCTL (L502_REGS_IOHARD_BLOCK+0x118)
#define L502_REGS_IOHARD_OUTSWAP_ERROR (L502_REGS_IOHARD_BLOCK+0x120)
/********************* Àäðåñà ðåãèñòðîâ áëîêà IOARITH **************************/
#define L502_REGS_IOARITH_BLOCK 0x0400
#define L502_REGS_IOARITH_B10 L502_REGS_IOARITH_BLOCK
#define L502_REGS_IOARITH_B5 (L502_REGS_IOARITH_BLOCK+0x01)
#define L502_REGS_IOARITH_B2 (L502_REGS_IOARITH_BLOCK+0x02)
#define L502_REGS_IOARITH_B1 (L502_REGS_IOARITH_BLOCK+0x03)
#define L502_REGS_IOARITH_B05 (L502_REGS_IOARITH_BLOCK+0x04)
#define L502_REGS_IOARITH_B02 (L502_REGS_IOARITH_BLOCK+0x05)
#define L502_REGS_IOARITH_K10 (L502_REGS_IOARITH_BLOCK+0x08)
#define L502_REGS_IOARITH_K5 (L502_REGS_IOARITH_BLOCK+0x09)
#define L502_REGS_IOARITH_K2 (L502_REGS_IOARITH_BLOCK+0x0A)
#define L502_REGS_IOARITH_K1 (L502_REGS_IOARITH_BLOCK+0x0B)
#define L502_REGS_IOARITH_K05 (L502_REGS_IOARITH_BLOCK+0x0C)
#define L502_REGS_IOARITH_K02 (L502_REGS_IOARITH_BLOCK+0x0D)
#define L502_REGS_IOARITH_ADC_FREQ_DIV (L502_REGS_IOARITH_BLOCK+0x12)
#define L502_REGS_IOARITH_IN_STREAM_ENABLE (L502_REGS_IOARITH_BLOCK+0x19)
#define L502_REGS_IOARITH_DIN_ASYNC (L502_REGS_IOARITH_BLOCK+0x1A)
/********************* Àäðåñà ðåãèñòðîâ áëîêà óïðàâëåíèÿ BlackFin'îì **********/
#define L502_REGS_BF_CTL_BLOCK 0
#define L502_REGS_BF_CTL (L502_REGS_BF_CTL_BLOCK+0)
#define L502_REGS_BF_CMD (L502_REGS_BF_CTL_BLOCK+1)
#define L502_REGS_BF_STATUS (L502_REGS_BF_CTL_BLOCK+2)
#define L502_REGS_BF_IRQ (L502_REGS_BF_CTL_BLOCK+3)
#define L502_REGS_BF_IRQ_EN (L502_REGS_BF_CTL_BLOCK+4)
#define L502_REGS_BF_REQ_ADDR (L502_REGS_BF_CTL_BLOCK+5)
#define L502_REGS_BF_REQ_SIZE (L502_REGS_BF_CTL_BLOCK+6)
#define L502_REGS_BF_REQ_DATA (L502_REGS_BF_CTL_BLOCK+128)
#define L502_BF_REQ_DATA_SIZE_MAX 128
#define L502_BF_REQ_DATA_SIZE_MIN 8
/********************* Àäðåñà ðåãèñòðîâ áëîêà DMA *****************************/
#define L502_REGS_DMA_CTL_BLOCK 0x700
#define L502_REGS_DMA_CAP (L502_REGS_DMA_CTL_BLOCK)
#define L502_REGS_DMA_EN (L502_REGS_DMA_CTL_BLOCK+1)
#define L502_REGS_DMA_DIS (L502_REGS_DMA_CTL_BLOCK+2)
#define L502_REGS_DMA_RST (L502_REGS_DMA_CTL_BLOCK+3)
#define L502_REGS_DMA_IRQ (L502_REGS_DMA_CTL_BLOCK+4)
#define L502_REGS_DMA_IRQ_EN (L502_REGS_DMA_CTL_BLOCK+5)
#define L502_REGS_DMA_IRQ_DIS (L502_REGS_DMA_CTL_BLOCK+6)
#define L502_REGS_DMA_CH_PARAMS_SIZE (16 + L502_MAX_PAGES_CNT*4)
#define L502_DMA_CHNUM_IN 0
#define L502_DMA_CHNUM_OUT 1
/* íîìåð ðåãèñòðà, ñ êîòîðîãî íà÷èíàþòñÿ ïàðàìåòðû êàíàëà DMA */
#define L502_REGS_DMA_CH_PARAMS(ch) (0x800 + L502_REGS_DMA_CH_PARAMS_SIZE*ch)
#define L502_REGS_DMA_CH_CTL(ch) (L502_REGS_DMA_CH_PARAMS(ch) + 0)
#define L502_REGS_DMA_CH_CMP_CNTR(ch) (L502_REGS_DMA_CH_PARAMS(ch) + 1)
#define L502_REGS_DMA_CH_CUR_CNTR(ch) (L502_REGS_DMA_CH_PARAMS(ch) + 2)
#define L502_REGS_DMA_CH_CUR_POS(ch) (L502_REGS_DMA_CH_PARAMS(ch) + 3)
#define L502_REGS_DMA_CH_PC_POS(ch) (L502_REGS_DMA_CH_PARAMS(ch) + 4)
/* àäðåñà äëÿ ðåãèñòðîâ ñòðàíèö DMA ÀÖÏ */
#define L502_REGS_DMA_CH_PAGES(ch) (L502_REGS_DMA_CH_PARAMS(ch) + 16)
#define L502_REGS_DMA_CH_PAGE_ADDRL(ch,n) (L502_REGS_DMA_CH_PAGES(ch) + 4*(n))
#define L502_REGS_DMA_CH_PAGE_ADDRH(ch,n) (L502_REGS_DMA_CH_PAGES(ch) + 4*(n)+1)
#define L502_REGS_DMA_CH_PAGE_LEN(ch,n) (L502_REGS_DMA_CH_PAGES(ch) + 4*(n)+2)
#define L502_REGBIT_BF_STATUS_HWAIT_Pos 0
#define L502_REGBIT_BF_STATUS_HWAIT_Msk (1UL << L502_REGBIT_BF_STATUS_HWAIT_Pos)
#define L502_REGBIT_BF_STATUS_BUSY_Pos 1
#define L502_REGBIT_BF_STATUS_BUSY_Msk (1UL << L502_REGBIT_BF_STATUS_BUSY_Pos)
/* îïèñàíèå îòäåëüíûõ áèòîâ ðåãèñòðîâ */
#define L502_REGBIT_DMA_CTL_PACK_SIZE_Pos 0
#define L502_REGBIT_DMA_CTL_PACK_SIZE_Msk (0xFFUL << L502_REGBIT_DMA_CTL_PACK_SIZE_Pos)
#define L502_REGBIT_DMA_CTL_PAGE_CNT_Pos 16
#define L502_REGBIT_DMA_CTL_PAGE_CNT_Msk (0xFFUL << L502_REGBIT_DMA_CTL_PAGE_CNT_Pos)
#define L502_REGBIT_DMA_CTL_AUTOSTOP_Pos 31
#define L502_REGBIT_DMA_CTL_AUTOSTOP_Msk (0x1UL << L502_REGBIT_DMA_CTL_AUTOSTOP_Pos)
#define L502_REGBIT_DMA_CTL_PC_WAIT_Pos 30
#define L502_REGBIT_DMA_CTL_PC_WAIT_Msk (0x1UL << L502_REGBIT_DMA_CTL_PC_WAIT_Pos)
#define L502_REGBIT_DMA_CH_ADC_Pos 0
#define L502_REGBIT_DMA_CH_ADC_Msk (0x1UL << L502_REGBIT_DMA_CH_ADC_Pos)
#define L502_REGBIT_DMA_CH_DAC_Pos 1
#define L502_REGBIT_DMA_CH_DAC_Msk (0x1UL << L502_REGBIT_DMA_CH_DAC_Pos)
#define L502_REGBIT_BF_CTL_BF_RESET_Pos 1
#define L502_REGBIT_BF_CTL_BF_RESET_Msk (0x1UL << L502_REGBIT_BF_CTL_BF_RESET_Pos)
#define L502_REGBIT_BF_CTL_HOST_WAIT_Pos 3
#define L502_REGBIT_BF_CTL_HOST_WAIT_Msk (0x1UL << L502_REGBIT_BF_CTL_HOST_WAIT_Pos)
#define L502_REGBIT_BF_CTL_DSP_MODE_Pos 4
#define L502_REGBIT_BF_CTL_DSP_MODE_Msk (0x1UL << L502_REGBIT_BF_CTL_DSP_MODE_Pos)
#define L502_REGBIT_BF_CTL_DBG_MODE_Pos 5
#define L502_REGBIT_BF_CTL_DBG_MODE_Msk (0x1UL << L502_REGBIT_BF_CTL_DBG_MODE_Pos)
#define L502_REGBIT_BF_CTL_CLK_DIV_Pos 8
#define L502_REGBIT_BF_CTL_CLK_DIV_Msk (0xFUL << L502_REGBIT_BF_CTL_CLK_DIV_Pos)
#define L502_REGBIT_DMA_CURPOS_PAGE_Pos 24
#define L502_REGBIT_DMA_CURPOS_PAGE_Msk (0xFFUL << L502_REGBIT_DMA_CURPOS_PAGE_Pos)
#define L502_REGBIT_ADC_SLV_CLK_LOCK_Pos 31
#define L502_REGBIT_ADC_SLV_CLK_LOCK_Msk (0x1UL << L502_REGBIT_ADC_SLV_CLK_LOCK_Pos)
#define L502_REGBIT_IOHARD_OUT_SWAP_Pos 0
#define L502_REGBIT_IOHARD_OUT_SWAP_Msk (0x1UL << L502_REGBIT_IOHARD_OUT_SWAP_Pos)
#define L502_REGBIT_IOHARD_OUT_TFS_EN_Pos 1
#define L502_REGBIT_IOHARD_OUT_TFS_EN_Msk (0x1UL << L502_REGBIT_IOHARD_OUT_TFS_EN_Pos)
#define L502_REGBIT_IOHARD_OUT_RING_Pos 2
#define L502_REGBIT_IOHARD_OUT_RING_Msk (0x1UL << L502_REGBIT_IOHARD_OUT_RING_Pos)
#define L502_REGBIT_IOHARD_OUT_RFS_EN_Pos 3
#define L502_REGBIT_IOHARD_OUT_RFS_EN_Msk (0x1UL << L502_REGBIT_IOHARD_OUT_RFS_EN_Pos)
#define L502_REGBIT_DMA_IRQ_STEP_Msk(ch) (1UL << ch)
#define L502_REGBIT_DMA_IRQ_PAGE_Msk(ch) (1UL << (ch+8))
#endif // L5XX_REGS_H
src/l502_global.h
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/** @defgroup global_defs Фиксированная область памяти */
/***************************************************************************//**
@addtogroup global_defs
@{
@file l502_global.h
Файл содержит определение структур, описывающих область памяти
BlackFin с фиксированными адресами:
- Структуры дескрипторов для передачи потоков данных по HostDMA
- Структру для передачи команд от ПК к BlackFin
*******************************************************************************/
#ifndef L502_GLOBAL_H_
#define L502_GLOBAL_H_
#include <stdint.h>
#include "l502_bf_cmd_defs.h"
/** Версия прошивки BlackFin */
#define L502_BF_FIRM_VERSION 0x00000002
/** Дополнительные возможности, реализованные в прошивке */
#define L502_BF_FIRM_FEATURES (L502_BF_FEATURE_FPGA_REG_ACCESS | L502_BF_FEATURE_OUT_STATUS_FLAGS)
/** Структура дескриптора для передачи потока по HostDMA */
typedef struct {
uint32_t flags; /**< Флаги */
uint32_t full_size; /**< Полный размер передачи */
void* addr; /**< Начальный адрес данных для передачи */
uint16_t xcnt; /**< Кол-во 16-разрядных слов в одном передаваемом блоке */
uint16_t xmod; /**< Модификатор указателя */
uint16_t ycnt; /**< Не используется */
uint16_t ymod; /**< Не используется */
void* next_descr; /**< Указатель на следующий дескриптор */
uint16_t id; /**< id-номер дескриптора */
uint16_t valid; /**< Признак действительности */
uint32_t udata; /**< Доп данные */
} t_hdma_stream_descr;
/** Максимальное количество дескрипторов на передачу данных (Bf->ПК) */
#define L502_IN_HDMA_DESCR_CNT (31)
/** Максимальное количество дескрипторов на прием данных (ПК->Bf) */
#define L502_OUT_HDMA_DESCR_CNT (31)
/** @brief Описание массива дескрипторов HDMA
Структура описывает расположение дескрипторов HostDMA для организации
потока данных между BlackFin и персональным компьютером как на передачу,
так и на прием */
typedef struct {
t_hdma_stream_descr in_lb; /**< Последний выполненный дескриптор на ввод */
t_hdma_stream_descr in[L502_IN_HDMA_DESCR_CNT]; /**< Список дескрипторов на ввод */
t_hdma_stream_descr out_lb; /**< Последний выполненный дескриптор на вывод */
t_hdma_stream_descr out[L502_OUT_HDMA_DESCR_CNT]; /**< Список дескрипторов на вывод */
} t_hdma_descr_arr;
/** @brief Описание фиксированной области памяти
Структура описывает данные в памяти сигнального процессора, которые должны
быть расположены по фиксированным адресам */
typedef struct {
t_hdma_descr_arr hdma; /**< 0xFF800000 - дескрипторы для обмена потоком по HDMA*/
t_l502_bf_cmd cmd; /**< 0xFF800800 - команда обмена с PC*/
} t_l502_board_state;
/** Структура, содержащая данные фиксированной памяти */
extern volatile t_l502_board_state g_state;
#endif
/** @} */
src/l502_hdma.c
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/***************************************************************************//**
@addtogroup hdma
@{
@file l502_hdma.c
Файл содержит логику работы с hdma на прием и на передачу данных
как из, так и в BlackFin.
***************************************************************************/
/******************************************************************************
При запуске должно вызываться один раз hdma_stream_init().
Вызов hdma_xxx_start() инициализирует прием или передачу, а hdma_xxx_stop()
останавливает все текущие передачи.
Для запуска обмена блоком данных нужно проверить готовность
(наличие свободных дескрипторов) с помощью hdma_xxx_req_rdy()
и вызвать hdma_xxx_req_start(), указав массив для передачи или приема
данных и его размер.
Можно устанавливать до 31 запроса в очередь.
По завершению обмена будет вызвана функция hdma_xxx_done(), которая
должна быть реализована в другом файле. Для передачи BF->PC
функция вызывается один раз на каждый поставленный запрос,
а при приеме PC->BF может вызываться по несколько раз - при приеме
части запроса (в случае, если от PC пока нет больше данных)
*******************************************************************************/
#include "l502_global.h"
#include "l502_cdefs.h"
#include "l502_cmd.h"
#include <cdefBF523.h>
#include <sys/exception.h>
#include <ccblkfn.h>
#define STREAM_IN_EN() *pPORTFIO_CLEAR = PF14
#define STREAM_IN_DIS() *pPORTFIO_SET = PF14
#define STREAM_OUT_EN() *pPORTFIO_CLEAR = PF15
#define STREAM_OUT_DIS() *pPORTFIO_SET = PF15
#define STREAM_IN_SET_REQ() *pPORTGIO_TOGGLE = PG5
#define STREAM_OUT_SET_REQ() *pPORTGIO_TOGGLE = PG6
#define L502_HDMA_STEP_SIZE_MAX 256
static uint16_t f_snd_start_id, f_rcv_start_id;
static uint16_t f_snd_done_id, f_rcv_done_id;
static uint8_t f_snd_next_descr, f_rcv_next_descr;
static uint8_t f_rcv_done_descr;
void hdma_send_done(uint32_t* addr, uint32_t size);
void hdma_recv_done(uint32_t* addr, uint32_t size);
ISR(hdma_isr);
ISR(hdma_rd_isr);
inline static void hdma_set_descr(t_hdma_stream_descr* descr_arr, uint8_t* pos,
uint16_t* id, uint32_t* addr, uint32_t size, uint32_t flags) {
descr_arr[*pos].flags = flags;
descr_arr[*pos].addr = addr;
descr_arr[*pos].id = *id;
descr_arr[*pos].full_size = size*2;
descr_arr[*pos].xcnt = size > L502_HDMA_STEP_SIZE_MAX ? 2*L502_HDMA_STEP_SIZE_MAX : 2*size;
descr_arr[*pos].udata = size;
*id = *id+1;
*pos=*pos+1;
if (*pos== L502_IN_HDMA_DESCR_CNT)
*pos = 0;
}
/** @brief Инициализация интерфейса HostDMA
Настройка параметров HostDMA и инициализация неизменяемых полей дескрипторов
для организации потока по данных по HostDMA */
void hdma_init(void) {
int d;
/* запрещаем ПЛИС отслеживать запросы на обмен по HDMA */
STREAM_IN_DIS();
STREAM_OUT_DIS();
*pPORTGIO_DIR |= PG5 | PG6;
*pPORTFIO_DIR |= PF14 | PF15;
/***************** настройка HOST DMA ***********************/
//настройка портов
*pPORTG_MUX |= 0x2800;
*pPORTG_FER |= 0xF800;
*pPORTH_MUX = 0x2A;
*pPORTH_FER = 0xFFFF;
//настройка прерываний
REGISTER_ISR(11, hdma_isr);
//*pSIC_IAR3 = (*pSIC_IAR6 & 0xFFF0FFFFUL) | (3 << 16);
*pSIC_IAR6 = (*pSIC_IAR6 & 0xFFFFF0FFUL) | P50_IVG(10); //назначение HDMARD на IVG10
REGISTER_ISR(10, hdma_rd_isr);
*pSIC_IMASK0 |= IRQ_DMA1; //разрешение прерывания HOSTDP на запись
*pSIC_IMASK1 |= IRQ_HOSTRD_DONE; //разрешение прерывания HOSTDP на чтение;
//разрешение HDMA
*pHOST_CONTROL = BDR | EHR | EHW | HOSTDP_EN | HOSTDP_DATA_SIZE; //burst, ehr, ehw, en
//g_state.cmd.data[100] = L502_BF_CMD_STATUS_DONE;
/* инициалзация полей дескрипторов, которые не будут изменяться
во время работы */
for (d=0; d < L502_IN_HDMA_DESCR_CNT; d++) {
g_state.hdma.in[d].xmod = 2;
g_state.hdma.in[d].valid = 1;
g_state.hdma.in[d].next_descr = d==( L502_IN_HDMA_DESCR_CNT-1) ?
(void*)&g_state.hdma.in[0] : (void*)&g_state.hdma.in[d+1];
}
for (d=0; d < L502_OUT_HDMA_DESCR_CNT; d++) {
g_state.hdma.out[d].xmod = 2;
g_state.hdma.out[d].valid = 1;
g_state.hdma.out[d].next_descr = d==( L502_IN_HDMA_DESCR_CNT-1) ?
(void*)&g_state.hdma.out[0] : (void*)&g_state.hdma.out[d+1];
}
}
/** @brief Запуск потока на передачу по HostDMA.
Функция сбрасывает логику обработки заданий на передачу данных по HostDMA
и разрешает передачу. Должна вызываться до добавления первого задания с помощью
hdma_send_req_start() */
void hdma_send_start(void) {
f_snd_start_id = 0;
f_snd_done_id = 0;
f_snd_next_descr = 0;
g_state.hdma.in_lb.valid = 0;
STREAM_IN_EN();
}
/** @brief Останов потока на передачу по HostDMA.
Запрет передачи по HostDMA с остановом всех текущих заданий */
void hdma_send_stop(void) {
STREAM_IN_DIS();
}
/** @brief Запуск потока на прием по HostDMA
Функция сбрасывает логику обработки заданий на прием данных по HostDMA
и разрешает прием. Должна вызываться до добавления первого задания с помощью
hdma_recv_req_start() */
void hdma_recv_start(void) {
f_rcv_start_id = 0;
f_rcv_done_id = 0;
f_rcv_next_descr = 0;
f_rcv_done_descr = 0;
g_state.hdma.out_lb.valid = 0;
STREAM_OUT_EN();
}
/** @brief Останов потока на прием по HostDMA
Запрет приема по HostDMA с остановом всех текущих заданий */
void hdma_recv_stop(void) {
STREAM_OUT_DIS();
}
/**************************************************************************//**
@brief Получить количество свободных запросов на передачу.
Фунция позволяет узнать, сколько запросов можно еще поставить в очередь на
передачу с помощью hdma_send_start().
@return Количество запросов на передачу, которое можно поставить в очередь
******************************************************************************/
int hdma_send_req_rdy(void) {
return L502_IN_HDMA_DESCR_CNT - (uint16_t)(f_snd_start_id - f_snd_done_id);
}
/**************************************************************************//**
@brief Получить количество свободных запросов на прием
Фунция позволяет узнать, сколько запросов можно еще поставить в очередь на
прием с помощью hdma_recv_start().
@return Количество запросов на прием, которое можно поставить в очередь
******************************************************************************/
int hdma_recv_req_rdy(void) {
return L502_OUT_HDMA_DESCR_CNT - (uint16_t)(f_rcv_start_id - f_rcv_done_id);
}
/**************************************************************************//**
@brief Поставить запрос на передачу по HostDMA
Функция ставит запрос на передачу указанных данных. Сами данные не копируются,
т.е. буфер нельзя будет использовать до того, как данные не будут переданы!
Для постановки запроса необходимо, чтобы был свободный дескриптор (можно
узнать через hdma_send_req_rdy())
@param[in] buf Указатель на массив на передачу.
@param[in] size Количество 32-битных слов на передачу
@param[in] flags Флаги из #t_hdma_send_flags
@return < 0 при ошибке, >= 0 - id передачи при успехе
*******************************************************************************/
int hdma_send_req_start(const uint32_t* buf, uint32_t size, uint32_t flags) {
if (hdma_send_req_rdy() > 0) {
hdma_set_descr((t_hdma_stream_descr*)g_state.hdma.in, &f_snd_next_descr, &f_snd_start_id,
(uint32_t*)buf, size, flags);
STREAM_IN_SET_REQ();
return f_snd_start_id-1;
}
return -1;
}
/**************************************************************************//**
@brief Поставить запрос на передачу по HostDMA
Функция ставит запрос на прием данных в указанный буфер.
Сами данные будут в буфере только по завершению запроса.
Для постановки запроса необходимо, чтобы был свободный дескриптор (можно
узнать через hdma_recv_req_rdy())
@param[in] buf Указатель на массив на передачу.
@param[in] size Количество 32-битных слов на передачу
@return < 0 при ошибке, >= 0 - id передачи при успехе
*******************************************************************************/
int hdma_recv_req_start(uint32_t* buf, uint32_t size) {
if (hdma_recv_req_rdy() > 0) {
hdma_set_descr((t_hdma_stream_descr*)g_state.hdma.out, &f_rcv_next_descr, &f_rcv_start_id, buf, size, 0);
STREAM_OUT_SET_REQ();
return f_rcv_start_id-1;
}
return -1;
}
/**
@brief Обработчик прерывания на завершения записи в память BF по HDMA
Обработчик вызывается по завершению приема блока по HostDMA. Обработчик
выполняет установку необходимых флагов для разрешения приема следующего блока
и, кроме того, проверяет наличие новой команды и завершения передачи или приема
блока из потока данных */
ISR(hdma_isr) {
if ((*pDMA1_IRQ_STATUS & DMA_DONE) != 0) {
/* проверяем, не была ли записана команда */
if (g_state.cmd.status == L502_BF_CMD_STATUS_REQ) {
l502_cmd_set_req();
}
/* проверяем, не был ли записан результат передачи
по HDMA из BF в PC */
if (g_state.hdma.in_lb.valid) {
/* обновляем id завершенной передачи и вызываем callback */
f_snd_done_id = g_state.hdma.in_lb.id;
g_state.hdma.in_lb.valid = 0;
hdma_send_done(g_state.hdma.in_lb.addr, g_state.hdma.in_lb.udata);
}
/* проверяем, не был ли записан результат приема данных по
HDMA из PC в BF */
if (g_state.hdma.out_lb.valid) {
/* может быть записан и при не полностью завершенном запросе.
определяем сперва резмер, сколько было реально принято */
uint32_t size = (g_state.hdma.out[f_rcv_done_descr].full_size -
g_state.hdma.out_lb.full_size)/2;
g_state.hdma.out_lb.valid = 0;
hdma_recv_done(g_state.hdma.out_lb.addr, size);
/* если была завершена только часть дескриптора -
обновляем оставшийся размер для приема */
if (g_state.hdma.out_lb.full_size) {
g_state.hdma.out[f_rcv_done_descr].full_size =
g_state.hdma.out_lb.full_size;
} else {
/* если завершен весь дескриптор - переходим
к следующему */
if (++f_rcv_done_descr== L502_OUT_HDMA_DESCR_CNT)
f_rcv_done_descr = 0;
f_rcv_done_id = g_state.hdma.out_lb.id;
}
}
*pDMA1_IRQ_STATUS = DMA_DONE;
csync();
*pHOST_STATUS = DMA_CMPLT;
}
ssync();
}
/**
@brief Обработчик прерывания на завершение чтения по HDMA.
Данный обработчик вызывается по завершению передачи блока данных по HostDMA.
Выполняет только установку необходимых флагов для разрешения следующей
передачи */
ISR(hdma_rd_isr) {
if ((*pHOST_STATUS & HOSTRD_DONE) != 0) {
*pHOST_STATUS &= ~((unsigned short)HOSTRD_DONE);
*pHOST_STATUS |= DMA_CMPLT;
}
ssync();
}
/** @} */
src/l502_hdma.h
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/** @defgroup hdma Ðàáîòà ñ èíòåðôåéñîì HostDMA */
/***************************************************************************//**
@addtogroup hdma
@{
@file l502_hdma.h
Ôàéë ñîäåðæèò îïèñàíèÿ ôóíêöèé äëÿ ðàáîòû ñ èíòåðôåéñîì HostDMA
******************************************************************************/
#ifndef L502_HDMA_H_
#define L502_HDMA_H_
void hdma_init(void);
/** Ôëàãè äëÿ ïåðåäà÷è ïî #t_hdma_send_flags */
typedef enum {
/** Ôëàã, óêàçûâàþùèé, ÷òî ïåðåäàåòñÿ ïîñëåäíèé ïàêåò äàííûõ. Ïî çàâåðøåíèþ
ïåðåäà÷è áóäåò îñòàíîâëåí ïîòîê è ñãåíåðèðîâàíî ïðåðûâàíèÿ äëÿ ÏÊ */
L502_HDMA_FLAGS_SEND_LAST = 0x1
} t_hdma_send_flags;
void hdma_send_start(void);
void hdma_send_stop(void);
int hdma_send_req_start(const uint32_t* snd_buf, uint32_t size, uint32_t flags);
int hdma_send_req_rdy(void);
void hdma_recv_start(void);
void hdma_recv_stop(void);
int hdma_recv_req_start(uint32_t* buf, uint32_t size);
int hdma_recv_req_rdy(void);
#endif
/** @} */
src/l502_init.c
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#include <cdefBF523.h>
#include <ccblkfn.h>
#include <bfrom.h>
#include <sys/exception.h>
#include <stdlib.h>
#include <stdint.h>
#include "l502_cdefs.h"
#include "l502_fpga.h"
#include "l502_hdma.h"
ISR(isr_sport_dma_rx);
ISR(isr_sport_dma_tx);
void l502_stream_init(void);
/* fVCO = 530 MHZ = (20/2)*53, CDIV=1, SDIV = 4 => SCLK = 132.5 MHz */
#define L502_PLL_CTL (SET_MSEL(53) | DF)
#define L502_PLL_DIV (SET_SSEL(4) | CSEL_DIV1)
/* конфигурим SDRAM
* RDIV=((117964,8*64ms)/8192)-(6+3)=912 // по логике - это последняя конфигурация
* кстати - возможно не 8192, а 4096, в таком случае 1834
*/
#define L502_SDRAM_SDRRC (((132500000 / 1000) * 64) / 8192 - (6 + 3))
/* размер памяти - 32 Мб, 9 бит - под адрес колонки */
#define L502_SDRAM_SDBCTL (EBE | EBSZ_32 | EBCAW_9)
/* CAS latency=3, хотя можно и 2 - чем меньше тем лучше (правда при этом глюки появляются!!!!)
* PASR_ALL - тоже для SDRAM с 2.5 В - экономия энергии, поэтому рефрешим все
* tRAS(min)=45 нс (при частоте 120 Мгц - 6 тактов)
* tRP(min)=20 нс (при частоте 120 Мгц - 3 тактов)
* tRCD(min)=20 нс (при частоте 120 Мгц - 3 тактов)
* tWR - хз, на вскидку 2
* POWER startup delay - не нужна
* PSS - power SDRAM - должно быть
* SRFS - нужна для перевода SDRAM в режим пониженного энергопотребления 0 не нужно
* EBUFE=0 - только один чип SDRAM
* FBBRW=0 - для того, чтобы чтение сразу шло за записью, может не работать - попробовать позже
* EMREN=0 - тоже для SDRAM с 2.5 В - экономия энергии
* TCSR=0 - тоже для SDRAM с 2.5 В - экономия энергии
* CDDBG=0 - по моему сотекщд signals не расшарены
*/
#define L502_SDRAM_SDGCTL (SCTLE | CL_2 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
uint32_t l502_otp_make_invalid(uint32_t page) {
uint32_t err = bfrom_OtpCommand(OTP_INIT, (0x0A548800 | 133));
if(!err) {
uint64_t val = (uint64_t)3 << OTP_INVALID_P;
err = bfrom_OtpWrite(page, OTP_LOWER_HALF | OTP_NO_ECC, &val);
}
return err;
}
/* Настройка частоты BlackFin'a */
void l502_setup_pll(void) {
ADI_SYSCTRL_VALUES sysctl;
sysctl.uwPllCtl = L502_PLL_CTL;
bfrom_SysControl(SYSCTRL_WRITE | SYSCTRL_PLLCTL, &sysctl, 0);
}
/* Запись настроек PLL и SDRAM в блок OTP, начиная с заданной страницы */
uint32_t l502_otp_write_cfg(uint32_t first_page) {
uint32_t err = bfrom_OtpCommand(OTP_INIT, (0x0A548800 | 133));
uint64_t val = 0;
if (!err) {
val = ((uint64_t)L502_PLL_DIV << OTP_PLL_DIV_P) | ((uint64_t)L502_PLL_CTL << OTP_PLL_CTL_P)
| ((uint64_t)OTP_SET_PLL_M<< 32)| ((uint64_t)OTP_LOAD_PBS02L_M<<32);
err = bfrom_OtpWrite(first_page, OTP_LOWER_HALF | OTP_CHECK_FOR_PREV_WRITE, &val);
if (!err) {
val = ((uint64_t)L502_SDRAM_SDRRC << OTP_EBIU_SDRCC_P) | ((uint64_t)L502_SDRAM_SDBCTL << OTP_EBIU_SDBCTL_P)
| ((uint64_t)L502_SDRAM_SDGCTL << OTP_EBIU_SDGCTL_P);
err = bfrom_OtpWrite(PBS02-PBS00+first_page, OTP_LOWER_HALF
| OTP_CHECK_FOR_PREV_WRITE, &val);
}
/* если была ошибка - делаем недействительным весь блок */
if (err)
l502_otp_make_invalid(first_page);
}
return err;
}
/* Проверяем, есть ли действтиельные настройки PLL и SDRAM в OTP. Если нет,
то записываем их в OTP и инициализируем PLL вручную */
void l502_otp_init(void) {
uint32_t err=0, page, fnd=0, pll_setup=0;
//err = l502_otp_make_invalid(PBS00);
/* ищем первый действительный блок настройки загрузки */
for (page = PBS00; !(fnd && !err) && (page < 0xD8); page += 4) {
uint64_t val;
err = bfrom_OtpRead(page, OTP_LOWER_HALF, &val);
if (!err && !((val>>OTP_INVALID_P)&0x3)) {
fnd = 1;
if (!val) {
/* если блок с настройками не был записан => PLL записываем
вручную и записываем настройки для корректной инициализации
в дальнейшем */
if (!pll_setup) {
l502_setup_pll();
pll_setup = 1;
}
err = l502_otp_write_cfg(page);
page+=4;
if (!err && (page< 0xD8)) {
/* если есть место - то дописываем вторую копию, чтобы всегда
быть уверенным, что если даже при первом чтении была ошибка,
все загрузится нормально */
err = l502_otp_write_cfg(page);
}
}
}
}
/* если все страницы настроек испорчены, то инициализируем PLL,
так как скорее всего его система не проинициализировала */
if (!fnd && !pll_setup) {
l502_setup_pll();
}
}
void l502_init(void) {
/* инициализация OTP-памяти и PLL, если эти значения не были уже
* проинициализированны до этого. Если в OTP уже были нужные значения, то
* SDRAM и PLL проинициализированы уже загрузочным кодом BlackFin */
l502_otp_init();
/* настройка SPI */
fpga_spi_init();
/* настройки SPORT0 */
*pSPORT0_TCLKDIV = 0;
*pSPORT0_RCLKDIV = 0;
/* clk - internal, fs - external, req, active high, early */
*pSPORT0_TCR1 = ITCLK | TFSR; //TCKFE-???
*pSPORT0_RCR1 = IRCLK | RFSR | RCKFE;
/* len = 16 bit, secondary enable */
*pSPORT0_TCR2 = SLEN(15) | TXSE;
*pSPORT0_RCR2 = SLEN(15) | RXSE;
*pPORTF_MUX = (*pPORTF_MUX & 0xFFFC) | 1;
*pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF7;
/* назначение SPORT RX на IVG7 */
*pSIC_IAR2 = (*pSIC_IAR2 & 0xFFFFFFF0UL) | P16_IVG(7);
REGISTER_ISR(7, isr_sport_dma_rx);
/* SPORT TX оставляем на IVG9 */
REGISTER_ISR(9, isr_sport_dma_tx);
/* настройка HostDMA-интерфейса */
hdma_init();
/* если SDRAM не настроена, то инициализируем ее */
if (*pEBIU_SDSTAT & SDRS) {
uint32_t* a=0;
*pEBIU_SDRRC = L502_SDRAM_SDRRC;
*pEBIU_SDBCTL = L502_SDRAM_SDBCTL;
*pEBIU_SDGCTL = L502_SDRAM_SDGCTL;
ssync();
*a = 0; /* записываем по нулевому адресу произвольное слово, чтобы активировать память */
while (*pEBIU_SDSTAT & SDRS) {}
}
/* инициализируем параметры для потоков ввода/вывода */
l502_stream_init();
}
src/l502_params.c
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/** @addtogroup config_params
@{
@file l502_params.c
Ôàéë ñîäåðæèò ôóíêöèè ïî îáðàáîòêå êîìàíä îò ÏÊ íà óñòàíîâêó ïàðàìåòðîâ
êîíôèãóðàöèè ñáîðà äàííûõ è äðóãèõ ïàðàìåòðîâ.
Òîëüêî â äàííîì ôàéëå äîëæíû áûòü èçìåíåíèÿ ïîëåé ñòðóêòóðû îáùèõ
íàñòðîåê - g_set.
Òàê æå çäåñü */
#include <stdint.h>
#include <stdlib.h>
#include "l502_global.h"
#include "l502_cmd.h"
#include "l502_fpga.h"
#include "l502_params.h"
#include "l502_stream.h"
/* ïðîâåðêà ïðàâèëüíîãî ðåæèìà ñèíõðîíèçàöèè */
#define CHECK_SYNC_MODE(cmd) (((cmd) != L502_SYNC_INTERNAL) \
&& ((cmd) !=L502_SYNC_EXTERNAL_MASTER) \
&& ((cmd) != L502_SYNC_DI_SYN1_RISE) \
&& ((cmd) != L502_SYNC_DI_SYN2_RISE) \
&& ((cmd) != L502_SYNC_DI_SYN1_FALL) \
&& ((cmd) != L502_SYNC_DI_SYN2_FALL) ? L502_BF_ERR_INVALID_CMD_PARAMS : 0)
t_settings g_set = {
.lch_cnt = 1,
.adc_freq_div = 1,
.adc_frame_delay = 0,
.din_freq_div = 2,
.ref_freq = L502_REF_FREQ_2000KHZ,
.out_freq_div = X502_OUT_FREQ_DIV_DEFAULT,
.sync_mode = L502_SYNC_INTERNAL,
.sync_start_mode = L502_SYNC_INTERNAL
};
t_module_info g_module_info;
/** @brief Óñòàíîâêà êîëè÷åñòâà ëîãè÷åñêèõ êàíàëîâ
Ïðîâåðêà è çàïèñü â ïîëå g_set.lch_cnt çíà÷åíèå êîë-âà êàíàëîâ â ëîãè÷åñêîé
òàáëèöå ÀÖÏ.
@param[in] lch_cnt Êîëè÷åñòâî ëîãè÷åñêèõ êàíàëîâ (îò 1 äî #L502_LTABLE_MAX_CH_CNT)
@return Êîä îøèáêè */
int32_t params_set_lch_cnt(uint32_t lch_cnt) {
if (lch_cnt > L502_LTABLE_MAX_CH_CNT)
return L502_BF_ERR_INVALID_CMD_PARAMS;
g_set.lch_cnt = lch_cnt;
return 0;
}
/** @brief Óñòàíîâèòü ïàðàìåòðû ëîãè÷åñêîãî êàíàëà
Ôóíêöèÿ ïðîâåðÿåò âõîäíûå ïàðàìåòðû è çàïèñûâàåò èõ â ñîîòâåòñòâóþùåå ïîëå
òàáëèöû g_set.lch[]
@param[in] index Íîìåð ëîãè÷åñêîãî êàíàëà [0, L502_LTABLE_MAX_CH_CNT-1]
@param[in] ch Íîìåð ôèçè÷åñêîãî êàíàëà (îò 0 äî 15 èëè 31)
@param[in] mode Ðåæèì èçìåðåíèÿ äëÿ äàííîãî ëîã. êàíàëà
@param[in] range Äèàïàçîí èçìåðåíèÿ äëÿ äàííîãî ëîã. êàíàëà
@param[in] avg Êîýô. óñðåäíåíèÿ ïî äàííîìó ëîã. êàíàëó
@param[in] flags Äîïîëíèòåëüíûå ôëàãè
@return Êîä îøèáêè */
int32_t params_set_lch(uint32_t index, uint32_t ch, t_l502_lch_mode mode,
t_l502_adc_range range, uint32_t avg, uint32_t flags) {
if (index >= L502_LTABLE_MAX_CH_CNT)
return L502_BF_ERR_INVALID_CMD_PARAMS;
if ((mode!=L502_LCH_MODE_COMM) && (mode != L502_LCH_MODE_DIFF) &&
(mode!=L502_LCH_MODE_ZERO))
return L502_BF_ERR_INVALID_CMD_PARAMS;
if ((ch >= 32) || ((mode != L502_LCH_MODE_COMM) && (ch>=16)))
return L502_BF_ERR_INVALID_CMD_PARAMS;
g_set.lch[index].phy_ch = ch;
g_set.lch[index].mode = mode;
g_set.lch[index].range = range;
g_set.lch[index].avg = avg;
g_set.lch[index].flags = flags;
return 0;
}
/** Óñòàíîâêà äåëèòåëÿ ÷àñòîòû ÀÖÏ
@param[in] div Çíà÷åíèå äåëèòåëÿ
@return Êîä îøèáêè */
int32_t params_set_adc_freq_div(uint32_t div) {
if ((div==0) || (div > L502_ADC_FREQ_DIV_MAX))
return L502_BF_ERR_INVALID_CMD_PARAMS;
g_set.adc_freq_div = div;
return 0;
}
/** Óñòàíîâêà çíà÷åíèÿ îïîðíîé ÷àñòîòû
@param[in] freq_code Çíà÷åíèå ÷àñòîòû. Äëÿ âíóòðåííåé ìîæåò áûòü òîëüêî
#L502_REF_FREQ_2000KHZ èëè #L502_REF_FREQ_1500KHZ
@return Êîä îøèáêè */
int32_t params_set_ref_freq(uint32_t freq_code) {
g_set.ref_freq = freq_code;
return 0;
}
/** Óñòàíîâêà çíà÷åíèÿ ìåæêàäðîâîé çàäåðæêè
@param[in] delay Çíà÷åíèå ìåæêàäðîâîé çàäåðæêè (îò 0 äî L502_ADC_INTERFRAME_DELAY_MAX)
@return Êîä îøèáêè */
int32_t params_set_adc_interframe_delay(uint32_t delay) {
if (delay > L502_ADC_INTERFRAME_DELAY_MAX)
return L502_BF_ERR_INVALID_CMD_PARAMS;
g_set.adc_frame_delay = delay;
return 0;
}
/** Óñòàíîâêà èñòî÷íèêà îïðîíîé ÷àñòîòû ñèíõðîíèçàöèè
@param[in] sync_mode Çíà÷åíèå èç #t_l502_sync_mode
@return Êîä îøèáêè */
int32_t params_set_sync_mode(t_l502_sync_mode sync_mode) {
int32_t err = CHECK_SYNC_MODE(sync_mode);
if (!err)
g_set.sync_mode = sync_mode;
return err;
}
/** Óñòàíîâêà èñòî÷íèêà ñèíõðîíèçàöèè ñòàðòà ñáîðà äàííûõ
@param[in] sync_mode Çíà÷åíèå èç #t_l502_sync_mode
@return Êîä îøèáêè */
int32_t params_set_sync_start_mode(t_l502_sync_mode sync_mode) {
int32_t err = CHECK_SYNC_MODE(sync_mode);
if (!err)
g_set.sync_start_mode = sync_mode;
return err;
}
/** Óñòàíîâêà äåëèòåëÿ ÷àñòîòû ñèíõðîííîãî ââîäà öèôðîâûõ ëèíèé
@param[in] div Çíà÷åíèå äåëèòåëÿ
@return Êîä îøèáêè */
int32_t params_set_din_freq_div(uint32_t div) {
if ((div==0) || (div > L502_DIN_FREQ_DIV_MAX))
return L502_BF_ERR_INVALID_CMD_PARAMS;
g_set.din_freq_div = div;
return 0;
}
/** Óñòàíîâêà äåëèòåëÿ ÷àñòîòû âûâîäà íà ÖÀÏ
@param[in] div Çíà÷åíèå äåëèòåëÿ (1 èëè 2)
@return Êîä îøèáêè */
int32_t params_set_dac_freq_div(uint32_t div) {
if ((div < X502_OUT_FREQ_DIV_MIN) || (div > X502_OUT_FREQ_DIV_MAX))
return L502_BF_ERR_INVALID_CMD_PARAMS;
g_set.out_freq_div = div;
return 0;
}
/** @brief Çàïèñü ïàðàìåòðîâ ñáîðà â ðåãèñòðû ÏËÈÑ
Ôóíêöèÿ âûïîëíÿåò çàïèñü âñåõ ïàðàìåòðîâ èç ñòðóêòóðû #g_set â ðåãèñòðû
ÏËÈÑ. Ôóíêöèÿ ìîæåò âûçûâàòüñÿ òîëüêî êîãäà ñáîð äàííûõ îñòàíîâëåí.
@return Êîä îøèáêè */
int32_t configure(void) {
uint16_t ch;
int32_t err = g_mode != L502_BF_MODE_IDLE ? L502_BF_ERR_STREAM_RUNNING : 0;
if (!err) {
/* çàïèñûâàåì ëîãè÷åñêóþ òàáëèöó */
for (ch = 0; ch < g_set.lch_cnt; ch++) {
uint32_t wrd = ((g_set.lch[ch].phy_ch & 0xF) << 3) | (g_set.lch[ch].range & 0x7);
if (g_set.lch[ch].mode == L502_LCH_MODE_ZERO) {
wrd |= (3 << 7);
} else if (g_set.lch[ch].mode == L502_LCH_MODE_COMM) {
wrd |= (g_set.lch[ch].phy_ch & 0x10 ? 2 : 1) << 7;
}
if (g_set.lch[ch].avg)
wrd |= ((g_set.lch[ch].avg-1) & 0x7F) << 9;
fpga_reg_write(L502_REGS_IOHARD_LTABLE + g_set.lch_cnt - 1 - ch, wrd);
}
fpga_reg_write(L502_REGS_IOHARD_LCH_CNT, g_set.lch_cnt - 1);
fpga_reg_write(L502_REGS_IOHARD_ADC_FREQ_DIV, g_set.adc_freq_div - 1);
fpga_reg_write(L502_REGS_IOARITH_ADC_FREQ_DIV, g_set.adc_freq_div - 1);
fpga_reg_write(L502_REGS_IOHARD_ADC_FRAME_DELAY, g_set.adc_frame_delay);
fpga_reg_write(L502_REGS_IOHARD_IO_MODE, (g_set.sync_mode & 0x7)
| ((g_set.sync_start_mode&0x7)<<3)
| ((g_set.ref_freq==L502_REF_FREQ_2000KHZ ? 0 : 2) << 7)
| (((g_set.out_freq_div-1)&0x3FF)<<9));
fpga_reg_write(L502_REGS_IOHARD_DIGIN_FREQ_DIV, g_set.din_freq_div - 1);
}
return err;
}
/** @} */
src/l502_params.h
+79
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/** @defgroup config_params Íàñòðîéêè ñáîðà äàííûõ ìîäóëÿ */
/***************************************************************************//**
@addtogroup config_params
@{
@file l502_params.h
Ôàéë ñîäåðæèò îïðåäåëåíèå ñòðóêòóð, îïèñûâàþùèõ òåêóùèå
íàñòðîéêè ñáîðà äàííûõ äëÿ ìîäóëÿ è îáúÿâëÿåò
âíåøíþþ ïåðåìåííóþ g_set, ñîäåðæàùóþ ýòè ïàðàìåòðû
*******************************************************************************/
#ifndef L502_PARAMS_H_
#define L502_PARAMS_H_
#include "l502_defs.h"
/** Êàëèáðîâî÷íûå êîýôôèöèåíòû ÖÀÏ */
typedef struct {
float offs; /**< Ñìåùåíèå íóëÿ */
float k; /**< Êîýôôèöèåíò øêàëû */
} t_dac_cbr_coef;
/** Èíôîðìàöèÿ î èñïîëüçóåìîì ìîäóëå */
typedef struct {
uint32_t devflags; /**< Ôëàãè ñ èíôîðìàöèåé î íàëè÷èè îïöèé è ñîñò. ìîäóëÿ */
uint16_t fpga_ver; /**< Âåðñèÿ FPGA */
uint8_t plda_ver; /**< Âåðñèÿ PLDA */
t_dac_cbr_coef dac_cbr[L502_DAC_CH_CNT]; /**< Êîýôôèöèåíòû ÖÀÏ */
} t_module_info;
/** Ïàðàìåòðû ëîãè÷åñêîãî êàíàëà */
typedef struct {
uint8_t phy_ch; /**< Íîìåð ôèçè÷åñêîãî êàíàëà */
uint8_t mode; /**< Ðåæèì ñáîðà */
uint8_t range; /**< Äèàïàçîí */
uint8_t avg; /**< Êîýô. óñðåäíåíèÿ */
uint32_t flags; /**< Äîï. ôëàãè */
} t_lch;
/** Íàñòðîéêè ñáîðà äàííûõ */
typedef struct {
/** Òàáëèöà ëîãè÷åñêèõ êàíàëîâ */
t_lch lch[L502_LTABLE_MAX_CH_CNT];
uint16_t lch_cnt; /**< Êîëè÷åñòâî êàíàëîâ â ëîã. òàáëèöå */
uint32_t adc_freq_div; /**< Äåëèòåëü ÷àñòîòû ÀÖÏ */
uint32_t din_freq_div; /**< Äåëèòåëü ÷àñòîòû äëÿ öèôðîâîãî âõîäà */
uint32_t adc_frame_delay; /**< Ìåæêàäðîâàÿ çàäåðæêà */
uint32_t ref_freq; /**< Çíà÷åíèå îïîðíîé ÷àñòîòû (2 èëè 1.5 ÌÃö) èëè âíåøíÿÿ */
uint16_t out_freq_div; /**< Äåëèòåëü ÷àñòîòû âûâîäà */
uint8_t sync_mode; /**< Ðåæèì ñèíõðîíèçàöèè äëÿ îïîðíîé ÷àñòîòû */
uint8_t sync_start_mode; /**< Ðåæèì çàïóñêà ñèãíàëà ñèíõðîíèçàöèè */
} t_settings;
/** Ñòðóêòóðà, ñîäåðæàùàÿ òåêóùèå íàñòðîéêè ñáîðà äàííûõ */
extern t_settings g_set;
/** Ñòðóêòóðà, ñîäåðæàùàÿ èíôîðìàöèþ î ìîäóëå */
extern t_module_info g_module_info;
int32_t configure(void);
int32_t params_set_lch_cnt(uint32_t lch_cnt);
int32_t params_set_lch(uint32_t index, uint32_t ch, t_l502_lch_mode mode,
t_l502_adc_range range, uint32_t avg, uint32_t flags);
int32_t params_set_adc_freq_div(uint32_t div);
int32_t params_set_adc_interframe_delay(uint32_t delay);
int32_t params_set_ref_freq(uint32_t freq_code);
int32_t params_set_sync_mode(t_l502_sync_mode sync_mode);
int32_t params_set_sync_start_mode(t_l502_sync_mode sync_mode);
int32_t params_set_din_freq_div(uint32_t div);
int32_t params_set_dac_freq_div(uint32_t div);
int32_t params_set_dac_freq_div(uint32_t div);
#endif
/** @} */
src/l502_sport_rx.h
+23
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/** @defgroup sport_rx Ïðèåì ïîòîêà äàííûõ ïî SPORT0 */
/***************************************************************************//**
@addtogroup sport_rx
@{
@file l502_sport_rx.h
Ôàéë ñîäåðæèò îïèñàíèÿ ôóíêöèé äëÿ óïðàâëåíèÿ ïðèåìîì ïîòîêà ïî SPORT0
******************************************************************************/
#ifndef L502_SPORT_RX_H
#define L502_SPORT_RX_H
#include <stdint.h>
void sport_rx_start(void);
void sport_rx_stop(void);
int32_t sport_in_set_step_size(uint32_t size);
#endif // L502_SPORT_RX_H
/** @} */
src/l502_sport_tx.c
+238
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/** @addtogroup sport_tx
@{
@file l502_sport_tx.c
Файл содержит логику для управления передачей по SPORT0.
Изначально DMA должен быть проинициализирован с помощью sport_tx_init(),
Передача начинается с помщью sport_tx_start_req(). Можно поставить до 16
запросов одновременно.
Останвить все текущие передачи можно с помощью sport_tx_stop().
***********************************************************************/
#include <stdint.h>
#include <stdlib.h>
#include <cdefBF523.h>
#include <sys/exception.h>
#include <ccblkfn.h>
#include "l502_sport_tx.h"
#include "l502_cdefs.h"
#include "l502_fpga_regs.h"
#include "l502_fpga.h"
#include "l502_bf_cmd_defs.h"
#include "l502_defs.h"
#include "l502_stream.h"
#define SPORT_TX_DESCR_CNT 16
#define SPORT_TX_DMA_CFG_WAIT (DMAEN | DI_EN | WDSIZE_16 | SYNC)
#define SPORT_TX_DMA_CFG_START (SPORT_TX_DMA_CFG_WAIT | NDSIZE_5 | FLOW_SMALL)
/* дескриптор DMA размера 5 16-битных слов */
typedef struct {
uint16_t ndpl;
uint16_t sal;
uint16_t sah;
uint16_t cfg;
uint16_t xcnt;
} t_sport_dma_descr;
static t_sport_dma_descr f_descrs[SPORT_TX_DESCR_CNT];
static uint8_t f_put_descr, f_done_descr;
static volatile int f_put_cnt, f_done_cnt;
static int f_first;
static volatile int f_tx_was_empty = 0;
void sport_tx_done(uint32_t* addr, uint32_t size);
/***************************************************************************//**
@brief Чтение флагов статуса вывода
@return Флаги статуса --- набор битов из #t_x502_out_status_flags,
объединенных через логическое “ИЛИ”.
******************************************************************************/
uint32_t sport_tx_out_status(void) {
uint32_t ret = 0;
if (f_put_cnt == f_done_cnt)
ret |= X502_OUT_STATUS_FLAG_BUF_IS_EMPTY;
if (f_tx_was_empty) {
ret |= X502_OUT_STATUS_FLAG_BUF_WAS_EMPTY;
f_tx_was_empty = 0;
}
return ret;
}
/** @brief Начальная инициализация канала DMA на передачу по SPORT.
Функция устанавливает параметры DMA которые не меняются при последующей работе
прошивки */
void sport_tx_init(void) {
int i;
for (i=0; i < SPORT_TX_DESCR_CNT; i++) {
f_descrs[i].cfg = SPORT_TX_DMA_CFG_WAIT;
f_descrs[i].ndpl = i==(SPORT_TX_DESCR_CNT-1) ? (uint32_t)&f_descrs[0]&0xFFFF :
(uint32_t)&f_descrs[i+1]&0xFFFF;
}
*pDMA4_NEXT_DESC_PTR = f_descrs;
*pDMA4_X_MODIFY = 2;
f_put_cnt = f_done_cnt = 0;
f_put_descr = f_done_descr = 0;
f_first = 1;
}
/* Функция разрешает канал DMA для передачи данных в SPORT0 и саму передачу
* для SPORT 0 */
static void f_sport_tx_start(void) {
/* разрешаем передачу по SPORT'у */
*pSPORT0_TCR1 |= TSPEN;
f_first = 0;
f_tx_was_empty = 0;
}
/** @brief Останов сбора по SPORT0.
*
* Функция запрещает прием по SPORT0 и соответствующий канал DMA на прем */
void sport_tx_stop(void) {
*pSIC_IMASK0 &= ~IRQ_DMA4;
*pDMA4_CONFIG = 0;
/* нужно подождать до 3-х циклов, чтобы DMA действительно завершился */
ssync();
ssync();
ssync();
/* запрет передачи по SPORT */
*pSPORT0_TCR1 &= ~TSPEN;
/* сбрасываем признаки прерываний от DMA */
*pDMA4_IRQ_STATUS = DMA_DONE | DMA_ERR;
/* заново инициализируем все дескрипторы */
sport_tx_init();
}
/**************************************************************************//**
@brief Получить количество свободных дескрипторов на передачу
Функция возвращает количество запросов, которое можно поставить в очередь
на передачу с помощью sport_tx_start_req().
@return Количество запросов на передачу, которое можно поставить в очередь
******************************************************************************/
int sport_tx_req_rdy(void) {
return SPORT_TX_DESCR_CNT - (f_put_cnt - f_done_cnt + 1);
}
/**************************************************************************//**
@brief Поставить запрос на передачу по SPORT0
Функция ставит запрос на передачу указанных данных. Сами данные не копируются,
т.е. буфер нельзя будет использовать до того, как данные не будут переданы!
Для постановки запроса необходимо, чтобы был свободный дескриптор (можно
узнать через sport_tx_req_rdy()).
Количество слов в запросе не должно превышать #SPORT_TX_REQ_SIZE_MAX
При добавление первого дескриптора автомтически разрешается передача по
DMA и SPORT0.
@param[in] buf Указатель на массив на передачу.
@param[in] size Количество 32-битных слов на передачу
*******************************************************************************/
void sport_tx_start_req(uint32_t* buf, uint32_t size) {
/* запрещаем прерывание от DMA на случай гонок с изменением позиций */
*pSIC_IMASK0 &= ~IRQ_DMA4;
f_descrs[f_put_descr].sal = (uint32_t)buf & 0xFFFF;
f_descrs[f_put_descr].sah = ((uint32_t)buf >> 16) & 0xFFFF;
f_descrs[f_put_descr].xcnt = size*2;
f_descrs[f_put_descr].cfg = SPORT_TX_DMA_CFG_WAIT;
/* убеждаемся, что данные будут уже записаны в память к моменту запуска DMA */
ssync();
/* если DMA сейчас остановлен => запускаем его */
if (f_put_cnt==f_done_cnt) {
uint32_t cfg_wrd = SPORT_TX_DMA_CFG_START;
*pDMA4_CONFIG = cfg_wrd;
if (f_first)
f_sport_tx_start();
}
if (f_put_cnt!=f_done_cnt) {
uint8_t prev_descr = (f_put_descr==0) ? SPORT_TX_DESCR_CNT-1 : f_put_descr-1;
f_descrs[prev_descr].cfg = SPORT_TX_DMA_CFG_START;
}
if (++f_put_descr==SPORT_TX_DESCR_CNT)
f_put_descr=0;
f_put_cnt++;
*pSIC_IMASK0 |= IRQ_DMA4;
}
/** @brief Обработчик прерывания по SPORT0 на завершение передачи.
Прерывание возникает, когда был передан блок данных по SPORT0, соответствующий
одному дескриптору.
Функция рассчитывает количество переданных данных и вызывает sport_tx_done().
Также функция помечает дескриптор как свободный и при необходимости
снова запускает DMA (если он был остановлен, но при этом уже добавлен новый
дескриптор на передачу) */
ISR( isr_sport_dma_tx) {
if (*pDMA4_IRQ_STATUS & DMA_DONE) {
uint32_t* addr;
uint32_t size;
uint32_t status;
*pDMA4_IRQ_STATUS = DMA_DONE;
/* обработку выполняем только в случае, если есть начатые, но не завершенные
дескрипторы */
if (f_done_cnt != f_put_cnt) {
f_done_cnt++;
f_descrs[f_done_descr].cfg = SPORT_TX_DMA_CFG_WAIT;
addr = ((uint32_t*)(f_descrs[f_done_descr].sal |
((uint32_t)f_descrs[f_done_descr].sah<<16)) + f_descrs[f_done_descr].xcnt*2);
size = f_descrs[f_done_descr].xcnt/2;
if (!size)
size = 0x8000;
sport_tx_done(addr, size);
if (++f_done_descr==SPORT_TX_DESCR_CNT)
f_done_descr=0;
ssync();
status = *pDMA4_IRQ_STATUS;
/* если DMA остановлен, а дескрипторы на передачу еще есть => запускаем снова */
if ((f_done_cnt != f_put_cnt) && !(status & DMA_RUN)) {
*pDMA4_CONFIG = SPORT_TX_DMA_CFG_START;
}
if (f_done_cnt == f_put_cnt) {
ssync();
}
if ((g_stream_out_state == OUT_STREAM_RUN) && (f_done_cnt == f_put_cnt))
f_tx_was_empty = 1;
}
}
if (*pDMA4_IRQ_STATUS & DMA_ERR) {
*pDMA4_IRQ_STATUS = DMA_ERR;
}
}
/** @} */
src/l502_sport_tx.h
+28
View File
@@ -0,0 +1,28 @@
/** @defgroup sport_tx Ïåðåäà÷à ïîòîêà äàííûõ ïî SPORT0 */
/***************************************************************************//**
@addtogroup sport_tx
@{
@file l502_sport_tx.h
Ôàéë ñîäåðæèò îïèñàíèÿ ôóíêöèé äëÿ óïðàâëåíèÿ ïåðåäà÷è ïîòîêà ïî SPORT0
******************************************************************************/
#ifndef L502_SPORT_TX_H
#define L502_SPORT_TX_H
/** Ìàêñèìàëüíûé ðàçìåð ïðè ïåðåäà÷å â ôóíêöèþ sport_tx_start_req() */
#define SPORT_TX_REQ_SIZE_MAX (16*1024)
void sport_tx_init(void);
void sport_tx_stop(void);
int sport_tx_req_rdy(void);
void sport_tx_start_req(uint32_t* addr, uint32_t size);
uint32_t sport_tx_out_status(void);
#endif
/** @} */
src/l502_stream.c
+570
View File
@@ -0,0 +1,570 @@
/**
@addtogroup streams
@{
@file l502_stream.c
Файл содержит функции обработки потоков от АЦП/DIN в ПК и от ПК в ЦАП/DOUT.
Также в этот файл внесена реализация функций приема по SPORT0, так как они
связаны с логикой управления потоков.
*/
#include <stdint.h>
#include <stdlib.h>
#include <cdefBF523.h>
#include <sys/exception.h>
#include <ccblkfn.h>
#include "l502_cdefs.h"
#include "l502_cmd.h"
#include "l502_fpga.h"
#include "l502_defs.h"
#include "l502_global.h"
#include "l502_hdma.h"
#include "l502_sport_tx.h"
#include "l502_user_process.h"
#include "l502_stream.h"
#include "l502_sport_rx.h"
/** Размер буфера на прием данных по SPORT0 в 32-битных словах */
#define L502_SPORT_IN_BUF_SIZE (2048*1024)
/** Размер буфера для приема данных по HostDMA на вывод в 32-битных словах */
#define L502_HDMA_OUT_BUF_SIZE (1024*1024)
/** Шаг прерываний для приема данных по SPORT0 по-умолчанию */
#define L502_DEFAULT_SPORT_RX_BLOCK_SIZE (32*1024)
t_in_stream_state g_stream_in_state = IN_STREAM_STOP;
t_out_stream_state g_stream_out_state = OUT_STREAM_STOP;
/** Режим работы - определяет, запущен ли синхронный сбор или тест */
volatile int g_mode = L502_BF_MODE_IDLE;
int g_streams = L502_STREAM_ADC;
static int f_bf_reg = 0;
/* слово, обозначающее, что произошло переполнение */
static const uint32_t f_overflow_wrd = L502_STREAM_IN_MSG_OVERFLOW;
/* буфер для приема digin и данных АЦП от SPORT (в неинициализируемой области) */
#include "l502_sdram_noinit.h"
static volatile uint32_t f_sport_in_buf[L502_SPORT_IN_BUF_SIZE];
/* позиция в буфере в которую будет записан следующий принятых отсчет */
static volatile uint32_t f_sport_in_put_pos = 0;
/* позиция в буфере за последним обработанным отсчетом */
static uint32_t f_sport_in_proc_pos = 0;
/* позиция в буфере за последним изятым из буфера отсчетом (позиция первого занятого отсчета) */
static volatile uint32_t f_sport_in_get_pos = 0;
/* шаг прерываний на прием по SPORT0 */
static uint32_t f_sport_in_block_size = L502_DEFAULT_SPORT_RX_BLOCK_SIZE;
/* реально используемый размер входного буфера на прием */
static uint32_t f_sport_in_buf_size = L502_SPORT_IN_BUF_SIZE;
/* буфер для прв кинятых данных по HDMA для вывода на ЦАП и DIGOUT */
#include "l502_sdram_noinit.h"
static volatile uint32_t f_hdma_out_buf[L502_HDMA_OUT_BUF_SIZE];
static volatile uint32_t f_hdma_out_put_pos = 0; /* указатель на позицию за последним принятым по HDMA */
static uint32_t f_hdma_out_start_pos; /* указатель на позицию за последним поставленным на прием словом
(с нее будет стартовать следующий запрос) */
static volatile uint32_t f_hdma_out_get_pos = 0; /* указатель на позицию за последним обработанным словом
(с нее будет взято следующее слово для обработки, когда будет готово */
static int f_hdma_out_block_size = 0x8000;
static int f_hdma_out_proc_pos;
static uint32_t f_recv_size = 0;
/* функция вызывается при возникновении переполнения буфера на прием
по SPORT'у данных АЦП/DIGIN */
static void f_stream_in_set_overflow(void) {
/* останавливаем прием данных от АЦП */
sport_rx_stop();
/* устанавливаем флаг, что нужно передать сообщение о
переполнении */
g_stream_in_state = IN_STREAM_OV_ALERT;
}
/** @brief Начальная инициализация параметров для синхронных потоков */
void l502_stream_init(void) {
/* останавливаем сбор данных, если он был запущен */
fpga_reg_write(L502_REGS_IOHARD_GO_SYNC_IO, 0);
fpga_reg_write(L502_REGS_IOHARD_OUTSWAP_BFCTL, 0);
/* настройка DMA на передачу по SPORT */
sport_tx_init();
}
/** @brief Запуск предзагрузки данных на вывода
Данная функция запускает предзагрузку данных потока на вывод.
Используется, чтобы загрузить данные в буфер BlackFin до запуска синхронного
ввода-вывода.
@return Код ошибки */
int32_t stream_out_preload(void) {
int32_t err = g_stream_out_state==OUT_STREAM_RUN ? L502_BF_ERR_STREAM_RUNNING :
0;
if (!err) {
f_hdma_out_get_pos = f_hdma_out_start_pos =
f_hdma_out_put_pos = f_hdma_out_proc_pos = 0;
/* разрешаем прием по HDMA */
hdma_recv_start();
/* запускаем первый блок на прием (остальные будут
добавлены из stream_proc() */
f_hdma_out_start_pos+=f_hdma_out_block_size;
hdma_recv_req_start((uint32_t*)f_hdma_out_buf, f_hdma_out_block_size);
g_stream_out_state = OUT_STREAM_PRELOAD;
}
return err;
}
static void f_set_streams(uint32_t streams) {
uint32_t wrd_en = 0;
/* если уже запущен потоковый режим и разрешается один из
потоков на ввод, то инициализируем прием по SPORT и передачу по hdma */
if (g_mode == L502_BF_MODE_STREAM) {
if ((streams & L502_STREAM_ALL_IN) && !(g_streams & L502_STREAM_ALL_IN)) {
sport_rx_start();
}
if (!(streams & L502_STREAM_ALL_IN) && (g_streams & L502_STREAM_ALL_IN)) {
sport_rx_stop();
}
}
/* изменяем разрешенные потоки в регистре FPGA */
if (streams & L502_STREAM_ADC)
wrd_en |= 0x1;
if (streams & L502_STREAM_DIN)
wrd_en |= 0x2;
fpga_reg_write(L502_REGS_IOARITH_IN_STREAM_ENABLE, wrd_en);
/** @todo: разрешение на лету выходных потоков */
g_streams = streams;
}
/** @brief Разрешение указанных синхронных потоков
@param[in] streams Битовая маска из #t_l502_streams, указывающая какие потоки
должны быть разрешены (в дополнения к уже разрешенным)
@return Код ошибки */
int32_t stream_enable(uint32_t streams) {
f_set_streams(g_streams | streams);
return 0;
}
/** @brief Запрещение указанных синхронных потоков
@param[in] streams Битовая маска из #t_l502_streams, указывающая какие потоки
должны быть запрещены
@return Код ошибки */
int32_t stream_disable(uint32_t streams) {
f_set_streams(g_streams & ~streams);
return 0;
}
/***************************************************************************//**
@brief Запуск синхронного ввода-вывода
Функция запускает синхронный ввод-вывод платы.
При этом начинается передача по всем ранее разрешенным потокам с помощью
stream_enable().
После вызова этой функции изменять настройки модуля уже нельязя, однако
можно дополнительно разрешать или запрещать потоки через stream_enable()
или stream_disable().
@return Код ошибки.
***************************************************************************/
int32_t streams_start(void) {
int32_t err = g_mode != L502_BF_MODE_IDLE ? L502_BF_ERR_STREAM_RUNNING : 0;
if (!err) {
/* прием по SPORT инициализируется всесте с началом запуска
синхронного сбора */
f_sport_in_put_pos = f_sport_in_get_pos = f_sport_in_proc_pos = 0;
if (g_streams & L502_STREAM_ALL_IN) {
sport_rx_start();
g_stream_in_state = IN_STREAM_RUN;
}
hdma_send_start();
f_set_streams(g_streams);
if (g_streams & L502_STREAM_ALL_OUT) {
/* разрешаем ПЛИС генерацию TFS по SPORT */
f_bf_reg |= L502_REGBIT_IOHARD_OUT_TFS_EN_Msk;
fpga_reg_write(L502_REGS_IOHARD_OUTSWAP_BFCTL, f_bf_reg);
/* если не было предзагрузки до запуска,
то запускаем прием сейчас */
if ((g_stream_out_state == OUT_STREAM_STOP) ||
(g_stream_out_state == OUT_STREAM_ERR)) {
stream_out_preload();
}
if (g_stream_out_state == OUT_STREAM_PRELOAD) {
/* выполняем предзагрузку данных */
fpga_reg_write(L502_REGS_IOHARD_OUTSWAP_BFCTL, f_bf_reg | 1);
g_stream_out_state = OUT_STREAM_RUN;
}
}
/* Так как конвейер автомата управления входной коммутации АЦП состоит
из 2-х стадий, для корректного синхронного старта необходимо в
ыполнить два раза предзагрузку. В противном случае,
время момента первого отсчета может не совпадать с моментом
запуска синхронизации
*/
fpga_reg_write(L502_REGS_IOHARD_PRELOAD_ADC, 1);
fpga_reg_write(L502_REGS_IOHARD_PRELOAD_ADC, 1);
fpga_reg_write(L502_REGS_IOHARD_GO_SYNC_IO, 1);
g_mode = L502_BF_MODE_STREAM;
}
return err;
}
/** @brief Останов синхронных потоков ввода-вывода.
По этой функции останавливаются все синхронные потоки.
Запрещается передача потоков по SPORT и по HostDMA
@return Код ошибки */
int32_t streams_stop(void) {
int32_t err = g_mode != L502_BF_MODE_STREAM ? L502_BF_ERR_STREAM_STOPPED : 0;
if (!err) {
hdma_send_stop();
hdma_recv_stop();
fpga_reg_write(L502_REGS_IOHARD_GO_SYNC_IO, 0);
/* запрещаем прием и передачу по SPORT'у */
sport_rx_stop();
sport_tx_stop();
/* запрещаем генерацию TFS и RFS */
f_bf_reg = 0;
fpga_reg_write(L502_REGS_IOHARD_OUTSWAP_BFCTL, f_bf_reg);
g_mode = L502_BF_MODE_IDLE;
g_stream_in_state = IN_STREAM_STOP;
g_stream_out_state = OUT_STREAM_STOP;
}
return err;
}
/** @brief Фоновая обработка потокой ввода-вывода
Функция переодически вызывается из основного цикла программы.
При рабочем режиме, проверяются, есть
ли необработанные данные пришедшие от АЦП/DIGIN и/или пришедшие от ПК данные
на ЦАП или DOUT. При их наличии вызывается соответствующая функция пользовательской
обработки данных.
Также, если было переполнение и все данные до переполнения были обработаны,
то в ПК посылается слово о том, что в этом месте произошло переполнение */
void stream_proc(void) {
/* если запущен поток ввода */
if ((g_stream_in_state != IN_STREAM_STOP) && (g_stream_in_state != IN_STREAM_ERR)) {
uint32_t sport_rdy_size;
uint32_t put_pos = f_sport_in_put_pos;
/* смотрим, сколько принято необработанных данных по sport'у */
sport_rdy_size = put_pos >= f_sport_in_proc_pos ?
put_pos - f_sport_in_proc_pos : f_sport_in_buf_size - f_sport_in_proc_pos;
/* если есть необработанные данные - вызываем функцию для обработки */
if (sport_rdy_size) {
uint32_t processed = usr_in_proc_data(
(uint32_t*)&f_sport_in_buf[f_sport_in_proc_pos],
sport_rdy_size);
/* обновляем счетчик обработканных данных */
f_sport_in_proc_pos += processed;
if (f_sport_in_proc_pos==f_sport_in_buf_size)
f_sport_in_proc_pos = 0;
}
/* если было переполнение - нужно передать слово о переполнениии.
передаем его после того, как передадим все слова до переполнения */
if ((g_stream_in_state == IN_STREAM_OV_ALERT) && !sport_rdy_size && hdma_send_req_rdy()) {
hdma_send_req_start(&f_overflow_wrd, 1, 1);
g_stream_in_state = IN_STREAM_ERR;
}
}
/* если есть поток на вывод */
if ((g_stream_out_state == OUT_STREAM_PRELOAD) ||
(g_stream_out_state == OUT_STREAM_RUN)) {
uint32_t hdma_rdy_size;
uint32_t put_pos = f_hdma_out_put_pos;
/* проверяем, сколько есть необработанных данных, принятых по HDMA */
hdma_rdy_size = put_pos >= f_hdma_out_proc_pos ?
put_pos - f_hdma_out_proc_pos : L502_HDMA_OUT_BUF_SIZE - f_hdma_out_proc_pos;
/* если такие есть -> пробуем обработать */
if (hdma_rdy_size != 0) {
uint32_t processed = usr_out_proc_data(
(uint32_t*)&f_hdma_out_buf[f_hdma_out_proc_pos],
hdma_rdy_size);
/* обновляем счетчик обработанных данных */
f_hdma_out_proc_pos += processed;
if (f_hdma_out_proc_pos==L502_HDMA_OUT_BUF_SIZE)
f_hdma_out_proc_pos = 0;
}
/* если есть свободное место в буфере на прием и есть свободные
дескрипторы => ставим новый запрос на прием даннх */
if (hdma_recv_req_rdy()) {
uint32_t get_pos = f_hdma_out_get_pos;
hdma_rdy_size = f_hdma_out_start_pos >= get_pos ?
L502_HDMA_OUT_BUF_SIZE - f_hdma_out_start_pos + get_pos :
get_pos - f_hdma_out_start_pos;
if (hdma_rdy_size > f_hdma_out_block_size) {
hdma_recv_req_start((uint32_t*)&f_hdma_out_buf[f_hdma_out_start_pos],
f_hdma_out_block_size);
f_hdma_out_start_pos+=f_hdma_out_block_size;
if (f_hdma_out_start_pos==L502_HDMA_OUT_BUF_SIZE)
f_hdma_out_start_pos = 0;
}
}
}
}
/** @brief Освобождение size слов из буфера приема по SPORT0
Функция помечает, что size слов из начала той части буфера SPORT0, в которую
были приняты данные, но не освобождены, как освобожденные. Т.е. в эту область
снова можно будет принимать данные со SPORT0.
При этом надо всегда следить, чтобы количество освобожденных данных не
привышало количество обработанных!
@param[in] size Размер освобожденных данных в 32-битных словах */
void stream_in_buf_free(uint32_t size) {
/* обновляем позицию переданного слова */
uint32_t get_pos = f_sport_in_get_pos;
get_pos += size;
if (get_pos >= f_sport_in_buf_size)
get_pos-= f_sport_in_buf_size;
f_sport_in_get_pos = get_pos;
}
/** @brief Освобождение size слов из буфера приема по HostDMA
Функция помечает, что size слов из начала той части буфера HostDMA, в которую
были приняты данные от ПК, но не освобождены, как освобожденные. Т.е. в эту область
снова можно будет принимать данные от ПК по HostDMA.
При этом надо всегда следить, чтобы количество освобожденных данных не
привышало количество обработанных!
@param[in] size Размер освобожденных данных в 32-битных словах */
void stream_out_buf_free(uint32_t size) {
uint32_t get_pos = f_hdma_out_get_pos;
get_pos += size;
if (get_pos >= L502_HDMA_OUT_BUF_SIZE)
get_pos -= L502_HDMA_OUT_BUF_SIZE;
f_hdma_out_get_pos = get_pos;
}
/** @brief Обработка завершения приема по HostDMA
Функция вызывается из обработчика прерывания, когда завершился прием
блока данных по HDMA в ПК, поставленного до этого на передачу с
помощью hdma_recv_req_start().
Функция просто обновляет счетчик принятых данных (а обработка будет уже
из фоновой функции stream_proc().
@param[in] addr Адрес слова, сразу за последним принятым словом.
@param[in] size Количество принятых 32-битных слов */
void hdma_recv_done(uint32_t* addr, uint32_t size) {
/* обновляем позицию принятого слова */
uint32_t put_pos = f_hdma_out_put_pos;
put_pos += size;
if (put_pos == L502_HDMA_OUT_BUF_SIZE)
put_pos = 0;
f_hdma_out_put_pos = put_pos;
}
/** @brief Размер буфера на прием.
Функция возвращает размер буфера на прием по SPORT0
@return размер буфера на прием в 32-битных словах */
extern uint32_t sport_in_buffer_size(void) {
return L502_SPORT_IN_BUF_SIZE;
}
/** @} */
/** @addtogroup sport_rx
@{ */
/** @brief Установка шага прерывания для према по SPORT0
Функция устанавливает шаг прерываний для DMA, использующегося для
приема данных синхронного ввода.
При этом размер шага должен быть как имнимум в 4 раза меньше размера
буфера #L502_SPORT_IN_BUF_SIZE.
После установки шага определяется реально используемый размер буфера,
как наибольшее число кратное шагу и не превышающее #L502_SPORT_IN_BUF_SIZE.
@param[in] size Размер шага прерывания в 32-битных словах
@return Код ошибки */
int32_t sport_in_set_step_size(uint32_t size) {
int mul;
if ((size >= L502_SPORT_IN_BUF_SIZE/4) || (size > 0x8000))
return L502_BF_ERR_INVALID_CMD_PARAMS;
mul = L502_SPORT_IN_BUF_SIZE/size;
/* не может быть боьше 0x8000 шагов, так как регистр
YCNT 16-разрядный (+ еще умножаем на 2) */
if (mul > 0x8000)
mul = 0x8000;
f_sport_in_buf_size = size*mul;
f_sport_in_block_size = size;
return 0;
}
/** @brief Запуск сбора данных по SPORT0
Функция настраивает DMA3 на режим автобуфера с 2D, размер шага выбирается
равным f_sport_in_block_size. После чего разрешается канал DMA и
прием по SPORT0 */
void sport_rx_start(void) {
static volatile int dummy;
/* запрещаем DMA */
*pDMA3_CONFIG = 0;
ssync();
/* вычитываем все данные из буфера, если они были */
while (*pSPORT0_STAT & RXNE) {
dummy = *pSPORT0_RX16;
ssync();
}
/* настраиваем DMA */
*pDMA3_START_ADDR = (void*)f_sport_in_buf;
*pDMA3_X_COUNT = 2*f_sport_in_block_size; /* так как SPORT настроен на 16 бит (хоть и 2 канала),
а размер в 32 битных словах => умножаем на 2) */
*pDMA3_X_MODIFY = 2;
*pDMA3_Y_COUNT = f_sport_in_buf_size/f_sport_in_block_size;;
*pDMA3_Y_MODIFY = 2;
*pDMA3_CURR_ADDR = (void*)f_sport_in_buf;
*pDMA3_CONFIG = FLOW_AUTO | DI_EN | DI_SEL | SYNC | DMA2D | WNR | WDSIZE_16;
ssync();
/* разрешаем DMA */
*pSIC_IMASK0 |= IRQ_DMA3;
*pDMA3_CONFIG |= DMAEN;
/* разрешаем прием по SPORT'у */
*pSPORT0_RCR1 |= RSPEN;
/* разрешаем генерацию RFS на SPORT0 */
f_bf_reg |= L502_REGBIT_IOHARD_OUT_RFS_EN_Msk;
fpga_reg_write(L502_REGS_IOHARD_OUTSWAP_BFCTL, f_bf_reg);
}
/** @brief Останов сбора данных по SPORT0
Функция запрещает прием по SPORT0 и останавливает DMA */
void sport_rx_stop(void) {
/* останавливаем генерацию RFS */
f_bf_reg &= ~L502_REGBIT_IOHARD_OUT_RFS_EN_Msk;
fpga_reg_write(L502_REGS_IOHARD_OUTSWAP_BFCTL, f_bf_reg);
ssync();
ssync();
/* запрещаем прием по SPORT */
*pSPORT0_RCR1 &= ~RSPEN;
/* запрещаем DMA */
*pDMA3_CONFIG =0; //&= ~DMAEN;
*pSIC_IMASK0 &= ~IRQ_DMA3;
//ssync();
}
/** @brief Обработчик прерывания по SPORT0 на прием.
Прерывание возникает, когда был принят блок данных по SPORT0.
Обновляем указатель принятых данных и проверяем переполнение */
ISR(isr_sport_dma_rx) {
if (*pDMA3_IRQ_STATUS & DMA_DONE) {
uint32_t rdy_put_pos;
/* сбрасываем прерывание от DMA */
*pDMA3_IRQ_STATUS = DMA_DONE;
/* обновляем количество принятых данных на размер блока */
f_sport_in_put_pos += f_sport_in_block_size;
if (f_sport_in_put_pos == f_sport_in_buf_size)
f_sport_in_put_pos = 0;
/* смотрим, сколько свободно места в буфере на прием */
uint32_t get_pos = f_sport_in_get_pos;
rdy_put_pos = f_sport_in_put_pos > get_pos ?
f_sport_in_buf_size -f_sport_in_put_pos + get_pos :
get_pos - f_sport_in_put_pos;
f_recv_size += f_sport_in_block_size;
/* если осталось не больше блока - то считаем за переполнение,
т.к. тогда при следующем прерывании уже могут быть испорчены
принятые ранее данные */
if (rdy_put_pos < 2*f_sport_in_block_size) {
f_stream_in_set_overflow();
}
}
}
/** @} */
src/l502_stream.h
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/** @defgroup streams Управление потоками сбора данных */
/***************************************************************************//**
@addtogroup streams
@{
@file l502_stream.h
Файл содержит описания функций для работы с интерфейсом HostDMA
******************************************************************************/
#ifndef L502_STREAM_H_
#define L502_STREAM_H_
#include <stdint.h>
/** Состояние потока на ввод */
typedef enum {
IN_STREAM_STOP = 0, /**< Поток на ввод остановлен */
IN_STREAM_RUN = 2, /**< Поток на ввод в рабочем режиме */
IN_STREAM_OV_ALERT = 4, /**< Произошло переполнение - нужно сообщить о ошибке */
IN_STREAM_ERR= 3 /**< Поток остановлен из-за ошибки/переполнения */
} t_in_stream_state;
/** Состояние потока на вывод */
typedef enum {
OUT_STREAM_STOP = 0, /**< Поток на вывод остановлен */
OUT_STREAM_PRELOAD = 1, /**< Идет предзагрузка данных - данные принимаются
от ПК, но еще не запущен синхронных сбор/выдача */
OUT_STREAM_RUN = 2, /** Поток запущен на выдачу */
OUT_STREAM_ERR = 3, /** Поток остановлен по ошибке (сейчас не используется) */
OUT_STREAM_CYCLE = 4 /** Режим циклического буфера (сейчас не реализован) */
} t_out_stream_state;
/** Состояние потока на ввод */
extern t_in_stream_state g_stream_in_state;
/** Состояние потока на вывод */
extern t_out_stream_state g_stream_out_state;
/** Режим работы прошивки из #t_l502_bf_mode */
extern volatile int g_mode;
/** Флаги, обозначающие какие потоки разрешены */
extern int g_streams;
int32_t streams_start(void);
int32_t streams_stop(void);
int32_t stream_enable(uint32_t streams);
int32_t stream_disable(uint32_t streams);
int32_t stream_out_preload(void);
void stream_in_buf_free(uint32_t size);
void stream_out_buf_free(uint32_t size);
uint32_t sport_in_buffer_size(void);
int32_t sport_in_set_step_size(uint32_t size);
#endif
/** @} */
src/l502_tests.c
+421
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/** @file l502_test.c
Äàííûé ôàéë ñîäåðæèò ðåàëèçàöèþ òåñòîâ àïïàðàòóðû.
Ýòè òåñòû èñïîëüçóåòñÿ ïðè íàëàäêå ïðèáîðà è íå âûïîëíÿåòñÿ â øòàòíîì ðåæèìå ðàáîòû,
îäíàêî âêëþ÷åíèå èõ â ïðîøèâêó ïîçâîëÿåò âûïîëíÿòü ïðîâåðêó è ïîñëå ýòàïà íàëàäêè
(îäíàêî íå âî âðåìÿ ñáîðà äàííûõ è ò.ï.)
Äëÿ óïðàâëåíèÿ òåñòàìè ïðåäíàçíà÷åíà ñïåöèàëüíàÿ êîìàíäà îò PC ê BlackFin: L502_BF_CMD_CODE_TEST.
Ïàðàìåòð ýòîé êàîìàíäû îïðåäåëÿåò äåéñòâèå:
- çàïóñòèòü òåñò ñ çàäàííûì íîìåðîì
- îñòàíîâèòü òåêóùèé òåñò
- ïîëó÷èòü ðåçóëüòàòû âûïîëíÿåìîãî â äàííûõ ìîìåíò òåñòà èëè
ïîñëåäíåãî âûïîëíÿåìîãî òåñòà (åñëè òåñò îñòàíîâëåí).
Ïî êàêîãî-ëèáî òåñòà ìîäóëü ïåðåõîäèò â åòñòîâûé ðåæèì (èçìåíÿåòñÿ g_mode)
è âûïîëíÿåò ôóíêöèþ, ñîîòâåòñòâóþùóþ çàäàííîìó òåñòó (èç ýòîé ôóíêöèè òåñò
äîëæåí ïåðåîäè÷åñêè ïðîâåðÿòü ïðèõîä äðóãèõ êîìàíä îò PC).
Òåñò âûïîëíÿåòñÿ ëèáî äî îøèáêè, ëèáî äî ïðèõîäà êîìàíäû îñòàíîâà).
Óçíàòü ðåçóëüòàò òåñòà ìîæíî êîìàíäîé ñ ïàðàìåòðîì L502_BF_CMD_TEST_GET_RESULT.
Äîñòóïíû ñëåäóþùèå òåñòû:
- Ïðîâåðêà SDRAM
- Ïðîâåðêà SPI
- Ïðîâåðêà SPORT
**************************************************************************************************/
#include <stdlib.h>
#include <cdefBF523.h>
#include <sys/exception.h>
#include "l502_cmd.h"
#include "l502_fpga.h"
#include "l502_sport_tx.h"
#include <string.h>
extern int g_mode;
/* ìîäóëü ñ÷åò÷èêà, èñïîëüçóåìîãî äëÿ òåñòîâ SDRAM è SPORT */
#define L502_TEST_CNTR_MODULE 35317
/* ðàçìåð îäíîãî áàíêà SDRAM */
#define SDRAM_BANK_SIZE (4UL*1024*1024*2)
/* àäðåñà áàíêîâ SDRAM */
static volatile uint16_t* bank1 = NULL;
static volatile uint16_t* bank2 = (uint16_t*)(SDRAM_BANK_SIZE);
static volatile uint16_t* bank3 = (uint16_t*)(2*SDRAM_BANK_SIZE);
static volatile uint16_t* bank4 = (uint16_t*)(3*SDRAM_BANK_SIZE);
#define SPORT_TEST_START_ADDR 0xFF900000
#define SPORT_TEST_BUF_SIZE 4096
/* ðåçóëüòàò ïîñëåäíåãî òåñòà */
static t_l502_bf_test_res f_test_res;
/* íîìåð ïîñëåäíåãî âûïîëíÿåìîãî òåñòà */
static int32_t f_cur_test_ind = -1;
/* îáúÿâëåíèå ôóíêöèé çàïóñêà òåñòîâ */
static int f_sdram_test(void);
static int f_spi_test(void);
static int f_sport_test(void);
/* ñòðêóòóðà, îïèñûâàþùàÿ ñîîòâåòñòâèÿ êîäà òåñòà è ôóíêöèé òåñòà */
typedef struct {
uint32_t test_code;
int (*start)(void);
void (*get_result)(t_l502_bf_cmd *cmd);
} t_test_pars;
/* òåáëèöà ñîîòâåòñòâèé ôóíêöèé è êîäîâ òåñòîâ */
static t_test_pars f_test_pars[] = {
{ L502_BF_CMD_TEST_ECHO, NULL, NULL},
{ L502_BF_CMD_TEST_SPORT, f_sport_test, NULL},
{ L502_BF_CMD_TEST_SDRAM, f_sdram_test, NULL},
{ L502_BF_CMD_TEST_SPI, f_spi_test, NULL}
};
void l502_cmd_test(t_l502_bf_cmd *cmd) {
/* ïîëó÷åíèå ðåçóëüòàòà òåñòà */
if (cmd->param == L502_BF_CMD_TEST_GET_RESULT) {
/* åñëè íå áûëî íèêàêîãî òåñòà - âîçâðàùàåì îøèáêó */
if (f_cur_test_ind == -1) {
l502_cmd_done(L502_BF_ERR_INVALID_CMD_PARAMS, NULL, 0);
} else {
f_test_res.run = (g_mode == L502_BF_MODE_TEST) ? 1 : 0;
if (f_test_pars[f_cur_test_ind].get_result != NULL) {
/* åñëè åñòü ó òåñòà ñïåö ôóíêöèÿ äëÿ ïîëó÷åíèÿ ðåçóëüòàòà =>
âûçûâàåì åå */
f_test_pars[f_cur_test_ind].get_result(cmd);
} else {
/* èíà÷å ïðîñòî óñòàíàâëèâàåì ðåçóëüàòàò áåç äàííûõ */
l502_cmd_done(0, (uint32_t*)&f_test_res,
sizeof(t_l502_bf_test_res)/sizeof(uint32_t));
}
}
} else if (cmd->param == L502_BF_CMD_TEST_STOP) {
/* îñòàíîâ òåñòà => åñëè òåñò çàïóùåí - âîçâðàùàåì åãî ðåçóëüòàò,
èíà÷å âîçâðàùàåì îøèáêó ÷òî è òàê òåñòà íåòó */
if (g_mode == L502_BF_MODE_TEST) {
g_mode = L502_BF_MODE_IDLE;
l502_cmd_done(0, NULL, 0);
} else {
l502_cmd_done(L502_BF_ERR_NO_TEST_IN_PROGR, NULL, 0);
}
} else {
/* çàïóñê òåñòà - ïðîõîäèì ïî òàáëèöå è èùåì íóæíûé òåñò */
if (g_mode == L502_BF_MODE_IDLE) {
uint32_t i;
for (i=0, f_cur_test_ind=-1; (i<sizeof(f_test_pars)/sizeof(f_test_pars[0])) &&
(f_cur_test_ind==-1); i++) {
if (f_test_pars[i].test_code == cmd->param) {
f_cur_test_ind = i;
memset(&f_test_res, 0, sizeof(f_test_res));
f_test_res.test = cmd->param;
l502_cmd_done(0, 0, NULL);
if (f_test_pars[i].start != NULL) {
g_mode = L502_BF_MODE_TEST;
f_test_pars[i].start();
g_mode = L502_BF_MODE_IDLE;
}
}
}
if (f_cur_test_ind == -1)
l502_cmd_done(L502_BF_ERR_INVALID_CMD_PARAMS, NULL, 0);
}
else
{
l502_cmd_done(L502_BF_ERR_STREAM_RUNNING, NULL, 0);
}
}
}
#define SPORT_CNTR_INC 0x1
#define TEST_CHECK_OUT(label) \
do { \
l502_cmd_check_req(); \
if ((g_mode!= L502_BF_MODE_TEST) || f_test_res.err) \
goto label; \
} while (0);
/* òåñòèðîâàíèå SPORT'à, ñëóæàùåãî äëÿ ïåðåäà÷è ïîòîêîâ ÀÖÏ/ÖÀÏ
îò BlackFin'à ê ÏËÈÑ. Óñòàíàâëèâàåòñÿ öèêëè÷åñêèé ñêâîçíîé ðåæèì ïîòîêà
è ïåðåäàåòñÿ ñ÷åò÷èê, êîòîðûé ïðîâåðÿåòñÿ ïðè ïðèåìå */
static int f_sport_test(void) {
#define RX_BUF_SIZE 2048
static uint16_t rx_buf[RX_BUF_SIZE];
uint16_t stat=*pSPORT0_STAT;
uint16_t rx_cntr=0, tx_cntr=0;
uint16_t rx_val;
int err = 0, i;
/* ðàçðåøàåì ïðèåì è ïåðåäà÷ó ïî SPORT'ó */
*pSPORT0_TCR1 |= TSPEN;
*pSPORT0_RCR1 |= RSPEN;
while (stat & RXNE) {
rx_buf[0] = *pSPORT0_RX16;
stat=*pSPORT0_STAT;
}
/* âíà÷àëå ïîëíîñòüþ çàïîëíÿåì î÷åðåäü SPORT'à */
for (i = 0; i < 8; i++) {
*pSPORT0_TX16 = tx_cntr++;
//tx_cntr+=SPORT_CNTR_INC;
}
/* óñòàíàâëèâàåì â ÏËÈÑ ñêâîçíîé ðåæèì ðàáîòû SPORT */
fpga_reg_write(L502_REGS_IOHARD_OUTSWAP_BFCTL, 0xE);
while (!f_test_res.err) {// && (g_mode==L502_BF_MODE_TEST))
stat = *pSPORT0_STAT;
if (!(stat & TXF)) {
*pSPORT0_TX16 = tx_cntr++;
}
if (stat & RXNE) {
rx_val = *pSPORT0_RX16;
if ((rx_val != rx_cntr)) {
f_test_res.err = L502_BF_ERR_TEST_VALUE;
f_test_res.last_rd = rx_val;
f_test_res.last_wr = rx_cntr;
err = rx_val - rx_cntr;
}
if (!(rx_cntr & 0xFFFF)) {
TEST_CHECK_OUT(sport_test_end);
if (!rx_cntr)
f_test_res.cntr++;
}
rx_cntr++;
}
}
sport_test_end:
/* çàïðåùàåì ïðèåì è ïåðåäà÷ó ïî SPORT'ó */
*pSPORT0_TCR1 = 0;
*pSPORT0_RCR1 = 0;
/* âîçâðàùàåì øòàòíûé ðåæèì ðàáîòû SPORT'à */
fpga_reg_write(L502_REGS_IOHARD_OUTSWAP_BFCTL, 0);
return err;
}
/* òåñò SPI - çàïèñûâàåì áåãóùóþ åäèíèöó â ðåãèñòð ÏËÈÑ, ñ÷èòûâàåì
çíà÷åíèå ýòîãî ðåãèñòðà è ñâåðÿåì ðåçóëüòàòû */
static int f_spi_test(void) {
f_test_res.last_addr = L502_REGS_IOHARD_ADC_FRAME_DELAY;
while (!f_test_res.err && (g_mode==L502_BF_MODE_TEST)) {
int i;
for (i = 0; (i < 32) && !f_test_res.err; i++) {
f_test_res.last_wr = (1<<i);
fpga_reg_write(f_test_res.last_addr, f_test_res.last_wr);
f_test_res.last_rd = fpga_reg_read(f_test_res.last_addr);
if (f_test_res.last_wr != f_test_res.last_rd)
f_test_res.err = L502_BF_ERR_TEST_VALUE;
}
if (!f_test_res.err)
f_test_res.cntr++;
l502_cmd_check_req();
}
return f_test_res.err;
}
/* òåñò SDRAM ïàìÿòè */
static int f_sdram_test(void) {
int i;
unsigned short cntr = 0;
while (!f_test_res.err && (g_mode == L502_BF_MODE_TEST)) {
f_test_res.stage = 0;
/* çàïîëíÿåì âñþ ïàìÿòü ñ÷åò÷èêîì */
for (i = 0, cntr = 0; i < (16UL*1024*1024); i++) {
bank1[i] = cntr;
if (++cntr == L502_TEST_CNTR_MODULE) {
cntr = 0;
TEST_CHECK_OUT(sdram_test_end);
}
}
TEST_CHECK_OUT(sdram_test_end);
/* ÷èòàåì ïîñëåäîâàòåëüíî è ñâåðÿåì ðåçóëüòàò */
for (i = 0, cntr = 0; i < (16UL*1024*1024); i++) {
uint16_t word = bank1[i];
if (word != cntr) {
f_test_res.err = L502_BF_ERR_TEST_VALUE;
f_test_res.last_addr = (uint32_t)&bank1[i];
f_test_res.last_wr = cntr;
f_test_res.last_rd = word;
break;
}
if (++cntr==L502_TEST_CNTR_MODULE) {
cntr = 0;
TEST_CHECK_OUT(sdram_test_end);
}
}
TEST_CHECK_OUT(sdram_test_end);
f_test_res.stage++;
/* çàïèñûâàåì ïî ñëîâó â êàæäûé áàíê äëÿ ïðîâåðêè ïåðåêðåñòíîé
çàïèñè ïî ðàçíûì áàíêàì */
for (i = 0, cntr = 0; i < (4UL*1024*1024); i++) {
bank1[i] = cntr;
bank2[i] = ~cntr;
bank3[i] = cntr^0xAA55;
bank4[i] = cntr^0x55AA;
if (++cntr == L502_TEST_CNTR_MODULE) {
cntr = 0;
TEST_CHECK_OUT(sdram_test_end);
}
}
TEST_CHECK_OUT(sdram_test_end);
for (i = 0, cntr = 0; i < (4UL*1024*1024); i++) {
uint16_t word = bank1[i];
if (word != cntr) {
f_test_res.err = L502_BF_ERR_TEST_VALUE;
f_test_res.last_addr = (uint32_t)&bank1[i];
f_test_res.last_wr = cntr;
f_test_res.last_rd = word;
break;
}
word = bank2[i];
if (word != (~cntr & 0xFFFF)) {
f_test_res.err = L502_BF_ERR_TEST_VALUE;
f_test_res.last_addr = (uint32_t)&bank2[i];
f_test_res.last_wr = (~cntr & 0xFFFF);
f_test_res.last_rd = word;
break;
}
word = bank3[i];
if (word != ((cntr^0xAA55) & 0xFFFF)) {
f_test_res.err = L502_BF_ERR_TEST_VALUE;
f_test_res.last_addr = (uint32_t)&bank3[i];
f_test_res.last_wr = ((cntr^0xAA55) & 0xFFFF);
f_test_res.last_rd = word;
break;
}
word = bank4[i];
if (word != ((cntr^0x55AA) & 0xFFFF)) {
f_test_res.err = L502_BF_ERR_TEST_VALUE;
f_test_res.last_addr = (uint32_t)&bank4[i];
f_test_res.last_wr = ((cntr^0x55AA) & 0xFFFF);
f_test_res.last_rd = word;
break;
}
if (++cntr == L502_TEST_CNTR_MODULE) {
cntr = 0;
TEST_CHECK_OUT(sdram_test_end);
}
}
TEST_CHECK_OUT(sdram_test_end);
/* çàïèñü â 4 ðàçíûõ áàíêà ñ ïîñëåäóþùèì ÷òåíèåì */
f_test_res.stage++;
for (i = 0, cntr=0; i < (4UL*1024*1024); i++) {
uint16_t word[4], wr_val[4] = {~cntr, cntr, cntr^0x55AA, cntr^0xAA55};
bank1[i] = wr_val[0];
bank2[i] = wr_val[1];
bank3[i] = wr_val[2];
bank4[i] = wr_val[3];
word[1] = bank2[i];
word[0] = bank1[i];
word[3] = bank4[i];
word[2] = bank3[i];
if (word[0] != wr_val[0]) {
f_test_res.err = L502_BF_ERR_TEST_VALUE;
f_test_res.last_addr = (uint32_t)&bank1[i];
f_test_res.last_wr = wr_val[0];
f_test_res.last_rd = word[0];
break;
}
if (word[1] != wr_val[1]) {
f_test_res.err = L502_BF_ERR_TEST_VALUE;
f_test_res.last_addr = (uint32_t)&bank2[i];
f_test_res.last_wr = wr_val[1];
f_test_res.last_rd = word[1];
break;
}
if (word[2] != wr_val[2]) {
f_test_res.err = L502_BF_ERR_TEST_VALUE;
f_test_res.last_addr = (uint32_t)&bank3[i];
f_test_res.last_wr = wr_val[2];
f_test_res.last_rd = word[2];
break;
}
if (word[3] != wr_val[3]) {
f_test_res.err = L502_BF_ERR_TEST_VALUE;
f_test_res.last_addr = (uint32_t)&bank4[i];
f_test_res.last_wr = wr_val[3];
f_test_res.last_rd = word[3];
break;
}
if (++cntr == L502_TEST_CNTR_MODULE) {
cntr = 0;
TEST_CHECK_OUT(sdram_test_end);
}
}
TEST_CHECK_OUT(sdram_test_end);
f_test_res.cntr++;
}
sdram_test_end:
return f_test_res.err;
}
src/l502_user_process.c
+162
View File
@@ -0,0 +1,162 @@
/***************************************************************************//**
@addtogroup user_process
@{
@file l502_user_process.c
Файл содержит простейший вариант реализации пользовательских функций, в котором
потоки данных передаются без изменения и никакие пользовательские команды не
обрабатываются. Пользователь может изменить этот файл и добавить здесь свою
обработку.
*******************************************************************************/
#include "l502_stream.h"
#include "l502_hdma.h"
#include "l502_sport_tx.h"
#include "l502_cmd.h"
#include <stdlib.h>
/***************************************************************************//**
@brief Обработка принятого массива данных АЦП/DIN.
Функция вызывается каждый раз, когда обнаружены новые данные от
АЦП/цифровых входов, пришедшие по SPORT0.
Функция должна обработать данные и вернуть количество обработанных данных,
однако эти данные все еще считаются использованными (не могут быть переписаны
новыми пришедшими данными) до тех пор пока не будет вызвана функция
stream_in_buf_free()).
Если функция вернет значение меньше чем size, то функция будут вызванна при
следующем проходе еще раз с указателем на необработанные данные.
В текущей реализации просто запускается передача данных по HDMA в ПК
@param[in] data Указатель на массив с принятыми данными
@param[in] size Количество принятых данных в 32-битных словах
@return Функция возвращает количество обработанных данных (от 0 до size).
На эти данные не будет вызываться повторно usr_in_proc_data(),
но они считаются еще используемыми
*******************************************************************************/
uint32_t usr_in_proc_data(uint32_t* data, uint32_t size) {
/* если есть свободные дескрипторы на передачу по HDMA - ставим блок на
передачу. Иначе возвращаем 0, чтобы на обработку этих данных функцию
вызвали бы позже */
if (hdma_send_req_rdy()) {
hdma_send_req_start(data, size, 0);
return size;
}
return 0;
}
/***************************************************************************//**
@brief Обработка принятого массива с данными ЦАП/DOUT
Функция вызывается каждый раз, когда обнаружены новые данные, принятые от
ПК по HDMA.
Функция должна обработать данные и вернуть количество обработанных данных,
однако эти данные все еще считаются использованными (не могут быть переписаны
новыми пришедшими данными) до тех пор пока не будет вызвана функция
stream_out_buf_free()).
Если функция вернет значение меньше чем size, то функция будут
вызвана после еще раз с указателем на необработанные данные.
В текущей реализации просто запускается передача данных по SPORT
для вывода на ЦАП/цифровые выходы.
@param[in] data Указатель на массив с принятыми данными
@param[in] size Количество принятых данных в 32-битных словах
@return Функция возвращает количество обработанных данных (от 0 до size).
На эти данные не будет вызываться повторно usr_out_proc_data(),
но они считаются еще используемыми
******************************************************************************/
uint32_t usr_out_proc_data(uint32_t* data, uint32_t size) {
/* если есть свободные дескрипторы на передачу по HDMA - ставим блок на
передачу. Иначе возвращаем 0, чтобы на обработку этих данных функцию
вызвали бы позже */
if (sport_tx_req_rdy()) {
/* за один раз можем передать в SPORT не более
SPORT_TX_REQ_SIZE_MAX слов */
if (size > SPORT_TX_REQ_SIZE_MAX)
size = SPORT_TX_REQ_SIZE_MAX;
sport_tx_start_req(data, size);
return size;
}
return 0;
}
/****************************************************************************//**
@brief Обработка завершения передачи по HostDMA
Функция вызывается из обработчика прерывания, когда завершилась передача
блока данных по HDMA в ПК, поставленного до этого на передачу с
помощью hdma_send_req_start().
@param[in] addr Адрес слова, сразу за последним переданным словом
@param[in] size Размер переданных данных в 32-битных словах
****************************************************************************/
void hdma_send_done(uint32_t* addr, uint32_t size) {
stream_in_buf_free(size);
}
/***************************************************************************//**
@brief Обработка завершения передачи по SPORT
Функция вызывается из обработчика прерывания при завершении передачи блока данных
по SPORT'у на цифровые выходы/ЦАП, поставленного до этого на передачу с
помощью sport_tx_start_req().
@param[in] addr Адрес слова, сразу за последним переданным словом
@param[in] size Размер переданных данных в 32-битных словах */
void sport_tx_done(uint32_t* addr, uint32_t size) {
stream_out_buf_free(size);
}
/****************************************************************************//**
@brief Обработка пользовательских команд.
Функция вызывается при приеме команды от ПК с кодом большим или равным
#L502_BF_CMD_CODE_USER.
По завершению обработки необходимо обязательно вызвать
l502_cmd_done(), указав код завершения команды и
при необходимости передать данные с результатом
@param[in] cmd Структура с описанием принятой команды
******************************************************************************/
void usr_cmd_process(t_l502_bf_cmd *cmd) {
l502_cmd_done(L502_BF_ERR_UNSUP_CMD, NULL, 0);
}
/** @} */
src/l502_user_process.h
+26
View File
@@ -0,0 +1,26 @@
/** @defgroup user_process Пользовательская обработка данных */
/***************************************************************************//**
@addtogroup user_process
@{
@file l502_user_process.h
Файл содержит описания функций, которые предназначены для изменения
пользователем для написания своих алгоритмов обработки данных и реализации
пользовательских команд.
******************************************************************************/
#ifndef L502_USER_PROCESS_H_
#define L502_USER_PROCESS_H_
uint32_t usr_in_proc_data(uint32_t* data, uint32_t size);
uint32_t usr_out_proc_data(uint32_t* data, uint32_t size);
void usr_cmd_process(t_l502_bf_cmd *cmd);
#endif
/** @} */
src/main.c
+30
View File
@@ -0,0 +1,30 @@
/*****************************************************************************
* NewProject.c
*****************************************************************************/
#include "l502_cdefs.h"
void l502_init(void);
#include "l502_global.h"
#include "l502_cmd.h"
void stream_proc(void);
/* g_state îïèñûâàåò îáëàñòü ïàìÿòè, ðàñïîëîæåííóþ ïî ôèêñèðîâàííûì àäðåñàì.
* Äëÿ ðàñïîëîæåíèÿ â íà÷àëî áàíêà A äàííûõ èñïîëüçóåì ñïåöèàëüíóþ ñåêöèþ */
SECTION("board_state", volatile t_l502_board_state g_state);
int main(void) {
/* Èíèöèàëèçàöèÿ èíòåðôåéñîâ */
l502_init();
for (;;) {
/* ïðîâåðÿåì íàëè÷èå êîìàíäû îò ÏÊ è íà÷èíàÿåì
îáðàáîòêó, åñëè îíà åñòü */
l502_cmd_check_req();
/* îáðàáîòêà ïîòîêîâ äàííûõ */
stream_proc();
}
return 0;
}
vdsp/l502-bf.dpj
+433
View File
@@ -0,0 +1,433 @@
<?xml version="1.0" encoding='ISO-8859-1'?>
<visualdsp-project schema="17" name="l502-bf" file="l502-bf.dpj" version="1">
<!-- Project build target -->
<target>
<processor revision="0.2">ADSP-BF523</processor>
<extension>.ldr</extension>
<type>Loader file</type>
</target>
<!-- Configurations -->
<configurations active="Release">
<configuration name="Debug">
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
<changed-property-page-flags>4</changed-property-page-flags>
<tools>
<tool type="Compiler">
<option><![CDATA[|-Version>5.0|-O>0|-O1>0|-Ov>100|-ipa>0|-g>1|-no-annotate>0|-save-temps -path-output>0|-ED>0|-no-auto-attrs>0|-no-builtin>0|-no-extra-keywords>0|-enum-is-int>0|-no-fp-associative>0|-structs-do-not-overlap>1|-implicit-pointers>0|-eh >0|-rtti>0|-check-init-order>0|-ignore-std>1|-const-read-write>0|-const-strings>0|-no-multiline>1|-misra>0|-misra-strict>0|-misra-no-cross-module>0|-misra-no-runtime>0|-misra-testing>0|-misra-suppress-advisory>0|-no-std-inc>0|-double-size-64>1|-double-size-any>0|-Ofp>0|-guard-vol-loads>0|-decls-strong>1|-no-saturation>0|-cplbs>1|-sdram>0|-multicore>0|-stack-detect>0|-pguide>0|NOSWITCH>0|-flags-compiler --diag_warning,implicit_func_decl>1|-warn-protos>1|-flags-compiler --diag_warning,call_not_inlined>1|-Wremarks>0|-w>0]]></option>
</tool>
<tool type="Assembler">
<option><![CDATA[|-Version>4.5|-v>0|-g>1|-l>0|-save-temps>0|-sp>0]]></option>
</tool>
<tool type="Linker">
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</tool>
<tool type="Archiver">
<option><![CDATA[]]></option>
</tool>
<tool type="Loader">
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</tool>
<tool type="VdkGen">
<option><![CDATA[]]></option>
</tool>
</tools>
</configuration>
<configuration name="Release">
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
<changed-property-page-flags>0</changed-property-page-flags>
<tools>
<tool type="Compiler">
<option><![CDATA[|-Version>5.0|-O>1|-O1>1|-Ov>100|-ipa>0|-g>0|-no-annotate>0|-save-temps -path-output>0|-ED>0|-no-auto-attrs>0|-no-builtin>0|-no-extra-keywords>0|-enum-is-int>0|-no-fp-associative>0|-structs-do-not-overlap>1|-implicit-pointers>0|-eh >0|-rtti>0|-check-init-order>0|-ignore-std>0|-const-read-write>0|-const-strings>0|-no-multiline>1|-misra>0|-misra-strict>0|-misra-no-cross-module>0|-misra-no-runtime>0|-misra-testing>0|-misra-suppress-advisory>0|-no-std-inc>0|-double-size-32>1|-double-size-any>0|-Ofp>0|-guard-vol-loads>0|-decls-strong>1|-no-saturation>0|-cplbs>0|-sdram>0|-multicore>0|-stack-detect>0|-pguide>0|NOSWITCH>0|-flags-compiler --diag_warning,implicit_func_decl>0|-warn-protos>1|-flags-compiler --diag_warning,call_not_inlined>0|-Wremarks>0|-w>0]]></option>
</tool>
<tool type="Assembler">
<option><![CDATA[|-Version>4.5|-v>0|-g>0|-l>0|-save-temps>0|-sp>0]]></option>
</tool>
<tool type="Linker">
<option><![CDATA[|-Version>5.0|-flags-link -t>0|-flags-link -S>0|-flags-link -s>0|-mem>0|-flags-link -warnonce>0|-map>0|-flags-link -xref>0|-flags-link -save-temps>0|-flags-link -ip>1|-MD>USER_CRT="l502-bf_basiccrt.doj",USE_CACHE,USE_INSTRUCTION_CACHE|-flags-link -e>1|-flags-link -ev>0|-add-debug-libpaths>0|-flags-link -MD__ADI_LIBEH__>0|-multicore>0|-flags-link -MDUSE_CACHE>1|NOSWITCH>1]]></option>
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<option><![CDATA[]]></option>
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</tool>
<tool type="VdkGen">
<option><![CDATA[]]></option>
</tool>
</tools>
</configuration>
</configurations>
<!-- Project folders -->
<folders>
<folder name="Generated Files">
<folders>
<folder name="Startup">
<files>
<file name=".\l502-bf_basiccrt.s">
<file-configurations>
<file-configuration name="Debug">
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<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
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<intermediate-dir>.\Release</intermediate-dir>
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</file-configurations>
</file>
</files>
</folder>
<folder name="User Heap">
<files>
<file name=".\l502-bf_heaptab.c">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
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</file-configuration>
</file-configurations>
</file>
</files>
</folder>
</folders>
</folder>
<folder name="Header Files" ext=".h,.hpp,.hxx">
<files>
<file name="..\src\l502_async.h">
</file>
<file name="..\src\l502_bf_cmd_defs.h">
</file>
<file name="..\src\l502_cdefs.h">
</file>
<file name="..\src\l502_cmd.h">
</file>
<file name="..\src\l502_defs.h">
</file>
<file name="..\src\l502_fpga.h">
</file>
<file name="..\src\l502_fpga_regs.h">
</file>
<file name="..\src\l502_global.h">
</file>
<file name="..\src\l502_hdma.h">
</file>
<file name="..\src\l502_params.h">
</file>
<file name="..\src\l502_sport_tx.h">
</file>
<file name="..\src\l502_stream.h">
</file>
<file name="..\src\l502_user_process.h">
</file>
</files>
</folder>
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</folder>
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<files>
<file name="..\src\l502_async.c">
<file-configurations>
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<file-configuration name="Release">
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<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
<file name="..\src\l502_cmd.c">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
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</file-configuration>
</file-configurations>
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<file name="..\src\l502_fpga.c">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
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<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
<file name="..\src\l502_hdma.c">
<file-configurations>
<file-configuration name="Debug">
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</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
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<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
<file name="..\src\l502_init.c">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
<file name="..\src\l502_params.c">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
<file name="..\src\l502_sport_tx.c">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
<file name="..\src\l502_stream.c">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
<file name="..\src\l502_tests.c">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
<file name="..\src\l502_user_process.c">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
<file name="..\src\main.c">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
</files>
</folder>
</folders>
<!-- System Builder Components -->
<system-builder-component-tables>
<system-builder-plugin name="">
<system-builder-component name="Select Processor">
<property name="Processor family"><![CDATA[Blackfin]]></property>
</system-builder-component>
</system-builder-plugin>
<system-builder-plugin name="Startup Code Wizard" version="2.0">
<system-builder-component name="Advanced Options">
<property name="Add own event handlers"><![CDATA[True]]></property>
<property name="Include C++ support"><![CDATA[False]]></property>
<property name="Include C/C++ support"><![CDATA[True]]></property>
<property name="Include LDF exceptions support"><![CDATA[False]]></property>
<property name="Main never returns"><![CDATA[True]]></property>
<property name="Search for libraries in the tools installation directory"><![CDATA[True]]></property>
<property name="Using Argv"><![CDATA[False]]></property>
</system-builder-component>
<system-builder-component name="Cache and Memory Protection">
<property name="DCBS"><![CDATA[Unset]]></property>
<property name="Data cache memory configuration"><![CDATA[RAM with no memory protection]]></property>
<property name="Generate support for memory protection"><![CDATA[False]]></property>
<property name="Instruction cache memory configuration"><![CDATA[Instruction cache]]></property>
<property name="Write-back cache"><![CDATA[False]]></property>
<property name="Write-through cache"><![CDATA[False]]></property>
</system-builder-component>
<system-builder-component name="Compiler Instrumented Profiling">
<property name="Enable profiling"><![CDATA[False]]></property>
<property name="Profiling output"><![CDATA[mon.out]]></property>
</system-builder-component>
<system-builder-component name="Configuration">
<property name="Add LDF"><![CDATA[True]]></property>
<property name="Add startup code"><![CDATA[True]]></property>
<property name="LDF template schema"><![CDATA[5.4]]></property>
<property name="Startup code template schema"><![CDATA[3.8]]></property>
</system-builder-component>
<system-builder-component name="Custom system heap settings">
<property name="Absolute size"><![CDATA[]]></property>
<property name="Customize system heap"><![CDATA[True]]></property>
<property name="Memory types"><![CDATA[L1]]></property>
<property name="Minimum size"><![CDATA[7 kB]]></property>
</system-builder-component>
<system-builder-component name="Custom system stack settings">
<property name="Absolute size"><![CDATA[]]></property>
<property name="Customize system stack"><![CDATA[True]]></property>
<property name="Memory types"><![CDATA[L1]]></property>
<property name="Minimum size"><![CDATA[2 kB]]></property>
</system-builder-component>
<system-builder-component name="External memory settings">
<property name="Partition external memory"><![CDATA[None]]></property>
<property name="Size"><![CDATA[32MB]]></property>
<property name="Using external memory"><![CDATA[True]]></property>
</system-builder-component>
<system-builder-component name="Linker Options">
<property name="Search Directory"><![CDATA[]]></property>
</system-builder-component>
<system-builder-component name="Multi-core Selection">
<property name="Core"><![CDATA[Core A]]></property>
</system-builder-component>
<system-builder-component name="PGO">
<property name="Using PGO"><![CDATA[False]]></property>
</system-builder-component>
<system-builder-component name="Processor clock and power settings">
<property name="Clock and power settings"><![CDATA[Optimize for speed]]></property>
<property name="Configure clock and power settings"><![CDATA[False]]></property>
<property name="EZ-KIT"><![CDATA[ADSP-BF537 EZ-KIT]]></property>
</system-builder-component>
<system-builder-component name="Program Running From">
<property name="Internal Memory"><![CDATA[True]]></property>
</system-builder-component>
<system-builder-component name="Project Options">
<property name="Compiler Multicore"><![CDATA[False]]></property>
<property name="Configuration"><![CDATA[Release]]></property>
<property name="Full IO"><![CDATA[False]]></property>
<property name="Intermediate Directory"><![CDATA[.\Release]]></property>
<property name="Link against MT libraries"><![CDATA[False]]></property>
<property name="Linker Multicore"><![CDATA[False]]></property>
<property name="Name"><![CDATA[l502-bf]]></property>
<property name="Processor"><![CDATA[ADSP-BF523]]></property>
<property name="Silicon Revision"><![CDATA[0.2]]></property>
<property name="Strict IEEE Floating Point Compliance"><![CDATA[False]]></property>
<property name="Use C++ exceptions libraries"><![CDATA[False]]></property>
<property name="Utility ROM"><![CDATA[True]]></property>
</system-builder-component>
<system-builder-component name="Run-time Initialization">
<property name="I/O device initialization"><![CDATA[False]]></property>
<property name="Initialize data registers"><![CDATA[False]]></property>
<property name="Initialize return registers to zero"><![CDATA[False]]></property>
<property name="Run-time memory initialization"><![CDATA[False]]></property>
</system-builder-component>
<system-builder-component name="Welcome">
<property name="Enabled"><![CDATA[True]]></property>
</system-builder-component>
</system-builder-plugin>
</system-builder-component-tables>
</visualdsp-project>
vdsp/l502-bf.ldf
+497
View File
@@ -0,0 +1,497 @@
/* MANAGED-BY-SYSTEM-BUILDER */
/* VisualDSP++ 5.0 Update 10.1 */
/* LDF Printer version: 5.9.0.1 */
/* ldfgen.exe version: 5.9.0.1 */
/* VDSG version: 5.9.0.1 */
/*
** ADSP-BF523 linker description file generated on Jan 10, 2013 at 19:23:18.
**
** Copyright (C) 2000-2010 Analog Devices Inc., All Rights Reserved.
**
** This file is generated automatically based upon the options selected
** in the LDF Wizard. Changes to the LDF configuration should be made by
** changing the appropriate options rather than editing this file.
**
** Configuration:-
** crt_doj: l502-bf_basiccrt.doj
** processor: ADSP-BF523
** product_name: VisualDSP++ 5.0 Update 10.1
** si_revision: 0.2
** default_silicon_revision_from_archdef: 0.2
** cplb_init_cplb_ctrl: (
** CPLB_ENABLE_ICACHE
** CPLB_ENABLE_ICPLBS
** )
** using_cplusplus: false
** mem_init: false
** use_vdk: false
** use_mt: false
** use_eh: false
** use_argv: false
** running_from_internal_memory: true
** user_heap_src_file: C:\PRJ\L502\builds\lpcie_sdk\release\firmware-conv\l502-bf\vdsp\l502-bf_heaptab.c
** libraries_use_stdlib: true
** libraries_use_fileio_libs: false
** libraries_use_ieeefp_emulation_libs: false
** libraries_use_eh_enabled_libs: false
** libraries_use_fixed_point_io_libs: false
** libraries_use_utility_rom: true
** detect_stackoverflow: false
** system_heap: L1
** system_heap_min_size: 7k
** system_stack: L1
** system_stack_min_size: 2k
** use_sdram: true
** use_sdram_size: 32MB
** use_sdram_partitioned: none
**
*/
ARCHITECTURE(ADSP-BF523)
SEARCH_DIR($ADI_DSP/Blackfin/lib)
// Workarounds are enabled, exceptions are disabled.
#define RT_LIB_NAME(x) lib ## x ## y.dlb
#define RT_LIB_NAME_EH(x) lib ## x ## y.dlb
#define RT_LIB_NAME_MT(x) lib ## x ## y.dlb
#define RT_LIB_NAME_EH_MT(x) lib ## x ## y.dlb
#define RT_OBJ_NAME(x) x ## y.doj
#define RT_OBJ_NAME_MT(x) x ## mty.doj
$LIBRARIES =
/*$VDSG<insert-user-libraries-at-beginning> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-libraries-at-beginning> */
RT_LIB_NAME_MT(small532)
,RT_LIB_NAME_MT(io532)
,RT_LIB_NAME_MT(c532)
,RT_LIB_NAME_MT(event532)
,RT_LIB_NAME(ssl527)
,RT_LIB_NAME(drv527)
,RT_LIB_NAME(usb527)
,RT_LIB_NAME(f64ieee532)
,RT_LIB_NAME(dsp532)
,RT_LIB_NAME(sftflt532)
,RT_LIB_NAME(etsi532)
,RT_LIB_NAME(ftl527)
,RT_OBJ_NAME_MT(idle532)
,RT_LIB_NAME_MT(rt_fileio532)
/*$VDSG<insert-user-libraries-at-end> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-libraries-at-end> */
;
$OBJECTS =
"l502-bf_basiccrt.doj"
/*$VDSG<insert-user-objects-at-beginning> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-objects-at-beginning> */
, RT_LIB_NAME(profile532)
, $COMMAND_LINE_OBJECTS
, "cplbtab523.doj"
/*$VDSG<insert-user-objects-at-end> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-objects-at-end> */
;
$OBJS_LIBS_INTERNAL =
/*$VDSG<insert-libraries-internal> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-internal> */
$OBJECTS{prefersMem("internal")}, $LIBRARIES{prefersMem("internal")}
/*$VDSG<insert-libraries-internal-end> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-internal-end> */
;
$OBJS_LIBS_NOT_EXTERNAL =
/*$VDSG<insert-libraries-not-external> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-not-external> */
$OBJECTS{!prefersMem("external")}, $LIBRARIES{!prefersMem("external")}
/*$VDSG<insert-libraries-not-external-end> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-not-external-end> */
;
/*$VDSG<insert-user-macros> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-macros> */
/*$VDSG<customize-async-macros> */
/* This code is preserved if the LDF is re-generated. */
#define ASYNC0_MEMTYPE RAM
#define ASYNC1_MEMTYPE RAM
#define ASYNC2_MEMTYPE RAM
#define ASYNC3_MEMTYPE RAM
/*$VDSG<customize-async-macros> */
MEMORY
{
/*
** ADSP-BF523 MEMORY MAP.
**
** The known memory spaces are as follows:
**
** 0xFFE00000 - 0xFFFFFFFF Core MMR registers (2MB)
** 0xFFC00000 - 0xFFDFFFFF System MMR registers (2MB)
** 0xFFB01000 - 0xFFBFFFFF Reserved
** 0xFFB00000 - 0xFFB00FFF Scratch SRAM (4K)
** 0xFFA14000 - 0xFFAFFFFF Reserved
** 0xFFA10000 - 0XFFA13FFF Code SRAM/CACHE (16K)
** 0xFFA0C000 - 0xFFA0FFFF Reserved
** 0xFFA08000 - 0xFFA0BFFF Instruction Bank B SRAM (16K)
** 0xFFA00000 - 0xFFA07FFF Instruction Bank A SRAM (32K)
** 0xFF908000 - 0xFF9FFFFF Reserved
** 0xFF904000 - 0xFF907FFF Data Bank B SRAM/CACHE (16K)
** 0xFF900000 - 0XFF903FFF Data Bank B SRAM (16K)
** 0xFF808000 - 0xFF8FFFFF Reserved
** 0xFF804000 - 0xFF807FFF Data Bank A SRAM/CACHE (16K)
** 0xFF800000 - 0XFF803FFF Data Bank A SRAM (16K)
** 0xEF000800 - 0xFF800000 Reserved
** 0xEF000000 - 0xFF8007FF Boot ROM (2K)
** 0x20400000 - 0xEEFFFFFF Reserved
** 0x20300000 - 0x203FFFFF ASYNC MEMORY BANK 3 (1MB)
** 0x20200000 - 0x202FFFFF ASYNC MEMORY BANK 2 (1MB)
** 0x20100000 - 0x201FFFFF ASYNC MEMORY BANK 1 (1MB)
** 0x20000000 - 0x200FFFFF ASYNC MEMORY BANK 0 (1MB)
** 0x00000000 - 0x07FFFFFF SDRAM MEMORY (16MB - 128MB)
**
** Notes:
** 0xFF807FEF-0xFF807FFF
** Required by boot-loader. Used as heap or cache below which is ok. Cannot
** contain initialized data or code.
*/
MEM_L1_SCRATCH { TYPE(RAM) START(0xFFB00000) END(0xFFB00FFF) WIDTH(8) }
MEM_L1_CODE_CACHE { TYPE(RAM) START(0xFFA10000) END(0xFFA13FFF) WIDTH(8) }
MEM_L1_CODE { TYPE(RAM) START(0xFFA00000) END(0xFFA0BFFF) WIDTH(8) }
MEM_L1_DATA_B { TYPE(RAM) START(0xFF900000) END(0xFF907FFF) WIDTH(8) }
MEM_L1_DATA_A { TYPE(RAM) START(0xFF800000) END(0xFF807FFF) WIDTH(8) }
MEM_ASYNC3 { TYPE(ASYNC3_MEMTYPE) START(0x20300000) END(0x203FFFFF) WIDTH(8) }
MEM_ASYNC2 { TYPE(ASYNC2_MEMTYPE) START(0x20200000) END(0x202FFFFF) WIDTH(8) }
MEM_ASYNC1 { TYPE(ASYNC1_MEMTYPE) START(0x20100000) END(0x201FFFFF) WIDTH(8) }
MEM_ASYNC0 { TYPE(ASYNC0_MEMTYPE) START(0x20000000) END(0x200FFFFF) WIDTH(8) }
MEM_SDRAM0 { TYPE(RAM) START(0x00000004) END(0x01ffffff) WIDTH(8) }
/*$VDSG<insert-new-memory-segments> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-new-memory-segments> */
} /* MEMORY */
PROCESSOR p0
{
OUTPUT($COMMAND_LINE_OUTPUT_FILE)
RESOLVE(start, 0xFFA00000)
KEEP(start, _main)
/*$VDSG<insert-user-ldf-commands> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-ldf-commands> */
SECTIONS
{
/* Workaround for hardware errata 05-00-0189 and 05-00-0310 -
** "Speculative (and fetches made at boundary of reserved memory
** space) for instruction or data fetches may cause false
** protection exceptions" and "False hardware errors caused by
** fetches at the boundary of reserved memory ".
**
** Done by avoiding use of 76 bytes from at the end of blocks
** that are adjacent to reserved memory. Workaround is enabled
** for appropriate silicon revisions (-si-revision switch).
*/
RESERVE(___wab0=MEMORY_END(MEM_L1_SCRATCH) - 75, ___l0 = 76)
RESERVE(___wab2=MEMORY_END(MEM_L1_CODE) - 75, ___l2 = 76)
RESERVE(___wab4=MEMORY_END(MEM_L1_DATA_B) - 75, ___l4 = 76)
RESERVE(___wab6=MEMORY_END(MEM_L1_DATA_A) - 75, ___l6 = 76)
RESERVE(___wab7=MEMORY_END(MEM_ASYNC3) - 75, ___l7 = 76)
RESERVE(___wab9=MEMORY_END(MEM_SDRAM0) - 75, ___l9 = 76)
/*$VDSG<insert-new-sections-at-the-start> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-new-sections-at-the-start> */
scratchpad NO_INIT
{
INPUT_SECTION_ALIGN(4)
/*$VDSG<insert-input-sections-at-the-start-of-scratchpad> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-start-of-scratchpad> */
INPUT_SECTIONS($OBJECTS(L1_scratchpad) $LIBRARIES(L1_scratchpad))
/*$VDSG<insert-input-sections-at-the-end-of-scratchpad> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-scratchpad> */
} > MEM_L1_SCRATCH
L1_code
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS($OBJECTS(L1_code) $LIBRARIES(L1_code))
/*$VDSG<insert-input-sections-at-the-start-of-l1_code> */
INPUT_SECTION_ALIGN(64)
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-start-of-l1_code> */
INPUT_SECTIONS($OBJECTS(cplb_code) $LIBRARIES(cplb_code))
INPUT_SECTIONS($OBJECTS(cplb) $LIBRARIES(cplb))
INPUT_SECTIONS($OBJECTS(noncache_code) $LIBRARIES(noncache_code))
INPUT_SECTIONS($OBJS_LIBS_INTERNAL(program))
INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(program))
INPUT_SECTIONS($OBJECTS(program) $LIBRARIES(program))
/*$VDSG<insert-input-sections-at-the-end-of-l1_code> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-l1_code> */
} > MEM_L1_CODE
L1_code_cache
{
INPUT_SECTION_ALIGN(4)
___l1_code_cache = 1;
} > MEM_L1_CODE_CACHE
L1_data_a_tables
{
INPUT_SECTION_ALIGN(4)
FORCE_CONTIGUITY
/*$VDSG<insert-input-sections-at-the-start-of-L1_data_a_tables> */
/* Text inserted between these $VDSG comments will be preserved */
INPUT_SECTION_ALIGN(64)
_startfix_sect = .;
INPUT_SECTIONS($OBJECTS(board_state) $LIBRARIES(board_state))
. = _startfix_sect + 8196;
/*$VDSG<insert-input-sections-at-the-start-of-L1_data_a_tables> */
/*$VDSG<insert-input-sections-in-the-middle-of-L1_data_a_tables> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-in-the-middle-of-L1_data_a_tables> */
/*$VDSG<insert-input-sections-at-the-end-of-L1_data_a_tables> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-L1_data_a_tables> */
} > MEM_L1_DATA_A
L1_data_a_1
{
INPUT_SECTION_ALIGN(4)
___l1_data_cache_a = 0;
INPUT_SECTIONS($OBJECTS(L1_data_a) $LIBRARIES(L1_data_a))
INPUT_SECTIONS($OBJECTS(L1_data) $LIBRARIES(L1_data))
/*$VDSG<insert-input-sections-at-the-start-of-L1_data_a> */
INPUT_SECTION_ALIGN(64)
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-start-of-L1_data_a> */
RESERVE(heaps_and_stack_in_L1_data_a, heaps_and_stack_in_L1_data_a_length = 2048,4)
} > MEM_L1_DATA_A
L1_data_a_bsz ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJECTS(L1_bsz) $LIBRARIES(L1_bsz))
} > MEM_L1_DATA_A
L1_data_a
{
INPUT_SECTION_ALIGN(4)
/*$VDSG<insert-input-sections-in-the-middle-of-L1_data_a> */
INPUT_SECTION_ALIGN(64)
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-in-the-middle-of-L1_data_a> */
INPUT_SECTIONS($OBJECTS(cplb_data) $LIBRARIES(cplb_data))
INPUT_SECTIONS($OBJECTS(voldata) $LIBRARIES(voldata))
INPUT_SECTIONS($OBJS_LIBS_INTERNAL(data1))
INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(data1))
INPUT_SECTIONS($OBJECTS(data1) $LIBRARIES(data1))
INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata))
/*$VDSG<insert-input-sections-at-the-end-of-L1_data_a> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-L1_data_a> */
} > MEM_L1_DATA_A
bsz_L1_data_a ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
/*$VDSG<insert-input-sections-at-the-start-of-bsz_L1_data_a> */
FORCE_CONTIGUITY
INPUT_SECTION_ALIGN(64)
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-start-of-bsz_L1_data_a> */
INPUT_SECTIONS($OBJS_LIBS_INTERNAL(bsz))
INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(bsz))
INPUT_SECTIONS($OBJECTS(bsz) $LIBRARIES(bsz))
/*$VDSG<insert-input-sections-at-the-end-of-bsz_L1_data_a> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-bsz_L1_data_a> */
} > MEM_L1_DATA_A
L1_data_a_stack_heap
{
INPUT_SECTION_ALIGN(4)
RESERVE_EXPAND(heaps_and_stack_in_L1_data_a, heaps_and_stack_in_L1_data_a_length , 0, 4)
ldf_stack_space = heaps_and_stack_in_L1_data_a;
ldf_stack_end = (ldf_stack_space + (heaps_and_stack_in_L1_data_a_length - 4)) & 0xfffffffc;
} > MEM_L1_DATA_A
L1_data_b_bsz ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJECTS(L1_bsz) $LIBRARIES(L1_bsz))
} > MEM_L1_DATA_B
L1_data_b
{
INPUT_SECTION_ALIGN(4)
___l1_data_cache_b = 0;
INPUT_SECTIONS($OBJECTS(L1_data_b) $LIBRARIES(L1_data_b))
INPUT_SECTIONS($OBJECTS(L1_data) $LIBRARIES(L1_data))
/*$VDSG<insert-input-sections-at-the-start-of-L1_data_b> */
INPUT_SECTION_ALIGN(64)
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-start-of-L1_data_b> */
RESERVE(heaps_and_stack_in_L1_data_b, heaps_and_stack_in_L1_data_b_length = 7168,4)
INPUT_SECTIONS($OBJECTS(cplb_data) $LIBRARIES(cplb_data))
INPUT_SECTIONS($OBJECTS(voldata) $LIBRARIES(voldata))
INPUT_SECTIONS($OBJS_LIBS_INTERNAL(data1))
INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(data1))
INPUT_SECTIONS($OBJECTS(data1) $LIBRARIES(data1))
INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata))
/*$VDSG<insert-input-sections-at-the-end-of-L1_data_b> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-L1_data_b> */
} > MEM_L1_DATA_B
bsz_L1_data_b ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
/*$VDSG<insert-input-sections-at-the-start-of-bsz_L1_data_b> */
INPUT_SECTION_ALIGN(64)
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-start-of-bsz_L1_data_b> */
INPUT_SECTIONS($OBJS_LIBS_INTERNAL(bsz))
INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(bsz))
INPUT_SECTIONS($OBJECTS(bsz) $LIBRARIES(bsz))
/*$VDSG<insert-input-sections-at-the-end-of-bsz_L1_data_b> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-bsz_L1_data_b> */
} > MEM_L1_DATA_B
L1_data_b_stack_heap
{
INPUT_SECTION_ALIGN(4)
RESERVE_EXPAND(heaps_and_stack_in_L1_data_b, heaps_and_stack_in_L1_data_b_length , 0, 4)
ldf_heap_space = heaps_and_stack_in_L1_data_b;
ldf_heap_end = (ldf_heap_space + (heaps_and_stack_in_L1_data_b_length - 4)) & 0xfffffffc;
ldf_heap_length = ldf_heap_end - ldf_heap_space;
} > MEM_L1_DATA_B
sdram
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS($OBJECTS(sdram0) $LIBRARIES(sdram0))
INPUT_SECTIONS($OBJECTS(sdram0_bank0) $LIBRARIES(sdram0_bank0))
INPUT_SECTIONS($OBJECTS(sdram0_bank1) $LIBRARIES(sdram0_bank1))
INPUT_SECTIONS($OBJECTS(sdram0_bank2) $LIBRARIES(sdram0_bank2))
INPUT_SECTIONS($OBJECTS(sdram0_bank3) $LIBRARIES(sdram0_bank3))
/*$VDSG<insert-input-sections-at-the-start-of-sdram> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-start-of-sdram> */
INPUT_SECTIONS($OBJECTS(noncache_code) $LIBRARIES(noncache_code))
INPUT_SECTIONS($OBJECTS(program) $LIBRARIES(program))
INPUT_SECTIONS($OBJECTS(cplb) $LIBRARIES(cplb))
INPUT_SECTIONS($OBJECTS(cplb_code) $LIBRARIES(cplb_code))
INPUT_SECTIONS($OBJECTS(data1) $LIBRARIES(data1))
INPUT_SECTIONS($OBJECTS(voldata) $LIBRARIES(voldata))
INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata))
INPUT_SECTIONS($OBJECTS(cplb_data) $LIBRARIES(cplb_data))
/*$VDSG<insert-input-sections-at-the-end-of-sdram> */
INPUT_SECTION_ALIGN(64)
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-sdram> */
} > MEM_SDRAM0
bsz_sdram0 ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS($OBJECTS(sdram_bsz) $LIBRARIES(sdram_bsz))
INPUT_SECTIONS($OBJECTS(bsz) $LIBRARIES(bsz))
} > MEM_SDRAM0
sdram_stack_heap
{
} > MEM_SDRAM0
/*$VDSG<insert-new-sections-at-the-end> */
/* Text inserted between these $VDSG comments will be preserved */
noinit_sdram0 NO_INIT
{
INPUT_SECTION_ALIGN(64)
INPUT_SECTIONS($OBJECTS(sdram_noinit) $LIBRARIES(sdram_noinit))
} > MEM_SDRAM0
/*$VDSG<insert-new-sections-at-the-end> */
} /* SECTIONS */
} /* p0 */
vdsp/l502-bf_basiccrt.s
+324
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@@ -0,0 +1,324 @@
/* MANAGED-BY-SYSTEM-BUILDER */
/* VisualDSP++ 5.0 Update 10.1 */
/* CRT Printer version: 5.9.0.1 */
/* crtgen.exe version: 5.9.0.1 */
/* VDSG version: 5.9.0.1 */
/*
** l502-bf_basiccrt.s generated on Oct 22, 2012 at 13:05:29.
**
** Copyright (C) 2000-2010 Analog Devices Inc., All Rights Reserved.
** This contains Analog Devices Background IP and Development IP as
** defined in the ADI/Intel Collaboration Agreement.
**
** This file is generated automatically based upon the options selected
** in the Startup Code Wizard. Changes to the startup configuration
** should be made by changing the appropriate options rather than
** editing this file. Additional user code to be executed before calling
** main can be inserted between the labels .start_of_user_code1 and
** .end_of_user_code1 or .start_of_user_code2 and .end_of_user_code2.
** This code is preserved if the CRT is re-generated.
**
** Configuration:-
** product_name: VisualDSP++ 5.0 Update 10.1
** processor: ADSP-BF523
** si_revision: 0.2
** cplb_init: true
** cplb_ctrl: (
** CPLB_ENABLE_ICACHE
** CPLB_ENABLE_ICPLBS
** )
** mem_init: false
** device_init: false
** init_regs: false
** zero_return_regs: false
** use_profiling: false
** using_cplusplus: false
** use_argv: false
** main_never_returns: true
** use_default_handlers: true
** use_vdk: false
** set_clock_and_power: false
** detect_stackoverflow: false
**
*/
/////////////////////////////////////////////////////////////////
// blackfin-edinburgh-core
#include <sys/platform.h>
#include <sys/anomaly_macros_rtl.h>
/////////////////////////////////////////////////////////////////
// standard
#define IVBh (EVT0 >> 16)
#define IVBl (EVT0 & 0xFFFF)
#define UNASSIGNED_VAL 0x8181
#define INTERRUPT_BITS 0x400 // just IVG15
#define SYSCFG_VALUE 0x30
.section/DOUBLEANY program;
.file_attr requiredForROMBoot;
.align 2;
start:
/*$VDSG<insert-code-very-beginning> */
.start_of_user_code_very_beginning:
// Insert additional code to be executed before any other Startup Code here.
// This code is preserved if the CRT is re-generated.
.end_of_user_code_very_beginning:
/*$VDSG<insert-code-very-beginning> */
/////////////////////////////////////////////////////////////////
// standard
#if WA_05000229
// Avoid Anomaly 05-00-0229: DMA5_CONFIG and SPI_CTL not cleared on reset.
R1 = 0x400;
#if defined(__ADSPBF538__) || defined(__ADSPBF539__)
P0.L = SPI0_CTL & 0xFFFF;
P0.H = SPI0_CTL >> 16;
W[P0] = R1.L;
#else
P0.L = SPI_CTL & 0xFFFF;
P0.H = SPI_CTL >> 16;
W[P0] = R1.L;
#endif
P0.L = DMA5_CONFIG & 0xFFFF;
P0.H = DMA5_CONFIG >> 16;
R1 = 0;
W[P0] = R1.L;
#endif
// Clear loop counters to disable hardware loops
R7 = 0;
LC0 = R7;
LC1 = R7;
// Clear the DAG Length regs, to force linear addressing
L0 = R7;
L1 = R7;
L2 = R7;
L3 = R7;
// Clear ITEST_COMMAND and DTEST_COMMAND registers
I0.L = (ITEST_COMMAND & 0xFFFF);
I0.H = (ITEST_COMMAND >> 16);
I1.L = (DTEST_COMMAND & 0xFFFF);
I1.H = (DTEST_COMMAND >> 16);
[I0] = R7;
[I1] = R7;
CSYNC;
// Initialise the Event Vector table.
P0.H = IVBh;
P0.L = IVBl;
// Install __unknown_exception_occurred in EVT so that
// there is defined behaviour.
P0 += 2*4; // Skip Emulation and Reset
P1 = 13;
R1.L = __unknown_exception_occurred;
R1.H = __unknown_exception_occurred;
LSETUP (.ivt,.ivt) LC0 = P1;
.ivt: [P0++] = R1;
// Set IVG15's handler to be the start of the mode-change
// code. Then, before we return from the Reset back to user
// mode, we'll raise IVG15. This will mean we stay in supervisor
// mode, and continue from the mode-change point, but at a
// much lower priority.
P1.H = supervisor_mode;
P1.L = supervisor_mode;
[P0] = P1;
/////////////////////////////////////////////////////////////////
// cplb-handler
#include "cplb.h"
P1.H = _cplb_hdr;
P1.L = _cplb_hdr;
[P0-48] = P1; // write exception handler
.extern _cplb_hdr;
/////////////////////////////////////////////////////////////////
// standard
// Initialise the stack.
// Note: this points just past the end of the section.
// First write should be with [--SP].
SP.L=ldf_stack_end;
SP.H=ldf_stack_end;
usp = sp;
// We're still in supervisor mode at the moment, so the FP
// needs to point to the supervisor stack.
FP = SP;
// Make space for incoming "parameters" for functions
// we call from here:
SP += -12;
R0 = INTERRUPT_BITS;
R0 <<= 5; // Bits 0-4 not settable.
/////////////////////////////////////////////////////////////////
// install-default-handlers
CALL.X __install_default_handlers;
.extern __install_default_handlers;
.type __install_default_handlers,STT_FUNC;
/////////////////////////////////////////////////////////////////
// standard
R1 = SYSCFG;
R4 = R0; // Save modified list
BITSET(R1,1);
SYSCFG = R1; // Enable the cycle counter
/*$VDSG<insert-code-early-startup> */
.start_of_user_code1:
// Insert additional code to be executed before main here.
// This code is preserved if the CRT is re-generated.
.end_of_user_code1:
/*$VDSG<insert-code-early-startup> */
/////////////////////////////////////////////////////////////////
// cplb-init
// initialise the CPLBs if they're needed. This was not possible
// before we set up the stacks.
R0 = 17; // cplb_ctrl = 17
CALL.X _cplb_init;
.extern _cplb_init;
.type _cplb_init,STT_FUNC;
.section/DOUBLEANY cplb_data;
// Set the CPLB control variable. It's defined in a section that will be
// covered by an installed locked CPLB.
___cplb_ctrl:
.align 4;
.byte4=17;
.global ___cplb_ctrl;
.type ___cplb_ctrl,STT_OBJECT;
.section/DOUBLEANY program;
.align 2;
/////////////////////////////////////////////////////////////////
// standard
// Enable interrupts
STI R4; // Using the mask from default handlers
RAISE 15;
// Move the processor into user mode.
P0.L=still_interrupt_in_ipend;
P0.H=still_interrupt_in_ipend;
RETI=P0;
NOP; // Purely to prevent a stall warning
still_interrupt_in_ipend:
// execute RTI until we've `finished` servicing all
// interrupts of priority higher than IVG15. Normally one
// would expect to only have the reset interrupt in IPEND
// being serviced, but occasionally when debugging this may
// not be the case - if restart is hit when servicing an
// interrupt.
//
// When we clear all bits from IPEND, we'll enter user mode,
// then we'll automatically jump to supervisor_mode to start
// servicing IVG15 (which we will 'service' for the whole
// program, so that the program is in supervisor mode.
// Need to do this to 'finish' servicing the reset interupt.
RTI;
supervisor_mode:
[--SP] = RETI; // re-enables the interrupt system
R0.L = UNASSIGNED_VAL;
R0.H = UNASSIGNED_VAL;
// Push a RETS and Old FP onto the stack, for sanity.
[--SP]=R0;
[--SP]=R0;
// Make sure the FP is sensible.
FP = SP;
// Leave space for incoming "parameters"
SP += -12;
/*$VDSG<insert-code-before-device-initialization> */
.start_of_user_code2:
// Insert additional code to be executed before device initialization here.
// This code is preserved if the CRT is re-generated.
.end_of_user_code2:
/*$VDSG<insert-code-before-device-initialization> */
/*$VDSG<insert-code-before-main-entry> */
.start_of_user_code3:
// Insert additional code to be executed before main here.
// This code is preserved if the CRT is re-generated.
.end_of_user_code3:
/*$VDSG<insert-code-before-main-entry> */
/////////////////////////////////////////////////////////////////
// standard
// Call the application program.
CALL.X _main;
/////////////////////////////////////////////////////////////////
// standard
.start.end: // Required by the linker to know the size of the routine
// that is needed for absolute placement.
.global start;
.type start,STT_FUNC;
.extern _main;
.type _main,STT_FUNC;
.extern ldf_stack_end;
.extern __unknown_exception_occurred;
.type __unknown_exception_occurred,STT_FUNC;
/////////////////////////////////////////////////////////////////
// no-device-initialization
// If File IO support isn't provided, then
// we provide dummy versions of the device-handling
// functions, so that the exception handlers don't rely
// on the file IO library
.section/DOUBLEANY program;
.align 2;
_dev_open:
_dev_close:
_dev_write:
_dev_read:
_dev_seek:
_dev_dup:
#if WA_05000371
/* Avoid anomaly 05-00-0371 by ensuring 4 instructions
** before an RTS.
*/
NOP;
NOP;
NOP;
#endif
R0 = -1;
RTS;
._dev_open.end:
._dev_close.end:
._dev_write.end:
._dev_read.end:
._dev_seek.end:
._dev_dup.end:
.global _dev_open;
.type _dev_open,STT_FUNC;
.global _dev_close;
.type _dev_close,STT_FUNC;
.global _dev_write;
.type _dev_write,STT_FUNC;
.global _dev_read;
.type _dev_read,STT_FUNC;
.global _dev_seek;
.type _dev_seek,STT_FUNC;
.global _dev_dup;
.type _dev_dup,STT_FUNC;
vdsp/l502-bf_heaptab.c
+93
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@@ -0,0 +1,93 @@
/* MANAGED-BY-SYSTEM-BUILDER */
/* VisualDSP++ 5.0 Update 10.1 */
/* LDF Printer version: 5.9.0.1 */
/* ldfgen.exe version: 5.9.0.1 */
/* VDSG version: 5.9.0.1 */
/*
** User heap source file generated on Oct 22, 2012 at 13:05:29.
**
** Copyright (C) 2000-2010 Analog Devices Inc., All Rights Reserved.
**
** This file is generated automatically based upon the options selected
** in the LDF Wizard. Changes to the LDF configuration should be made by
** changing the appropriate options rather than editing this file.
**
** Configuration:-
** crt_doj: l502-bf_basiccrt.doj
** processor: ADSP-BF523
** product_name: VisualDSP++ 5.0 Update 10.1
** si_revision: 0.2
** default_silicon_revision_from_archdef: 0.2
** cplb_init_cplb_ctrl: 17
** using_cplusplus: false
** mem_init: false
** use_vdk: false
** use_mt: false
** use_eh: false
** use_argv: false
** running_from_internal_memory: true
** user_heap_src_file: C:\PRJ\L502\lpcie_sdk\firmware\l502-bf\vdsp\l502-bf_heaptab.c
** libraries_use_stdlib: true
** libraries_use_fileio_libs: false
** libraries_use_ieeefp_emulation_libs: false
** libraries_use_eh_enabled_libs: false
** libraries_use_fixed_point_io_libs: false
** libraries_use_utility_rom: true
** detect_stackoverflow: false
** system_heap: L1
** system_heap_min_size: 7k
** system_stack: L1
** system_stack_min_size: 2k
** use_sdram: true
** use_sdram_size: 32MB
** use_sdram_partitioned: none
**
*/
#ifdef _MISRA_RULES
#pragma diag(push)
#pragma diag(suppress:misra_rule_1_1)
#pragma diag(suppress:misra_rule_2_2)
#pragma diag(suppress:misra_rule_6_3)
#pragma diag(suppress:misra_rule_8_10)
#pragma diag(suppress:misra_rule_10_1_a)
#pragma diag(suppress:misra_rule_11_3)
#pragma diag(suppress:misra_rule_12_7)
#else
#pragma diag(suppress:1124)
#endif /* _MISRA_RULES */
extern "asm" int ldf_heap_space;
extern "asm" int ldf_heap_length;
struct heap_table_t
{
void *base;
unsigned long length;
long int userid;
};
#pragma file_attr("libData=HeapTable")
#pragma section("constdata")
struct heap_table_t heap_table[2] =
{
{ &ldf_heap_space, (unsigned long) &ldf_heap_length, 0 },
{ 0, 0, 0 }
};
#ifdef _MISRA_RULES
#pragma diag(pop)
#endif /* _MISRA_RULES */
vdsp/l502_sdram_noinit.h
+1
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@@ -0,0 +1 @@
#pragma section("sdram_noinit", NO_INIT)