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This commit is contained in:
Theodor Chikin
2025-06-27 15:12:44 +03:00
commit c73ead2643
76 changed files with 45689 additions and 0 deletions
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vdsp/l502-bf.ldf Normal file
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/* MANAGED-BY-SYSTEM-BUILDER */
/* VisualDSP++ 5.0 Update 10.1 */
/* LDF Printer version: 5.9.0.1 */
/* ldfgen.exe version: 5.9.0.1 */
/* VDSG version: 5.9.0.1 */
/*
** ADSP-BF523 linker description file generated on Jan 10, 2013 at 19:23:18.
**
** Copyright (C) 2000-2010 Analog Devices Inc., All Rights Reserved.
**
** This file is generated automatically based upon the options selected
** in the LDF Wizard. Changes to the LDF configuration should be made by
** changing the appropriate options rather than editing this file.
**
** Configuration:-
** crt_doj: l502-bf_basiccrt.doj
** processor: ADSP-BF523
** product_name: VisualDSP++ 5.0 Update 10.1
** si_revision: 0.2
** default_silicon_revision_from_archdef: 0.2
** cplb_init_cplb_ctrl: (
** CPLB_ENABLE_ICACHE
** CPLB_ENABLE_ICPLBS
** )
** using_cplusplus: false
** mem_init: false
** use_vdk: false
** use_mt: false
** use_eh: false
** use_argv: false
** running_from_internal_memory: true
** user_heap_src_file: C:\PRJ\L502\builds\lpcie_sdk\release\firmware-conv\l502-bf\vdsp\l502-bf_heaptab.c
** libraries_use_stdlib: true
** libraries_use_fileio_libs: false
** libraries_use_ieeefp_emulation_libs: false
** libraries_use_eh_enabled_libs: false
** libraries_use_fixed_point_io_libs: false
** libraries_use_utility_rom: true
** detect_stackoverflow: false
** system_heap: L1
** system_heap_min_size: 7k
** system_stack: L1
** system_stack_min_size: 2k
** use_sdram: true
** use_sdram_size: 32MB
** use_sdram_partitioned: none
**
*/
ARCHITECTURE(ADSP-BF523)
SEARCH_DIR($ADI_DSP/Blackfin/lib)
// Workarounds are enabled, exceptions are disabled.
#define RT_LIB_NAME(x) lib ## x ## y.dlb
#define RT_LIB_NAME_EH(x) lib ## x ## y.dlb
#define RT_LIB_NAME_MT(x) lib ## x ## y.dlb
#define RT_LIB_NAME_EH_MT(x) lib ## x ## y.dlb
#define RT_OBJ_NAME(x) x ## y.doj
#define RT_OBJ_NAME_MT(x) x ## mty.doj
$LIBRARIES =
/*$VDSG<insert-user-libraries-at-beginning> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-libraries-at-beginning> */
RT_LIB_NAME_MT(small532)
,RT_LIB_NAME_MT(io532)
,RT_LIB_NAME_MT(c532)
,RT_LIB_NAME_MT(event532)
,RT_LIB_NAME(ssl527)
,RT_LIB_NAME(drv527)
,RT_LIB_NAME(usb527)
,RT_LIB_NAME(f64ieee532)
,RT_LIB_NAME(dsp532)
,RT_LIB_NAME(sftflt532)
,RT_LIB_NAME(etsi532)
,RT_LIB_NAME(ftl527)
,RT_OBJ_NAME_MT(idle532)
,RT_LIB_NAME_MT(rt_fileio532)
/*$VDSG<insert-user-libraries-at-end> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-libraries-at-end> */
;
$OBJECTS =
"l502-bf_basiccrt.doj"
/*$VDSG<insert-user-objects-at-beginning> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-objects-at-beginning> */
, RT_LIB_NAME(profile532)
, $COMMAND_LINE_OBJECTS
, "cplbtab523.doj"
/*$VDSG<insert-user-objects-at-end> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-objects-at-end> */
;
$OBJS_LIBS_INTERNAL =
/*$VDSG<insert-libraries-internal> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-internal> */
$OBJECTS{prefersMem("internal")}, $LIBRARIES{prefersMem("internal")}
/*$VDSG<insert-libraries-internal-end> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-internal-end> */
;
$OBJS_LIBS_NOT_EXTERNAL =
/*$VDSG<insert-libraries-not-external> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-not-external> */
$OBJECTS{!prefersMem("external")}, $LIBRARIES{!prefersMem("external")}
/*$VDSG<insert-libraries-not-external-end> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-not-external-end> */
;
/*$VDSG<insert-user-macros> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-macros> */
/*$VDSG<customize-async-macros> */
/* This code is preserved if the LDF is re-generated. */
#define ASYNC0_MEMTYPE RAM
#define ASYNC1_MEMTYPE RAM
#define ASYNC2_MEMTYPE RAM
#define ASYNC3_MEMTYPE RAM
/*$VDSG<customize-async-macros> */
MEMORY
{
/*
** ADSP-BF523 MEMORY MAP.
**
** The known memory spaces are as follows:
**
** 0xFFE00000 - 0xFFFFFFFF Core MMR registers (2MB)
** 0xFFC00000 - 0xFFDFFFFF System MMR registers (2MB)
** 0xFFB01000 - 0xFFBFFFFF Reserved
** 0xFFB00000 - 0xFFB00FFF Scratch SRAM (4K)
** 0xFFA14000 - 0xFFAFFFFF Reserved
** 0xFFA10000 - 0XFFA13FFF Code SRAM/CACHE (16K)
** 0xFFA0C000 - 0xFFA0FFFF Reserved
** 0xFFA08000 - 0xFFA0BFFF Instruction Bank B SRAM (16K)
** 0xFFA00000 - 0xFFA07FFF Instruction Bank A SRAM (32K)
** 0xFF908000 - 0xFF9FFFFF Reserved
** 0xFF904000 - 0xFF907FFF Data Bank B SRAM/CACHE (16K)
** 0xFF900000 - 0XFF903FFF Data Bank B SRAM (16K)
** 0xFF808000 - 0xFF8FFFFF Reserved
** 0xFF804000 - 0xFF807FFF Data Bank A SRAM/CACHE (16K)
** 0xFF800000 - 0XFF803FFF Data Bank A SRAM (16K)
** 0xEF000800 - 0xFF800000 Reserved
** 0xEF000000 - 0xFF8007FF Boot ROM (2K)
** 0x20400000 - 0xEEFFFFFF Reserved
** 0x20300000 - 0x203FFFFF ASYNC MEMORY BANK 3 (1MB)
** 0x20200000 - 0x202FFFFF ASYNC MEMORY BANK 2 (1MB)
** 0x20100000 - 0x201FFFFF ASYNC MEMORY BANK 1 (1MB)
** 0x20000000 - 0x200FFFFF ASYNC MEMORY BANK 0 (1MB)
** 0x00000000 - 0x07FFFFFF SDRAM MEMORY (16MB - 128MB)
**
** Notes:
** 0xFF807FEF-0xFF807FFF
** Required by boot-loader. Used as heap or cache below which is ok. Cannot
** contain initialized data or code.
*/
MEM_L1_SCRATCH { TYPE(RAM) START(0xFFB00000) END(0xFFB00FFF) WIDTH(8) }
MEM_L1_CODE_CACHE { TYPE(RAM) START(0xFFA10000) END(0xFFA13FFF) WIDTH(8) }
MEM_L1_CODE { TYPE(RAM) START(0xFFA00000) END(0xFFA0BFFF) WIDTH(8) }
MEM_L1_DATA_B { TYPE(RAM) START(0xFF900000) END(0xFF907FFF) WIDTH(8) }
MEM_L1_DATA_A { TYPE(RAM) START(0xFF800000) END(0xFF807FFF) WIDTH(8) }
MEM_ASYNC3 { TYPE(ASYNC3_MEMTYPE) START(0x20300000) END(0x203FFFFF) WIDTH(8) }
MEM_ASYNC2 { TYPE(ASYNC2_MEMTYPE) START(0x20200000) END(0x202FFFFF) WIDTH(8) }
MEM_ASYNC1 { TYPE(ASYNC1_MEMTYPE) START(0x20100000) END(0x201FFFFF) WIDTH(8) }
MEM_ASYNC0 { TYPE(ASYNC0_MEMTYPE) START(0x20000000) END(0x200FFFFF) WIDTH(8) }
MEM_SDRAM0 { TYPE(RAM) START(0x00000004) END(0x01ffffff) WIDTH(8) }
/*$VDSG<insert-new-memory-segments> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-new-memory-segments> */
} /* MEMORY */
PROCESSOR p0
{
OUTPUT($COMMAND_LINE_OUTPUT_FILE)
RESOLVE(start, 0xFFA00000)
KEEP(start, _main)
/*$VDSG<insert-user-ldf-commands> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-ldf-commands> */
SECTIONS
{
/* Workaround for hardware errata 05-00-0189 and 05-00-0310 -
** "Speculative (and fetches made at boundary of reserved memory
** space) for instruction or data fetches may cause false
** protection exceptions" and "False hardware errors caused by
** fetches at the boundary of reserved memory ".
**
** Done by avoiding use of 76 bytes from at the end of blocks
** that are adjacent to reserved memory. Workaround is enabled
** for appropriate silicon revisions (-si-revision switch).
*/
RESERVE(___wab0=MEMORY_END(MEM_L1_SCRATCH) - 75, ___l0 = 76)
RESERVE(___wab2=MEMORY_END(MEM_L1_CODE) - 75, ___l2 = 76)
RESERVE(___wab4=MEMORY_END(MEM_L1_DATA_B) - 75, ___l4 = 76)
RESERVE(___wab6=MEMORY_END(MEM_L1_DATA_A) - 75, ___l6 = 76)
RESERVE(___wab7=MEMORY_END(MEM_ASYNC3) - 75, ___l7 = 76)
RESERVE(___wab9=MEMORY_END(MEM_SDRAM0) - 75, ___l9 = 76)
/*$VDSG<insert-new-sections-at-the-start> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-new-sections-at-the-start> */
scratchpad NO_INIT
{
INPUT_SECTION_ALIGN(4)
/*$VDSG<insert-input-sections-at-the-start-of-scratchpad> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-start-of-scratchpad> */
INPUT_SECTIONS($OBJECTS(L1_scratchpad) $LIBRARIES(L1_scratchpad))
/*$VDSG<insert-input-sections-at-the-end-of-scratchpad> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-scratchpad> */
} > MEM_L1_SCRATCH
L1_code
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS($OBJECTS(L1_code) $LIBRARIES(L1_code))
/*$VDSG<insert-input-sections-at-the-start-of-l1_code> */
INPUT_SECTION_ALIGN(64)
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-start-of-l1_code> */
INPUT_SECTIONS($OBJECTS(cplb_code) $LIBRARIES(cplb_code))
INPUT_SECTIONS($OBJECTS(cplb) $LIBRARIES(cplb))
INPUT_SECTIONS($OBJECTS(noncache_code) $LIBRARIES(noncache_code))
INPUT_SECTIONS($OBJS_LIBS_INTERNAL(program))
INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(program))
INPUT_SECTIONS($OBJECTS(program) $LIBRARIES(program))
/*$VDSG<insert-input-sections-at-the-end-of-l1_code> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-l1_code> */
} > MEM_L1_CODE
L1_code_cache
{
INPUT_SECTION_ALIGN(4)
___l1_code_cache = 1;
} > MEM_L1_CODE_CACHE
L1_data_a_tables
{
INPUT_SECTION_ALIGN(4)
FORCE_CONTIGUITY
/*$VDSG<insert-input-sections-at-the-start-of-L1_data_a_tables> */
/* Text inserted between these $VDSG comments will be preserved */
INPUT_SECTION_ALIGN(64)
_startfix_sect = .;
INPUT_SECTIONS($OBJECTS(board_state) $LIBRARIES(board_state))
. = _startfix_sect + 8196;
/*$VDSG<insert-input-sections-at-the-start-of-L1_data_a_tables> */
/*$VDSG<insert-input-sections-in-the-middle-of-L1_data_a_tables> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-in-the-middle-of-L1_data_a_tables> */
/*$VDSG<insert-input-sections-at-the-end-of-L1_data_a_tables> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-L1_data_a_tables> */
} > MEM_L1_DATA_A
L1_data_a_1
{
INPUT_SECTION_ALIGN(4)
___l1_data_cache_a = 0;
INPUT_SECTIONS($OBJECTS(L1_data_a) $LIBRARIES(L1_data_a))
INPUT_SECTIONS($OBJECTS(L1_data) $LIBRARIES(L1_data))
/*$VDSG<insert-input-sections-at-the-start-of-L1_data_a> */
INPUT_SECTION_ALIGN(64)
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-start-of-L1_data_a> */
RESERVE(heaps_and_stack_in_L1_data_a, heaps_and_stack_in_L1_data_a_length = 2048,4)
} > MEM_L1_DATA_A
L1_data_a_bsz ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJECTS(L1_bsz) $LIBRARIES(L1_bsz))
} > MEM_L1_DATA_A
L1_data_a
{
INPUT_SECTION_ALIGN(4)
/*$VDSG<insert-input-sections-in-the-middle-of-L1_data_a> */
INPUT_SECTION_ALIGN(64)
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-in-the-middle-of-L1_data_a> */
INPUT_SECTIONS($OBJECTS(cplb_data) $LIBRARIES(cplb_data))
INPUT_SECTIONS($OBJECTS(voldata) $LIBRARIES(voldata))
INPUT_SECTIONS($OBJS_LIBS_INTERNAL(data1))
INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(data1))
INPUT_SECTIONS($OBJECTS(data1) $LIBRARIES(data1))
INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata))
/*$VDSG<insert-input-sections-at-the-end-of-L1_data_a> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-L1_data_a> */
} > MEM_L1_DATA_A
bsz_L1_data_a ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
/*$VDSG<insert-input-sections-at-the-start-of-bsz_L1_data_a> */
FORCE_CONTIGUITY
INPUT_SECTION_ALIGN(64)
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-start-of-bsz_L1_data_a> */
INPUT_SECTIONS($OBJS_LIBS_INTERNAL(bsz))
INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(bsz))
INPUT_SECTIONS($OBJECTS(bsz) $LIBRARIES(bsz))
/*$VDSG<insert-input-sections-at-the-end-of-bsz_L1_data_a> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-bsz_L1_data_a> */
} > MEM_L1_DATA_A
L1_data_a_stack_heap
{
INPUT_SECTION_ALIGN(4)
RESERVE_EXPAND(heaps_and_stack_in_L1_data_a, heaps_and_stack_in_L1_data_a_length , 0, 4)
ldf_stack_space = heaps_and_stack_in_L1_data_a;
ldf_stack_end = (ldf_stack_space + (heaps_and_stack_in_L1_data_a_length - 4)) & 0xfffffffc;
} > MEM_L1_DATA_A
L1_data_b_bsz ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJECTS(L1_bsz) $LIBRARIES(L1_bsz))
} > MEM_L1_DATA_B
L1_data_b
{
INPUT_SECTION_ALIGN(4)
___l1_data_cache_b = 0;
INPUT_SECTIONS($OBJECTS(L1_data_b) $LIBRARIES(L1_data_b))
INPUT_SECTIONS($OBJECTS(L1_data) $LIBRARIES(L1_data))
/*$VDSG<insert-input-sections-at-the-start-of-L1_data_b> */
INPUT_SECTION_ALIGN(64)
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-start-of-L1_data_b> */
RESERVE(heaps_and_stack_in_L1_data_b, heaps_and_stack_in_L1_data_b_length = 7168,4)
INPUT_SECTIONS($OBJECTS(cplb_data) $LIBRARIES(cplb_data))
INPUT_SECTIONS($OBJECTS(voldata) $LIBRARIES(voldata))
INPUT_SECTIONS($OBJS_LIBS_INTERNAL(data1))
INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(data1))
INPUT_SECTIONS($OBJECTS(data1) $LIBRARIES(data1))
INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata))
/*$VDSG<insert-input-sections-at-the-end-of-L1_data_b> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-L1_data_b> */
} > MEM_L1_DATA_B
bsz_L1_data_b ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
/*$VDSG<insert-input-sections-at-the-start-of-bsz_L1_data_b> */
INPUT_SECTION_ALIGN(64)
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-start-of-bsz_L1_data_b> */
INPUT_SECTIONS($OBJS_LIBS_INTERNAL(bsz))
INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(bsz))
INPUT_SECTIONS($OBJECTS(bsz) $LIBRARIES(bsz))
/*$VDSG<insert-input-sections-at-the-end-of-bsz_L1_data_b> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-bsz_L1_data_b> */
} > MEM_L1_DATA_B
L1_data_b_stack_heap
{
INPUT_SECTION_ALIGN(4)
RESERVE_EXPAND(heaps_and_stack_in_L1_data_b, heaps_and_stack_in_L1_data_b_length , 0, 4)
ldf_heap_space = heaps_and_stack_in_L1_data_b;
ldf_heap_end = (ldf_heap_space + (heaps_and_stack_in_L1_data_b_length - 4)) & 0xfffffffc;
ldf_heap_length = ldf_heap_end - ldf_heap_space;
} > MEM_L1_DATA_B
sdram
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS($OBJECTS(sdram0) $LIBRARIES(sdram0))
INPUT_SECTIONS($OBJECTS(sdram0_bank0) $LIBRARIES(sdram0_bank0))
INPUT_SECTIONS($OBJECTS(sdram0_bank1) $LIBRARIES(sdram0_bank1))
INPUT_SECTIONS($OBJECTS(sdram0_bank2) $LIBRARIES(sdram0_bank2))
INPUT_SECTIONS($OBJECTS(sdram0_bank3) $LIBRARIES(sdram0_bank3))
/*$VDSG<insert-input-sections-at-the-start-of-sdram> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-start-of-sdram> */
INPUT_SECTIONS($OBJECTS(noncache_code) $LIBRARIES(noncache_code))
INPUT_SECTIONS($OBJECTS(program) $LIBRARIES(program))
INPUT_SECTIONS($OBJECTS(cplb) $LIBRARIES(cplb))
INPUT_SECTIONS($OBJECTS(cplb_code) $LIBRARIES(cplb_code))
INPUT_SECTIONS($OBJECTS(data1) $LIBRARIES(data1))
INPUT_SECTIONS($OBJECTS(voldata) $LIBRARIES(voldata))
INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata))
INPUT_SECTIONS($OBJECTS(cplb_data) $LIBRARIES(cplb_data))
/*$VDSG<insert-input-sections-at-the-end-of-sdram> */
INPUT_SECTION_ALIGN(64)
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-sdram> */
} > MEM_SDRAM0
bsz_sdram0 ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS($OBJECTS(sdram_bsz) $LIBRARIES(sdram_bsz))
INPUT_SECTIONS($OBJECTS(bsz) $LIBRARIES(bsz))
} > MEM_SDRAM0
sdram_stack_heap
{
} > MEM_SDRAM0
/*$VDSG<insert-new-sections-at-the-end> */
/* Text inserted between these $VDSG comments will be preserved */
noinit_sdram0 NO_INIT
{
INPUT_SECTION_ALIGN(64)
INPUT_SECTIONS($OBJECTS(sdram_noinit) $LIBRARIES(sdram_noinit))
} > MEM_SDRAM0
/*$VDSG<insert-new-sections-at-the-end> */
} /* SECTIONS */
} /* p0 */