ChTheo/E502_ADC_BFfirmware
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

git init of an empty project

Browse Source
This commit is contained in:
Theodor Chikin
2025-06-27 15:12:44 +03:00
commit c73ead2643
76 changed files with 45689 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

433
vdsp/l502-bf.dpj Normal file
View File

@ -0,0 +1,433 @@
<?xml version="1.0" encoding='ISO-8859-1'?>
<visualdsp-project schema="17" name="l502-bf" file="l502-bf.dpj" version="1">
<!-- Project build target -->
<target>
<processor revision="0.2">ADSP-BF523</processor>
<extension>.ldr</extension>
<type>Loader file</type>
</target>
<!-- Configurations -->
<configurations active="Release">
<configuration name="Debug">
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
<changed-property-page-flags>4</changed-property-page-flags>
<tools>
<tool type="Compiler">
<option><![CDATA[|-Version>5.0|-O>0|-O1>0|-Ov>100|-ipa>0|-g>1|-no-annotate>0|-save-temps -path-output>0|-ED>0|-no-auto-attrs>0|-no-builtin>0|-no-extra-keywords>0|-enum-is-int>0|-no-fp-associative>0|-structs-do-not-overlap>1|-implicit-pointers>0|-eh >0|-rtti>0|-check-init-order>0|-ignore-std>1|-const-read-write>0|-const-strings>0|-no-multiline>1|-misra>0|-misra-strict>0|-misra-no-cross-module>0|-misra-no-runtime>0|-misra-testing>0|-misra-suppress-advisory>0|-no-std-inc>0|-double-size-64>1|-double-size-any>0|-Ofp>0|-guard-vol-loads>0|-decls-strong>1|-no-saturation>0|-cplbs>1|-sdram>0|-multicore>0|-stack-detect>0|-pguide>0|NOSWITCH>0|-flags-compiler --diag_warning,implicit_func_decl>1|-warn-protos>1|-flags-compiler --diag_warning,call_not_inlined>1|-Wremarks>0|-w>0]]></option>
</tool>
<tool type="Assembler">
<option><![CDATA[|-Version>4.5|-v>0|-g>1|-l>0|-save-temps>0|-sp>0]]></option>
</tool>
<tool type="Linker">
<option><![CDATA[|-Version>5.0|-flags-link -t>0|-flags-link -S>0|-flags-link -s>0|-mem>0|-flags-link -warnonce>0|-map>0|-flags-link -xref>0|-flags-link -save-temps>0|-flags-link -ip>0|-MD>USER_CRT="l502-bf_basiccrt.doj",USE_CACHE,USE_INSTRUCTION_CACHE|-flags-link -e>0|-flags-link -ev>0|-add-debug-libpaths>1|-flags-link -MD__ADI_LIBEH__>0|-multicore>0|-flags-link -MDUSE_CACHE>1|NOSWITCH>1]]></option>
</tool>
<tool type="Archiver">
<option><![CDATA[]]></option>
</tool>
<tool type="Loader">
<option><![CDATA[|-Version>4.5|-b HOSTDP>1|-f BINARY>1|-Width 16>1|-p>0x0|DefaultStart>0|-v>0|-waits >-1|-BaudRate 500k>1|-HoldTime >-1|-pFlag >-1|-zinit>0|-No2Kernel>0|-o2>0|-kb Flash>1|-kf HEX>1|-kWidth 8>1|-kp>0x0|DefaultKernelStart>1|UserKernel>1|-romsplitter>0|split HEX>1|-maskaddr>0]]></option>
</tool>
<tool type="VdkGen">
<option><![CDATA[]]></option>
</tool>
</tools>
</configuration>
<configuration name="Release">
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
<changed-property-page-flags>0</changed-property-page-flags>
<tools>
<tool type="Compiler">
<option><![CDATA[|-Version>5.0|-O>1|-O1>1|-Ov>100|-ipa>0|-g>0|-no-annotate>0|-save-temps -path-output>0|-ED>0|-no-auto-attrs>0|-no-builtin>0|-no-extra-keywords>0|-enum-is-int>0|-no-fp-associative>0|-structs-do-not-overlap>1|-implicit-pointers>0|-eh >0|-rtti>0|-check-init-order>0|-ignore-std>0|-const-read-write>0|-const-strings>0|-no-multiline>1|-misra>0|-misra-strict>0|-misra-no-cross-module>0|-misra-no-runtime>0|-misra-testing>0|-misra-suppress-advisory>0|-no-std-inc>0|-double-size-32>1|-double-size-any>0|-Ofp>0|-guard-vol-loads>0|-decls-strong>1|-no-saturation>0|-cplbs>0|-sdram>0|-multicore>0|-stack-detect>0|-pguide>0|NOSWITCH>0|-flags-compiler --diag_warning,implicit_func_decl>0|-warn-protos>1|-flags-compiler --diag_warning,call_not_inlined>0|-Wremarks>0|-w>0]]></option>
</tool>
<tool type="Assembler">
<option><![CDATA[|-Version>4.5|-v>0|-g>0|-l>0|-save-temps>0|-sp>0]]></option>
</tool>
<tool type="Linker">
<option><![CDATA[|-Version>5.0|-flags-link -t>0|-flags-link -S>0|-flags-link -s>0|-mem>0|-flags-link -warnonce>0|-map>0|-flags-link -xref>0|-flags-link -save-temps>0|-flags-link -ip>1|-MD>USER_CRT="l502-bf_basiccrt.doj",USE_CACHE,USE_INSTRUCTION_CACHE|-flags-link -e>1|-flags-link -ev>0|-add-debug-libpaths>0|-flags-link -MD__ADI_LIBEH__>0|-multicore>0|-flags-link -MDUSE_CACHE>1|NOSWITCH>1]]></option>
</tool>
<tool type="Archiver">
<option><![CDATA[]]></option>
</tool>
<tool type="Loader">
<option><![CDATA[|-Version>4.5|-b Flash>1|-f BINARY>1|-Width 16>1|-p>0x0|DefaultStart>0|-v>0|-waits >-1|-BaudRate 500k>1|-HoldTime >-1|-pFlag >-1|-zinit>0|-No2Kernel>0|-o2>0|-kb Flash>1|-kf HEX>1|-kWidth 8>1|-kp>0x0|DefaultKernelStart>1|UserKernel>1|-romsplitter>0|split HEX>1|-maskaddr>0]]></option>
</tool>
<tool type="VdkGen">
<option><![CDATA[]]></option>
</tool>
</tools>
</configuration>
</configurations>
<!-- Project folders -->
<folders>
<folder name="Generated Files">
<folders>
<folder name="Startup">
<files>
<file name=".\l502-bf_basiccrt.s">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
</files>
</folder>
<folder name="User Heap">
<files>
<file name=".\l502-bf_heaptab.c">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
</files>
</folder>
</folders>
</folder>
<folder name="Header Files" ext=".h,.hpp,.hxx">
<files>
<file name="..\src\l502_async.h">
</file>
<file name="..\src\l502_bf_cmd_defs.h">
</file>
<file name="..\src\l502_cdefs.h">
</file>
<file name="..\src\l502_cmd.h">
</file>
<file name="..\src\l502_defs.h">
</file>
<file name="..\src\l502_fpga.h">
</file>
<file name="..\src\l502_fpga_regs.h">
</file>
<file name="..\src\l502_global.h">
</file>
<file name="..\src\l502_hdma.h">
</file>
<file name="..\src\l502_params.h">
</file>
<file name="..\src\l502_sport_tx.h">
</file>
<file name="..\src\l502_stream.h">
</file>
<file name="..\src\l502_user_process.h">
</file>
</files>
</folder>
<folder name="Linker Files" ext=".ldf,.dlb">
<files>
<file name=".\l502-bf.ldf">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
</files>
</folder>
<folder name="Source Files" ext=".c,.cpp,.cxx,.asm,.dsp,.s">
<files>
<file name="..\src\l502_async.c">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
<file name="..\src\l502_cmd.c">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
<file name="..\src\l502_fpga.c">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
<file name="..\src\l502_hdma.c">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
<file name="..\src\l502_init.c">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
<file name="..\src\l502_params.c">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
<file name="..\src\l502_sport_tx.c">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
<file name="..\src\l502_stream.c">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
<file name="..\src\l502_tests.c">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
<file name="..\src\l502_user_process.c">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
<file name="..\src\main.c">
<file-configurations>
<file-configuration name="Debug">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Debug</intermediate-dir>
<output-dir>.\Debug</output-dir>
</file-configuration>
<file-configuration name="Release">
<excluded-flag value="no"/>
<build-with-flag value="project"/>
<intermediate-dir>.\Release</intermediate-dir>
<output-dir>.\Release</output-dir>
</file-configuration>
</file-configurations>
</file>
</files>
</folder>
</folders>
<!-- System Builder Components -->
<system-builder-component-tables>
<system-builder-plugin name="">
<system-builder-component name="Select Processor">
<property name="Processor family"><![CDATA[Blackfin]]></property>
</system-builder-component>
</system-builder-plugin>
<system-builder-plugin name="Startup Code Wizard" version="2.0">
<system-builder-component name="Advanced Options">
<property name="Add own event handlers"><![CDATA[True]]></property>
<property name="Include C++ support"><![CDATA[False]]></property>
<property name="Include C/C++ support"><![CDATA[True]]></property>
<property name="Include LDF exceptions support"><![CDATA[False]]></property>
<property name="Main never returns"><![CDATA[True]]></property>
<property name="Search for libraries in the tools installation directory"><![CDATA[True]]></property>
<property name="Using Argv"><![CDATA[False]]></property>
</system-builder-component>
<system-builder-component name="Cache and Memory Protection">
<property name="DCBS"><![CDATA[Unset]]></property>
<property name="Data cache memory configuration"><![CDATA[RAM with no memory protection]]></property>
<property name="Generate support for memory protection"><![CDATA[False]]></property>
<property name="Instruction cache memory configuration"><![CDATA[Instruction cache]]></property>
<property name="Write-back cache"><![CDATA[False]]></property>
<property name="Write-through cache"><![CDATA[False]]></property>
</system-builder-component>
<system-builder-component name="Compiler Instrumented Profiling">
<property name="Enable profiling"><![CDATA[False]]></property>
<property name="Profiling output"><![CDATA[mon.out]]></property>
</system-builder-component>
<system-builder-component name="Configuration">
<property name="Add LDF"><![CDATA[True]]></property>
<property name="Add startup code"><![CDATA[True]]></property>
<property name="LDF template schema"><![CDATA[5.4]]></property>
<property name="Startup code template schema"><![CDATA[3.8]]></property>
</system-builder-component>
<system-builder-component name="Custom system heap settings">
<property name="Absolute size"><![CDATA[]]></property>
<property name="Customize system heap"><![CDATA[True]]></property>
<property name="Memory types"><![CDATA[L1]]></property>
<property name="Minimum size"><![CDATA[7 kB]]></property>
</system-builder-component>
<system-builder-component name="Custom system stack settings">
<property name="Absolute size"><![CDATA[]]></property>
<property name="Customize system stack"><![CDATA[True]]></property>
<property name="Memory types"><![CDATA[L1]]></property>
<property name="Minimum size"><![CDATA[2 kB]]></property>
</system-builder-component>
<system-builder-component name="External memory settings">
<property name="Partition external memory"><![CDATA[None]]></property>
<property name="Size"><![CDATA[32MB]]></property>
<property name="Using external memory"><![CDATA[True]]></property>
</system-builder-component>
<system-builder-component name="Linker Options">
<property name="Search Directory"><![CDATA[]]></property>
</system-builder-component>
<system-builder-component name="Multi-core Selection">
<property name="Core"><![CDATA[Core A]]></property>
</system-builder-component>
<system-builder-component name="PGO">
<property name="Using PGO"><![CDATA[False]]></property>
</system-builder-component>
<system-builder-component name="Processor clock and power settings">
<property name="Clock and power settings"><![CDATA[Optimize for speed]]></property>
<property name="Configure clock and power settings"><![CDATA[False]]></property>
<property name="EZ-KIT"><![CDATA[ADSP-BF537 EZ-KIT]]></property>
</system-builder-component>
<system-builder-component name="Program Running From">
<property name="Internal Memory"><![CDATA[True]]></property>
</system-builder-component>
<system-builder-component name="Project Options">
<property name="Compiler Multicore"><![CDATA[False]]></property>
<property name="Configuration"><![CDATA[Release]]></property>
<property name="Full IO"><![CDATA[False]]></property>
<property name="Intermediate Directory"><![CDATA[.\Release]]></property>
<property name="Link against MT libraries"><![CDATA[False]]></property>
<property name="Linker Multicore"><![CDATA[False]]></property>
<property name="Name"><![CDATA[l502-bf]]></property>
<property name="Processor"><![CDATA[ADSP-BF523]]></property>
<property name="Silicon Revision"><![CDATA[0.2]]></property>
<property name="Strict IEEE Floating Point Compliance"><![CDATA[False]]></property>
<property name="Use C++ exceptions libraries"><![CDATA[False]]></property>
<property name="Utility ROM"><![CDATA[True]]></property>
</system-builder-component>
<system-builder-component name="Run-time Initialization">
<property name="I/O device initialization"><![CDATA[False]]></property>
<property name="Initialize data registers"><![CDATA[False]]></property>
<property name="Initialize return registers to zero"><![CDATA[False]]></property>
<property name="Run-time memory initialization"><![CDATA[False]]></property>
</system-builder-component>
<system-builder-component name="Welcome">
<property name="Enabled"><![CDATA[True]]></property>
</system-builder-component>
</system-builder-plugin>
</system-builder-component-tables>
</visualdsp-project>

497
vdsp/l502-bf.ldf Normal file
View File

@ -0,0 +1,497 @@
/* MANAGED-BY-SYSTEM-BUILDER */
/* VisualDSP++ 5.0 Update 10.1 */
/* LDF Printer version: 5.9.0.1 */
/* ldfgen.exe version: 5.9.0.1 */
/* VDSG version: 5.9.0.1 */
/*
** ADSP-BF523 linker description file generated on Jan 10, 2013 at 19:23:18.
**
** Copyright (C) 2000-2010 Analog Devices Inc., All Rights Reserved.
**
** This file is generated automatically based upon the options selected
** in the LDF Wizard. Changes to the LDF configuration should be made by
** changing the appropriate options rather than editing this file.
**
** Configuration:-
** crt_doj: l502-bf_basiccrt.doj
** processor: ADSP-BF523
** product_name: VisualDSP++ 5.0 Update 10.1
** si_revision: 0.2
** default_silicon_revision_from_archdef: 0.2
** cplb_init_cplb_ctrl: (
** CPLB_ENABLE_ICACHE
** CPLB_ENABLE_ICPLBS
** )
** using_cplusplus: false
** mem_init: false
** use_vdk: false
** use_mt: false
** use_eh: false
** use_argv: false
** running_from_internal_memory: true
** user_heap_src_file: C:\PRJ\L502\builds\lpcie_sdk\release\firmware-conv\l502-bf\vdsp\l502-bf_heaptab.c
** libraries_use_stdlib: true
** libraries_use_fileio_libs: false
** libraries_use_ieeefp_emulation_libs: false
** libraries_use_eh_enabled_libs: false
** libraries_use_fixed_point_io_libs: false
** libraries_use_utility_rom: true
** detect_stackoverflow: false
** system_heap: L1
** system_heap_min_size: 7k
** system_stack: L1
** system_stack_min_size: 2k
** use_sdram: true
** use_sdram_size: 32MB
** use_sdram_partitioned: none
**
*/
ARCHITECTURE(ADSP-BF523)
SEARCH_DIR($ADI_DSP/Blackfin/lib)
// Workarounds are enabled, exceptions are disabled.
#define RT_LIB_NAME(x) lib ## x ## y.dlb
#define RT_LIB_NAME_EH(x) lib ## x ## y.dlb
#define RT_LIB_NAME_MT(x) lib ## x ## y.dlb
#define RT_LIB_NAME_EH_MT(x) lib ## x ## y.dlb
#define RT_OBJ_NAME(x) x ## y.doj
#define RT_OBJ_NAME_MT(x) x ## mty.doj
$LIBRARIES =
/*$VDSG<insert-user-libraries-at-beginning> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-libraries-at-beginning> */
RT_LIB_NAME_MT(small532)
,RT_LIB_NAME_MT(io532)
,RT_LIB_NAME_MT(c532)
,RT_LIB_NAME_MT(event532)
,RT_LIB_NAME(ssl527)
,RT_LIB_NAME(drv527)
,RT_LIB_NAME(usb527)
,RT_LIB_NAME(f64ieee532)
,RT_LIB_NAME(dsp532)
,RT_LIB_NAME(sftflt532)
,RT_LIB_NAME(etsi532)
,RT_LIB_NAME(ftl527)
,RT_OBJ_NAME_MT(idle532)
,RT_LIB_NAME_MT(rt_fileio532)
/*$VDSG<insert-user-libraries-at-end> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-libraries-at-end> */
;
$OBJECTS =
"l502-bf_basiccrt.doj"
/*$VDSG<insert-user-objects-at-beginning> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-objects-at-beginning> */
, RT_LIB_NAME(profile532)
, $COMMAND_LINE_OBJECTS
, "cplbtab523.doj"
/*$VDSG<insert-user-objects-at-end> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-objects-at-end> */
;
$OBJS_LIBS_INTERNAL =
/*$VDSG<insert-libraries-internal> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-internal> */
$OBJECTS{prefersMem("internal")}, $LIBRARIES{prefersMem("internal")}
/*$VDSG<insert-libraries-internal-end> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-internal-end> */
;
$OBJS_LIBS_NOT_EXTERNAL =
/*$VDSG<insert-libraries-not-external> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-not-external> */
$OBJECTS{!prefersMem("external")}, $LIBRARIES{!prefersMem("external")}
/*$VDSG<insert-libraries-not-external-end> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-not-external-end> */
;
/*$VDSG<insert-user-macros> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-macros> */
/*$VDSG<customize-async-macros> */
/* This code is preserved if the LDF is re-generated. */
#define ASYNC0_MEMTYPE RAM
#define ASYNC1_MEMTYPE RAM
#define ASYNC2_MEMTYPE RAM
#define ASYNC3_MEMTYPE RAM
/*$VDSG<customize-async-macros> */
MEMORY
{
/*
** ADSP-BF523 MEMORY MAP.
**
** The known memory spaces are as follows:
**
** 0xFFE00000 - 0xFFFFFFFF Core MMR registers (2MB)
** 0xFFC00000 - 0xFFDFFFFF System MMR registers (2MB)
** 0xFFB01000 - 0xFFBFFFFF Reserved
** 0xFFB00000 - 0xFFB00FFF Scratch SRAM (4K)
** 0xFFA14000 - 0xFFAFFFFF Reserved
** 0xFFA10000 - 0XFFA13FFF Code SRAM/CACHE (16K)
** 0xFFA0C000 - 0xFFA0FFFF Reserved
** 0xFFA08000 - 0xFFA0BFFF Instruction Bank B SRAM (16K)
** 0xFFA00000 - 0xFFA07FFF Instruction Bank A SRAM (32K)
** 0xFF908000 - 0xFF9FFFFF Reserved
** 0xFF904000 - 0xFF907FFF Data Bank B SRAM/CACHE (16K)
** 0xFF900000 - 0XFF903FFF Data Bank B SRAM (16K)
** 0xFF808000 - 0xFF8FFFFF Reserved
** 0xFF804000 - 0xFF807FFF Data Bank A SRAM/CACHE (16K)
** 0xFF800000 - 0XFF803FFF Data Bank A SRAM (16K)
** 0xEF000800 - 0xFF800000 Reserved
** 0xEF000000 - 0xFF8007FF Boot ROM (2K)
** 0x20400000 - 0xEEFFFFFF Reserved
** 0x20300000 - 0x203FFFFF ASYNC MEMORY BANK 3 (1MB)
** 0x20200000 - 0x202FFFFF ASYNC MEMORY BANK 2 (1MB)
** 0x20100000 - 0x201FFFFF ASYNC MEMORY BANK 1 (1MB)
** 0x20000000 - 0x200FFFFF ASYNC MEMORY BANK 0 (1MB)
** 0x00000000 - 0x07FFFFFF SDRAM MEMORY (16MB - 128MB)
**
** Notes:
** 0xFF807FEF-0xFF807FFF
** Required by boot-loader. Used as heap or cache below which is ok. Cannot
** contain initialized data or code.
*/
MEM_L1_SCRATCH { TYPE(RAM) START(0xFFB00000) END(0xFFB00FFF) WIDTH(8) }
MEM_L1_CODE_CACHE { TYPE(RAM) START(0xFFA10000) END(0xFFA13FFF) WIDTH(8) }
MEM_L1_CODE { TYPE(RAM) START(0xFFA00000) END(0xFFA0BFFF) WIDTH(8) }
MEM_L1_DATA_B { TYPE(RAM) START(0xFF900000) END(0xFF907FFF) WIDTH(8) }
MEM_L1_DATA_A { TYPE(RAM) START(0xFF800000) END(0xFF807FFF) WIDTH(8) }
MEM_ASYNC3 { TYPE(ASYNC3_MEMTYPE) START(0x20300000) END(0x203FFFFF) WIDTH(8) }
MEM_ASYNC2 { TYPE(ASYNC2_MEMTYPE) START(0x20200000) END(0x202FFFFF) WIDTH(8) }
MEM_ASYNC1 { TYPE(ASYNC1_MEMTYPE) START(0x20100000) END(0x201FFFFF) WIDTH(8) }
MEM_ASYNC0 { TYPE(ASYNC0_MEMTYPE) START(0x20000000) END(0x200FFFFF) WIDTH(8) }
MEM_SDRAM0 { TYPE(RAM) START(0x00000004) END(0x01ffffff) WIDTH(8) }
/*$VDSG<insert-new-memory-segments> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-new-memory-segments> */
} /* MEMORY */
PROCESSOR p0
{
OUTPUT($COMMAND_LINE_OUTPUT_FILE)
RESOLVE(start, 0xFFA00000)
KEEP(start, _main)
/*$VDSG<insert-user-ldf-commands> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-ldf-commands> */
SECTIONS
{
/* Workaround for hardware errata 05-00-0189 and 05-00-0310 -
** "Speculative (and fetches made at boundary of reserved memory
** space) for instruction or data fetches may cause false
** protection exceptions" and "False hardware errors caused by
** fetches at the boundary of reserved memory ".
**
** Done by avoiding use of 76 bytes from at the end of blocks
** that are adjacent to reserved memory. Workaround is enabled
** for appropriate silicon revisions (-si-revision switch).
*/
RESERVE(___wab0=MEMORY_END(MEM_L1_SCRATCH) - 75, ___l0 = 76)
RESERVE(___wab2=MEMORY_END(MEM_L1_CODE) - 75, ___l2 = 76)
RESERVE(___wab4=MEMORY_END(MEM_L1_DATA_B) - 75, ___l4 = 76)
RESERVE(___wab6=MEMORY_END(MEM_L1_DATA_A) - 75, ___l6 = 76)
RESERVE(___wab7=MEMORY_END(MEM_ASYNC3) - 75, ___l7 = 76)
RESERVE(___wab9=MEMORY_END(MEM_SDRAM0) - 75, ___l9 = 76)
/*$VDSG<insert-new-sections-at-the-start> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-new-sections-at-the-start> */
scratchpad NO_INIT
{
INPUT_SECTION_ALIGN(4)
/*$VDSG<insert-input-sections-at-the-start-of-scratchpad> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-start-of-scratchpad> */
INPUT_SECTIONS($OBJECTS(L1_scratchpad) $LIBRARIES(L1_scratchpad))
/*$VDSG<insert-input-sections-at-the-end-of-scratchpad> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-scratchpad> */
} > MEM_L1_SCRATCH
L1_code
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS($OBJECTS(L1_code) $LIBRARIES(L1_code))
/*$VDSG<insert-input-sections-at-the-start-of-l1_code> */
INPUT_SECTION_ALIGN(64)
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-start-of-l1_code> */
INPUT_SECTIONS($OBJECTS(cplb_code) $LIBRARIES(cplb_code))
INPUT_SECTIONS($OBJECTS(cplb) $LIBRARIES(cplb))
INPUT_SECTIONS($OBJECTS(noncache_code) $LIBRARIES(noncache_code))
INPUT_SECTIONS($OBJS_LIBS_INTERNAL(program))
INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(program))
INPUT_SECTIONS($OBJECTS(program) $LIBRARIES(program))
/*$VDSG<insert-input-sections-at-the-end-of-l1_code> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-l1_code> */
} > MEM_L1_CODE
L1_code_cache
{
INPUT_SECTION_ALIGN(4)
___l1_code_cache = 1;
} > MEM_L1_CODE_CACHE
L1_data_a_tables
{
INPUT_SECTION_ALIGN(4)
FORCE_CONTIGUITY
/*$VDSG<insert-input-sections-at-the-start-of-L1_data_a_tables> */
/* Text inserted between these $VDSG comments will be preserved */
INPUT_SECTION_ALIGN(64)
_startfix_sect = .;
INPUT_SECTIONS($OBJECTS(board_state) $LIBRARIES(board_state))
. = _startfix_sect + 8196;
/*$VDSG<insert-input-sections-at-the-start-of-L1_data_a_tables> */
/*$VDSG<insert-input-sections-in-the-middle-of-L1_data_a_tables> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-in-the-middle-of-L1_data_a_tables> */
/*$VDSG<insert-input-sections-at-the-end-of-L1_data_a_tables> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-L1_data_a_tables> */
} > MEM_L1_DATA_A
L1_data_a_1
{
INPUT_SECTION_ALIGN(4)
___l1_data_cache_a = 0;
INPUT_SECTIONS($OBJECTS(L1_data_a) $LIBRARIES(L1_data_a))
INPUT_SECTIONS($OBJECTS(L1_data) $LIBRARIES(L1_data))
/*$VDSG<insert-input-sections-at-the-start-of-L1_data_a> */
INPUT_SECTION_ALIGN(64)
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-start-of-L1_data_a> */
RESERVE(heaps_and_stack_in_L1_data_a, heaps_and_stack_in_L1_data_a_length = 2048,4)
} > MEM_L1_DATA_A
L1_data_a_bsz ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJECTS(L1_bsz) $LIBRARIES(L1_bsz))
} > MEM_L1_DATA_A
L1_data_a
{
INPUT_SECTION_ALIGN(4)
/*$VDSG<insert-input-sections-in-the-middle-of-L1_data_a> */
INPUT_SECTION_ALIGN(64)
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-in-the-middle-of-L1_data_a> */
INPUT_SECTIONS($OBJECTS(cplb_data) $LIBRARIES(cplb_data))
INPUT_SECTIONS($OBJECTS(voldata) $LIBRARIES(voldata))
INPUT_SECTIONS($OBJS_LIBS_INTERNAL(data1))
INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(data1))
INPUT_SECTIONS($OBJECTS(data1) $LIBRARIES(data1))
INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata))
/*$VDSG<insert-input-sections-at-the-end-of-L1_data_a> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-L1_data_a> */
} > MEM_L1_DATA_A
bsz_L1_data_a ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
/*$VDSG<insert-input-sections-at-the-start-of-bsz_L1_data_a> */
FORCE_CONTIGUITY
INPUT_SECTION_ALIGN(64)
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-start-of-bsz_L1_data_a> */
INPUT_SECTIONS($OBJS_LIBS_INTERNAL(bsz))
INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(bsz))
INPUT_SECTIONS($OBJECTS(bsz) $LIBRARIES(bsz))
/*$VDSG<insert-input-sections-at-the-end-of-bsz_L1_data_a> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-bsz_L1_data_a> */
} > MEM_L1_DATA_A
L1_data_a_stack_heap
{
INPUT_SECTION_ALIGN(4)
RESERVE_EXPAND(heaps_and_stack_in_L1_data_a, heaps_and_stack_in_L1_data_a_length , 0, 4)
ldf_stack_space = heaps_and_stack_in_L1_data_a;
ldf_stack_end = (ldf_stack_space + (heaps_and_stack_in_L1_data_a_length - 4)) & 0xfffffffc;
} > MEM_L1_DATA_A
L1_data_b_bsz ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJECTS(L1_bsz) $LIBRARIES(L1_bsz))
} > MEM_L1_DATA_B
L1_data_b
{
INPUT_SECTION_ALIGN(4)
___l1_data_cache_b = 0;
INPUT_SECTIONS($OBJECTS(L1_data_b) $LIBRARIES(L1_data_b))
INPUT_SECTIONS($OBJECTS(L1_data) $LIBRARIES(L1_data))
/*$VDSG<insert-input-sections-at-the-start-of-L1_data_b> */
INPUT_SECTION_ALIGN(64)
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-start-of-L1_data_b> */
RESERVE(heaps_and_stack_in_L1_data_b, heaps_and_stack_in_L1_data_b_length = 7168,4)
INPUT_SECTIONS($OBJECTS(cplb_data) $LIBRARIES(cplb_data))
INPUT_SECTIONS($OBJECTS(voldata) $LIBRARIES(voldata))
INPUT_SECTIONS($OBJS_LIBS_INTERNAL(data1))
INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(data1))
INPUT_SECTIONS($OBJECTS(data1) $LIBRARIES(data1))
INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata))
/*$VDSG<insert-input-sections-at-the-end-of-L1_data_b> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-L1_data_b> */
} > MEM_L1_DATA_B
bsz_L1_data_b ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
/*$VDSG<insert-input-sections-at-the-start-of-bsz_L1_data_b> */
INPUT_SECTION_ALIGN(64)
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-start-of-bsz_L1_data_b> */
INPUT_SECTIONS($OBJS_LIBS_INTERNAL(bsz))
INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(bsz))
INPUT_SECTIONS($OBJECTS(bsz) $LIBRARIES(bsz))
/*$VDSG<insert-input-sections-at-the-end-of-bsz_L1_data_b> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-bsz_L1_data_b> */
} > MEM_L1_DATA_B
L1_data_b_stack_heap
{
INPUT_SECTION_ALIGN(4)
RESERVE_EXPAND(heaps_and_stack_in_L1_data_b, heaps_and_stack_in_L1_data_b_length , 0, 4)
ldf_heap_space = heaps_and_stack_in_L1_data_b;
ldf_heap_end = (ldf_heap_space + (heaps_and_stack_in_L1_data_b_length - 4)) & 0xfffffffc;
ldf_heap_length = ldf_heap_end - ldf_heap_space;
} > MEM_L1_DATA_B
sdram
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS($OBJECTS(sdram0) $LIBRARIES(sdram0))
INPUT_SECTIONS($OBJECTS(sdram0_bank0) $LIBRARIES(sdram0_bank0))
INPUT_SECTIONS($OBJECTS(sdram0_bank1) $LIBRARIES(sdram0_bank1))
INPUT_SECTIONS($OBJECTS(sdram0_bank2) $LIBRARIES(sdram0_bank2))
INPUT_SECTIONS($OBJECTS(sdram0_bank3) $LIBRARIES(sdram0_bank3))
/*$VDSG<insert-input-sections-at-the-start-of-sdram> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-start-of-sdram> */
INPUT_SECTIONS($OBJECTS(noncache_code) $LIBRARIES(noncache_code))
INPUT_SECTIONS($OBJECTS(program) $LIBRARIES(program))
INPUT_SECTIONS($OBJECTS(cplb) $LIBRARIES(cplb))
INPUT_SECTIONS($OBJECTS(cplb_code) $LIBRARIES(cplb_code))
INPUT_SECTIONS($OBJECTS(data1) $LIBRARIES(data1))
INPUT_SECTIONS($OBJECTS(voldata) $LIBRARIES(voldata))
INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata))
INPUT_SECTIONS($OBJECTS(cplb_data) $LIBRARIES(cplb_data))
/*$VDSG<insert-input-sections-at-the-end-of-sdram> */
INPUT_SECTION_ALIGN(64)
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-input-sections-at-the-end-of-sdram> */
} > MEM_SDRAM0
bsz_sdram0 ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS($OBJECTS(sdram_bsz) $LIBRARIES(sdram_bsz))
INPUT_SECTIONS($OBJECTS(bsz) $LIBRARIES(bsz))
} > MEM_SDRAM0
sdram_stack_heap
{
} > MEM_SDRAM0
/*$VDSG<insert-new-sections-at-the-end> */
/* Text inserted between these $VDSG comments will be preserved */
noinit_sdram0 NO_INIT
{
INPUT_SECTION_ALIGN(64)
INPUT_SECTIONS($OBJECTS(sdram_noinit) $LIBRARIES(sdram_noinit))
} > MEM_SDRAM0
/*$VDSG<insert-new-sections-at-the-end> */
} /* SECTIONS */
} /* p0 */

324
vdsp/l502-bf_basiccrt.s Normal file
View File

@ -0,0 +1,324 @@
/* MANAGED-BY-SYSTEM-BUILDER */
/* VisualDSP++ 5.0 Update 10.1 */
/* CRT Printer version: 5.9.0.1 */
/* crtgen.exe version: 5.9.0.1 */
/* VDSG version: 5.9.0.1 */
/*
** l502-bf_basiccrt.s generated on Oct 22, 2012 at 13:05:29.
**
** Copyright (C) 2000-2010 Analog Devices Inc., All Rights Reserved.
** This contains Analog Devices Background IP and Development IP as
** defined in the ADI/Intel Collaboration Agreement.
**
** This file is generated automatically based upon the options selected
** in the Startup Code Wizard. Changes to the startup configuration
** should be made by changing the appropriate options rather than
** editing this file. Additional user code to be executed before calling
** main can be inserted between the labels .start_of_user_code1 and
** .end_of_user_code1 or .start_of_user_code2 and .end_of_user_code2.
** This code is preserved if the CRT is re-generated.
**
** Configuration:-
** product_name: VisualDSP++ 5.0 Update 10.1
** processor: ADSP-BF523
** si_revision: 0.2
** cplb_init: true
** cplb_ctrl: (
** CPLB_ENABLE_ICACHE
** CPLB_ENABLE_ICPLBS
** )
** mem_init: false
** device_init: false
** init_regs: false
** zero_return_regs: false
** use_profiling: false
** using_cplusplus: false
** use_argv: false
** main_never_returns: true
** use_default_handlers: true
** use_vdk: false
** set_clock_and_power: false
** detect_stackoverflow: false
**
*/
/////////////////////////////////////////////////////////////////
// blackfin-edinburgh-core
#include <sys/platform.h>
#include <sys/anomaly_macros_rtl.h>
/////////////////////////////////////////////////////////////////
// standard
#define IVBh (EVT0 >> 16)
#define IVBl (EVT0 & 0xFFFF)
#define UNASSIGNED_VAL 0x8181
#define INTERRUPT_BITS 0x400 // just IVG15
#define SYSCFG_VALUE 0x30
.section/DOUBLEANY program;
.file_attr requiredForROMBoot;
.align 2;
start:
/*$VDSG<insert-code-very-beginning> */
.start_of_user_code_very_beginning:
// Insert additional code to be executed before any other Startup Code here.
// This code is preserved if the CRT is re-generated.
.end_of_user_code_very_beginning:
/*$VDSG<insert-code-very-beginning> */
/////////////////////////////////////////////////////////////////
// standard
#if WA_05000229
// Avoid Anomaly 05-00-0229: DMA5_CONFIG and SPI_CTL not cleared on reset.
R1 = 0x400;
#if defined(__ADSPBF538__) || defined(__ADSPBF539__)
P0.L = SPI0_CTL & 0xFFFF;
P0.H = SPI0_CTL >> 16;
W[P0] = R1.L;
#else
P0.L = SPI_CTL & 0xFFFF;
P0.H = SPI_CTL >> 16;
W[P0] = R1.L;
#endif
P0.L = DMA5_CONFIG & 0xFFFF;
P0.H = DMA5_CONFIG >> 16;
R1 = 0;
W[P0] = R1.L;
#endif
// Clear loop counters to disable hardware loops
R7 = 0;
LC0 = R7;
LC1 = R7;
// Clear the DAG Length regs, to force linear addressing
L0 = R7;
L1 = R7;
L2 = R7;
L3 = R7;
// Clear ITEST_COMMAND and DTEST_COMMAND registers
I0.L = (ITEST_COMMAND & 0xFFFF);
I0.H = (ITEST_COMMAND >> 16);
I1.L = (DTEST_COMMAND & 0xFFFF);
I1.H = (DTEST_COMMAND >> 16);
[I0] = R7;
[I1] = R7;
CSYNC;
// Initialise the Event Vector table.
P0.H = IVBh;
P0.L = IVBl;
// Install __unknown_exception_occurred in EVT so that
// there is defined behaviour.
P0 += 2*4; // Skip Emulation and Reset
P1 = 13;
R1.L = __unknown_exception_occurred;
R1.H = __unknown_exception_occurred;
LSETUP (.ivt,.ivt) LC0 = P1;
.ivt: [P0++] = R1;
// Set IVG15's handler to be the start of the mode-change
// code. Then, before we return from the Reset back to user
// mode, we'll raise IVG15. This will mean we stay in supervisor
// mode, and continue from the mode-change point, but at a
// much lower priority.
P1.H = supervisor_mode;
P1.L = supervisor_mode;
[P0] = P1;
/////////////////////////////////////////////////////////////////
// cplb-handler
#include "cplb.h"
P1.H = _cplb_hdr;
P1.L = _cplb_hdr;
[P0-48] = P1; // write exception handler
.extern _cplb_hdr;
/////////////////////////////////////////////////////////////////
// standard
// Initialise the stack.
// Note: this points just past the end of the section.
// First write should be with [--SP].
SP.L=ldf_stack_end;
SP.H=ldf_stack_end;
usp = sp;
// We're still in supervisor mode at the moment, so the FP
// needs to point to the supervisor stack.
FP = SP;
// Make space for incoming "parameters" for functions
// we call from here:
SP += -12;
R0 = INTERRUPT_BITS;
R0 <<= 5; // Bits 0-4 not settable.
/////////////////////////////////////////////////////////////////
// install-default-handlers
CALL.X __install_default_handlers;
.extern __install_default_handlers;
.type __install_default_handlers,STT_FUNC;
/////////////////////////////////////////////////////////////////
// standard
R1 = SYSCFG;
R4 = R0; // Save modified list
BITSET(R1,1);
SYSCFG = R1; // Enable the cycle counter
/*$VDSG<insert-code-early-startup> */
.start_of_user_code1:
// Insert additional code to be executed before main here.
// This code is preserved if the CRT is re-generated.
.end_of_user_code1:
/*$VDSG<insert-code-early-startup> */
/////////////////////////////////////////////////////////////////
// cplb-init
// initialise the CPLBs if they're needed. This was not possible
// before we set up the stacks.
R0 = 17; // cplb_ctrl = 17
CALL.X _cplb_init;
.extern _cplb_init;
.type _cplb_init,STT_FUNC;
.section/DOUBLEANY cplb_data;
// Set the CPLB control variable. It's defined in a section that will be
// covered by an installed locked CPLB.
___cplb_ctrl:
.align 4;
.byte4=17;
.global ___cplb_ctrl;
.type ___cplb_ctrl,STT_OBJECT;
.section/DOUBLEANY program;
.align 2;
/////////////////////////////////////////////////////////////////
// standard
// Enable interrupts
STI R4; // Using the mask from default handlers
RAISE 15;
// Move the processor into user mode.
P0.L=still_interrupt_in_ipend;
P0.H=still_interrupt_in_ipend;
RETI=P0;
NOP; // Purely to prevent a stall warning
still_interrupt_in_ipend:
// execute RTI until we've `finished` servicing all
// interrupts of priority higher than IVG15. Normally one
// would expect to only have the reset interrupt in IPEND
// being serviced, but occasionally when debugging this may
// not be the case - if restart is hit when servicing an
// interrupt.
//
// When we clear all bits from IPEND, we'll enter user mode,
// then we'll automatically jump to supervisor_mode to start
// servicing IVG15 (which we will 'service' for the whole
// program, so that the program is in supervisor mode.
// Need to do this to 'finish' servicing the reset interupt.
RTI;
supervisor_mode:
[--SP] = RETI; // re-enables the interrupt system
R0.L = UNASSIGNED_VAL;
R0.H = UNASSIGNED_VAL;
// Push a RETS and Old FP onto the stack, for sanity.
[--SP]=R0;
[--SP]=R0;
// Make sure the FP is sensible.
FP = SP;
// Leave space for incoming "parameters"
SP += -12;
/*$VDSG<insert-code-before-device-initialization> */
.start_of_user_code2:
// Insert additional code to be executed before device initialization here.
// This code is preserved if the CRT is re-generated.
.end_of_user_code2:
/*$VDSG<insert-code-before-device-initialization> */
/*$VDSG<insert-code-before-main-entry> */
.start_of_user_code3:
// Insert additional code to be executed before main here.
// This code is preserved if the CRT is re-generated.
.end_of_user_code3:
/*$VDSG<insert-code-before-main-entry> */
/////////////////////////////////////////////////////////////////
// standard
// Call the application program.
CALL.X _main;
/////////////////////////////////////////////////////////////////
// standard
.start.end: // Required by the linker to know the size of the routine
// that is needed for absolute placement.
.global start;
.type start,STT_FUNC;
.extern _main;
.type _main,STT_FUNC;
.extern ldf_stack_end;
.extern __unknown_exception_occurred;
.type __unknown_exception_occurred,STT_FUNC;
/////////////////////////////////////////////////////////////////
// no-device-initialization
// If File IO support isn't provided, then
// we provide dummy versions of the device-handling
// functions, so that the exception handlers don't rely
// on the file IO library
.section/DOUBLEANY program;
.align 2;
_dev_open:
_dev_close:
_dev_write:
_dev_read:
_dev_seek:
_dev_dup:
#if WA_05000371
/* Avoid anomaly 05-00-0371 by ensuring 4 instructions
** before an RTS.
*/
NOP;
NOP;
NOP;
#endif
R0 = -1;
RTS;
._dev_open.end:
._dev_close.end:
._dev_write.end:
._dev_read.end:
._dev_seek.end:
._dev_dup.end:
.global _dev_open;
.type _dev_open,STT_FUNC;
.global _dev_close;
.type _dev_close,STT_FUNC;
.global _dev_write;
.type _dev_write,STT_FUNC;
.global _dev_read;
.type _dev_read,STT_FUNC;
.global _dev_seek;
.type _dev_seek,STT_FUNC;
.global _dev_dup;
.type _dev_dup,STT_FUNC;

93
vdsp/l502-bf_heaptab.c Normal file
View File

@ -0,0 +1,93 @@
/* MANAGED-BY-SYSTEM-BUILDER */
/* VisualDSP++ 5.0 Update 10.1 */
/* LDF Printer version: 5.9.0.1 */
/* ldfgen.exe version: 5.9.0.1 */
/* VDSG version: 5.9.0.1 */
/*
** User heap source file generated on Oct 22, 2012 at 13:05:29.
**
** Copyright (C) 2000-2010 Analog Devices Inc., All Rights Reserved.
**
** This file is generated automatically based upon the options selected
** in the LDF Wizard. Changes to the LDF configuration should be made by
** changing the appropriate options rather than editing this file.
**
** Configuration:-
** crt_doj: l502-bf_basiccrt.doj
** processor: ADSP-BF523
** product_name: VisualDSP++ 5.0 Update 10.1
** si_revision: 0.2
** default_silicon_revision_from_archdef: 0.2
** cplb_init_cplb_ctrl: 17
** using_cplusplus: false
** mem_init: false
** use_vdk: false
** use_mt: false
** use_eh: false
** use_argv: false
** running_from_internal_memory: true
** user_heap_src_file: C:\PRJ\L502\lpcie_sdk\firmware\l502-bf\vdsp\l502-bf_heaptab.c
** libraries_use_stdlib: true
** libraries_use_fileio_libs: false
** libraries_use_ieeefp_emulation_libs: false
** libraries_use_eh_enabled_libs: false
** libraries_use_fixed_point_io_libs: false
** libraries_use_utility_rom: true
** detect_stackoverflow: false
** system_heap: L1
** system_heap_min_size: 7k
** system_stack: L1
** system_stack_min_size: 2k
** use_sdram: true
** use_sdram_size: 32MB
** use_sdram_partitioned: none
**
*/
#ifdef _MISRA_RULES
#pragma diag(push)
#pragma diag(suppress:misra_rule_1_1)
#pragma diag(suppress:misra_rule_2_2)
#pragma diag(suppress:misra_rule_6_3)
#pragma diag(suppress:misra_rule_8_10)
#pragma diag(suppress:misra_rule_10_1_a)
#pragma diag(suppress:misra_rule_11_3)
#pragma diag(suppress:misra_rule_12_7)
#else
#pragma diag(suppress:1124)
#endif /* _MISRA_RULES */
extern "asm" int ldf_heap_space;
extern "asm" int ldf_heap_length;
struct heap_table_t
{
void *base;
unsigned long length;
long int userid;
};
#pragma file_attr("libData=HeapTable")
#pragma section("constdata")
struct heap_table_t heap_table[2] =
{
{ &ldf_heap_space, (unsigned long) &ldf_heap_length, 0 },
{ 0, 0, 0 }
};
#ifdef _MISRA_RULES
#pragma diag(pop)
#endif /* _MISRA_RULES */

1
vdsp/l502_sdram_noinit.h Normal file
View File

@ -0,0 +1 @@
#pragma section("sdram_noinit", NO_INIT)