ChTheo/E502_ADC_BFfirmware
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

git init of an empty project

Browse Source
This commit is contained in:
Theodor Chikin
2025-06-27 15:12:44 +03:00
commit c73ead2643
76 changed files with 45689 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

723
gcc/bfrom.h Normal file
View File

@ -0,0 +1,723 @@
/* Blackfin on-chip ROM API
*
* Copyright 2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __BFROM_H__
#define __BFROM_H__
#include <stdint.h>
/* Possible syscontrol action flags */
#define SYSCTRL_READ 0x00000000 /* read registers */
#define SYSCTRL_WRITE 0x00000001 /* write registers */
#define SYSCTRL_SYSRESET 0x00000002 /* perform system reset */
#define SYSCTRL_CORERESET 0x00000004 /* perform core reset */
#define SYSCTRL_SOFTRESET 0x00000006 /* perform core and system reset */
#define SYSCTRL_VRCTL 0x00000010 /* read/write VR_CTL register */
#define SYSCTRL_EXTVOLTAGE 0x00000020 /* VDDINT supplied externally */
#define SYSCTRL_INTVOLTAGE 0x00000000 /* VDDINT generated by on-chip regulator */
#define SYSCTRL_OTPVOLTAGE 0x00000040 /* For Factory Purposes Only */
#define SYSCTRL_PLLCTL 0x00000100 /* read/write PLL_CTL register */
#define SYSCTRL_PLLDIV 0x00000200 /* read/write PLL_DIV register */
#define SYSCTRL_LOCKCNT 0x00000400 /* read/write PLL_LOCKCNT register */
#define SYSCTRL_PLLSTAT 0x00000800 /* read/write PLL_STAT register */
#define SYSCTRL_COLDBOOT 0x40000000 /* when called at cold boot */
#define SYSCTRL_PREBOOT 0x80000000 /* when called from preboot */
typedef struct ADI_SYSCTRL_VALUES {
uint16_t uwVrCtl;
uint16_t uwPllCtl;
uint16_t uwPllDiv;
uint16_t uwPllLockCnt;
uint16_t uwPllStat;
} ADI_SYSCTRL_VALUES;
static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)0xEF000038;
/* We need a dedicated function since we need to screw with the stack pointer
* when resetting. The on-chip ROM will save/restore registers on the stack
* when doing a system reset, so the stack cannot be outside of the chip.
*/
__attribute__((__noreturn__))
static inline void bfrom_SoftReset(void *new_stack)
{
while (1)
/*
* We don't declare the SP as clobbered on purpose, since
* it confuses the heck out of the compiler, and this function
* never returns
*/
__asm__ __volatile__(
"sp = %[stack];"
"jump (%[bfrom_syscontrol]);"
: : [bfrom_syscontrol] "p"(bfrom_SysControl),
"q0"(SYSCTRL_SOFTRESET),
"q1"(0),
"q2"(NULL),
[stack] "p"(new_stack)
);
}
/* OTP Functions */
static uint32_t (* const bfrom_OtpCommand)(uint32_t command, uint32_t value) = (void *)0xEF000018;
static uint32_t (* const bfrom_OtpRead)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001A;
static uint32_t (* const bfrom_OtpWrite)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001C;
/* otp command: defines for "command" */
#define OTP_INIT 0x00000001
#define OTP_CLOSE 0x00000002
/* otp read/write: defines for "flags" */
#define OTP_LOWER_HALF 0x00000000 /* select upper/lower 64-bit half (bit 0) */
#define OTP_UPPER_HALF 0x00000001
#define OTP_NO_ECC 0x00000010 /* do not use ECC */
#define OTP_LOCK 0x00000020 /* sets page protection bit for page */
#define OTP_CHECK_FOR_PREV_WRITE 0x00000080
/* ******************************************************************************************* */
/* */
/* Return Codes for OtpCommand, OtpRead and OtpWrite() routines */
/* */
/* ******************************************************************************************* */
/* Error codes */
#define OTP_SUCCESS 0x0000
/* Error Bits */
#define OTP_MASTER_ERROR 0
#define OTP_WRITE_ERROR 1
#define OTP_READ_ERROR 2
#define OTP_ACC_VIO_ERROR 3
#define OTP_DATA_MULT_ERROR 4
#define OTP_ECC_MULT_ERROR 5
#define OTP_PREV_WR_ERROR 6
#define OTP_SB_DEFECT_ERROR 7
/* Warning Bits */
#define OTP_DATA_SB_WARN 8
#define OTP_ECC_SB_WARN 9
/* ******************************************************************************************* */
/* */
/* Boot block header's bit fields */
/* */
/* ******************************************************************************************* */
#define HDRSGN 0xFF000000
#define HDRCHK 0x00FF0000
#define DMACODE 0x0000000F
/* ******************************************************************************************* */
/* */
/* Boot Flags (part of block header's block code field) */
/* */
/* ******************************************************************************************* */
#define BFLAG_FINAL 0x00008000 /* final block in stream */
#define BFLAG_FIRST 0x00004000 /* first block in stream */
#define BFLAG_INDIRECT 0x00002000 /* load data via intermediate buffer */
#define BFLAG_IGNORE 0x00001000 /* ignore block payload */
#define BFLAG_INIT 0x00000800 /* call initcode routine */
#define BFLAG_CALLBACK 0x00000400 /* call callback routine */
#define BFLAG_QUICKBOOT 0x00000200 /* boot block only when BFLAG_WAKEUP=0 */
#define BFLAG_FILL 0x00000100 /* fill memory with 32-bit argument value */
#define BFLAG_AUX 0x00000020 /* load auxiliary header -- reserved */
#define BFLAG_SAVE 0x00000010 /* save block on power down -- reserved */
/* ******************************************************************************************* */
/* */
/* Boot Flags (global flags for pFlag word) */
/* */
/* ******************************************************************************************* */
#define BFLAG_NORESTORE 0x80000000 /* do not restore MMR register when done */
#define BFLAG_RESET 0x40000000 /* issue system reset when done */
#define BFLAG_RETURN 0x20000000 /* issue RTS instead of jumping to EVT1 vector */
#define BFLAG_NEXTDXE 0x10000000 /* parse stream via Next DXE pointer */
#define BFLAG_WAKEUP 0x08000000 /* WURESET bit was a '1', enable quickboot */
#define BFLAG_SLAVE 0x04000000 /* boot mode is a slave mode */
#define BFLAG_PERIPHERAL 0x02000000 /* boot mode is a peripheral mode */
#define BFLAG_NOAUTO 0x01000000 /* skip automatic device detection */
#define BFLAG_ALTERNATE 0x00800000 /* use alternate boot source */
#define BFLAG_FASTREAD 0x00400000 /* use 0xB command in SPI master mode */
#define BFLAG_TYPE 0x00100000 /* device type (number of address bytes) */
#define BFLAG_TYPE1 0x00000000 /* device type (1 SPI/TWI address bytes, Small Page NAND Flash) */
#define BFLAG_TYPE2 0x00100000 /* device type (2 SPI/TWI address bytes, Large Page NAND Flash) */
#define BFLAG_TYPE3 0x00200000 /* device type (3 SPI/TWI address bytes, NAND reserved) */
#define BFLAG_TYPE4 0x00300000 /* device type (4 SPI/TWI address bytes, NAND reserved) */
#define BFLAG_HDRINDIRECT 0x00080000 /* boot block headers via intermediate buffer */
#define BFLAG_HOOK 0x00040000 /* call hook routine after initialization */
#define BFLAG_TEST 0x00020000 /* factory testing */
/* ******************************************************************************************* */
/* */
/* Callback Flags */
/* */
/* ******************************************************************************************* */
#define CBFLAG_FINAL 0x00000008
#define CBFLAG_FIRST 0x00000004
#define CBFLAG_DIRECT 0x00000001
/* ******************************************************************************************* */
/* */
/* Boot ROM Jump Table Entries */
/* */
/* ******************************************************************************************* */
#define BFROM_FINALINIT 0xEF000002
#define BFROM_PDMA 0xEF000004
#define BFROM_MDMA 0xEF000006
#define BFROM_MEMBOOT 0xEF000008
#define BFROM_SPIBOOT 0xEF00000A
#define BFROM_TWIBOOT 0xEF00000C
#define BFROM_OTPBOOT 0xEF00000E
#define BFROM_NANDBOOT 0xEF000010
#define BFROM_SECURE_ENTRY 0xEF000014
#define BFROM_OTP_ECC 0xEF000016
#define BFROM_OTP_COMMAND 0xEF000018
#define BFROM_OTP_READ 0xEF00001A
#define BFROM_OTP_WRITE 0xEF00001C
#define BFROM_ECC_LUTADDR 0xEF00001E
#define BFROM_BOOTKERNEL 0xEF000020
#define BFROM_GETPORT 0xEF000022
#define BFROM_NMI 0xEF000024
#define BFROM_HWERROR 0xEF000026
#define BFROM_EXCEPTION 0xEF000028
#define BFROM_EMUENTRY 0xEF00002A
#define BFROM_CRC32 0xEF000030
#define BFROM_CRC32POLY 0xEF000032
#define BFROM_CRC32CALLBACK 0xEF000034
#define BFROM_CRC32INITCODE 0xEF000036
#define BFROM_SYSCONTROL 0xEF000038
#if defined(__ADSPBF50x__)
#define BFROM_FLASHPROTECT 0xEF00003A
#define BFROM_FLASHPROTECTINITCODE 0xEF00003C
#endif
/* ******************************************************************************************* */
/* */
/* Flags and Argument for BFROM_FLASHPROTECT routine */
/* */
/* ******************************************************************************************* */
#if defined(__ADSPBF50x__)
#define FLASH_LOCK_CONTROL 0x80000000 /* Controls locking of the upper byte of the FLASH_CONTROL register */
#define FLASH_PROTECT_ENABLE 0x20000000 /* Controls the Vpp Flash Protect signal */
#define FLASH_PROTECT_DISABLE 0x10000000 /* Controls the Vpp Flash Protect signal */
#define FLASH_RESET_DISABLE 0x02000000 /* Controls the Flash Reset signal */
#define FLASH_RESET_ENABLE 0x01000000 /* Controls the Flash Reset signal */
#define FLASH_LOCKDOWN_ENABLE 0x00010000 /* Enables the block lockdown feature */
#define FLASH_LOCKDOWN_START_BLOCK 0x000000FF /* Block number to start the lockdown */
#define FLASH_LOCKDOWN_NUM_BLOCKS 0x0000FF00 /* Number of block to lockdown */
#define FLASH_BLOCK_SHIFT_VAL 0x00000010 /* shift value for FLASH_LOCKDOWN_START_BLOCK to generate the byte address */
#define FLASH_MAIN_BLOCK_SIZE 0x00010000 /* Size in bytes of a main block */
#endif
/* ******************************************************************************************* */
/* */
/* Boot ROM Data Constants with Bit Fields */
/* */
/* ******************************************************************************************* */
#define BK_REVISION 0xEF000040
#define BK_ZEROS 0xEF000048
#define BK_ONES 0xEF00004C
#define BK_DATECODE 0xEF000050
#if defined (_LANGUAGE_C)
# define pBK_REVISION ((const unsigned long *)BK_REVISION)
# define pBK_ZEROS ((const unsigned long *)BK_ZEROS)
# define pBK_ONES ((const unsigned long *)BK_ONES)
# define pBK_DATECODE ((const unsigned long *)BK_DATECODE)
#endif /* _LANGUAGE_C */
#define BK_ID 0xFF000000
#define BK_PROJECT 0x00FF0000
#define BK_VERSION 0x0000FF00
#define BK_UPDATE 0x000000FF
#define BK_YEAR 0xFFFF0000
#define BK_MONTH 0x0000FF00
#define BK_DAY 0x000000FF
/* ******************************************************************************************* */
/* */
/* Predefined OTP Pages to be used with bfrom_OtpRead() */
/* */
/* ******************************************************************************************* */
#define FPS00 0x0004
#define FPS01 0x0005
#define FPS02 0x0006
#define FPS03 0x0007
#define FPS04 0x0008
#define FPS05 0x0009
#define FPS06 0x000A
#define FPS07 0x000B
#define FPS08 0x000C
#define FPS09 0x000D
#define FPS10 0x000E
#define FPS11 0x000F
#define CPS00 0x0010
#define CPS01 0x0011
#define CPS02 0x0012
#define CPS03 0x0013
#define CPS04 0x0014
#define CPS05 0x0015
#define CPS06 0x0016
#define CPS07 0x0017
#define PBS00 0x0018
#define PBS01 0x0019
#define PBS02 0x001A
#define PBS03 0x001B
/* ******************************************************************************************* */
/* */
/* Bit Fields in OTP Half Page PBS00L */
/* */
/* ******************************************************************************************* */
#define OTP_VR_CTL_P 0
#define OTP_VR_CTL_M 0x0000FFFF /* lower 32-bit word */
#define OTP_PLL_CTL_P 16
#define OTP_PLL_CTL_M 0xFFFF0000 /* lower 32-bit word */
#define OTP_PLL_DIV_P 32
#define OTP_PLL_DIV_M 0x000000FF /* upper 32-bit word */
#define OTP_SPI_BAUD_P 40
#define OTP_SPI_BAUD_M 0x00000700 /* upper 32-bit word */
#define OTP_SPI_FASTREAD_P 43
#define OTP_SPI_FASTREAD_M 0x00000800 /* upper 32-bit word */
#define OTP_TWI_CLKDIV_P 44
#define OTP_TWI_CLKDIV_M 0x00001000 /* upper 32-bit word */
#define OTP_TWI_PRESCALE_P 45
#define OTP_TWI_PRESCALE_M 0x0000E000 /* upper 32-bit word */
#define OTP_TWI_TYPE_P 48
#define OTP_TWI_TYPE_M 0x00030000 /* upper 32-bit word */
#define OTP_SET_PLL_P 50
#define OTP_SET_PLL_M 0x00040000 /* upper 32-bit word */
#define OTP_SET_VR_P 51
#define OTP_SET_VR_M 0x00080000 /* upper 32-bit word */
#define OTP_RESETOUT_HWAIT_P 52
#define OTP_RESETOUT_HWAIT_M 0x00100000 /* upper 32-bit word */
#if defined(__ADSPBF54x__)
#define OTP_ALTERNATE_HWAIT_P 53
#define OTP_ALTERNATE_HWAIT_M 0x00200000 /* upper 32-bit word */
/* bit 54 reserved */
#elif defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
/* bits 53 to 54 reserved */
#endif
#define OTP_LOAD_PBS00H_P 55
#define OTP_LOAD_PBS00H_M 0x00800000 /* upper 32-bit word */
#define OTP_LOAD_PBS01L_P 56
#define OTP_LOAD_PBS01L_M 0x01000000 /* upper 32-bit word */
#define OTP_LOAD_PBS01H_P 57
#define OTP_LOAD_PBS01H_M 0x02000000 /* upper 32-bit word */
#define OTP_LOAD_PBS02L_P 58
#define OTP_LOAD_PBS02L_M 0x04000000 /* upper 32-bit word */
#define OTP_LOAD_PBS02H_P 59
#define OTP_LOAD_PBS02H_M 0x08000000 /* upper 32-bit word */
#define OTP_LOAD_PBS03L_P 60
#define OTP_LOAD_PBS03L_M 0x10000000 /* upper 32-bit word */
#define OTP_LOAD_PBS03H_P 61
#define OTP_LOAD_PBS03H_M 0x20000000 /* upper 32-bit word */
#define OTP_INVALID_P 62
#define OTP_INVALID_M 0xC0000000 /* upper 32-bit word */
/* ******************************************************************************************* */
/* */
/* Bit Fields in OTP Half Page PBS00H */
/* */
/* ******************************************************************************************* */
#define OTP_EBIU_AMBCTL_P 0
#define OTP_EBIU_AMBCTL_M 0x0000FFFF /* lower 32-bit word */
#if defined(__ADSPBF54x__)
#define OTP_EBIU_FCTL_P 16
#define OTP_EBIU_FCTL_M 0xFFFF0000 /* lower 32-bit word */
#define OTP_EBIU_MODE_P 32
#define OTP_EBIU_MODE_M 0x000000FF /* upper 32-bit word */
#elif defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
/* bits 16 to 39 reserved */
#endif
#define OTP_EBIU_AMG_P 40
#define OTP_EBIU_AMG_M 0x00000F00 /* upper 32-bit word */
#if defined(__ADSPBF54x__)
#define OTP_EBIU_DEVSEQ_P 44
#define OTP_EBIU_DEVSEQ_M 0x0000F000 /* upper 32-bit word */
#define OTP_EBIU_DEVCFG_P 48
#define OTP_EBIU_DEVCFG_M 0xFFFF0000 /* upper 32-bit word */
#elif defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
/* bits 16 to 63 reserved */
#endif
/* ******************************************************************************************* */
/* */
/* Bit Fields in OTP Half Page PBS01L */
/* */
/* ******************************************************************************************* */
/* bits 0 to 63 reserved */
/* ******************************************************************************************* */
/* */
/* Bit Fields in OTP Half Page PBS01H */
/* */
/* ******************************************************************************************* */
#define OTP_BMODE00_DIS_P 0
#define OTP_BMODE00_DIS_M 0x00000001 /* lower 32-bit word */
#define OTP_BMODE01_DIS_P 1
#define OTP_BMODE01_DIS_M 0x00000002 /* lower 32-bit word */
#define OTP_BMODE02_DIS_P 2
#define OTP_BMODE02_DIS_M 0x00000004 /* lower 32-bit word */
#define OTP_BMODE03_DIS_P 3
#define OTP_BMODE03_DIS_M 0x00000008 /* lower 32-bit word */
#define OTP_BMODE04_DIS_P 4
#define OTP_BMODE04_DIS_M 0x00000010 /* lower 32-bit word */
#define OTP_BMODE05_DIS_P 5
#define OTP_BMODE05_DIS_M 0x00000020 /* lower 32-bit word */
#define OTP_BMODE06_DIS_P 6
#define OTP_BMODE06_DIS_M 0x00000040 /* lower 32-bit word */
#define OTP_BMODE07_DIS_P 7
#define OTP_BMODE07_DIS_M 0x00000080 /* lower 32-bit word */
#define OTP_BMODE08_DIS_P 8
#define OTP_BMODE08_DIS_M 0x00000100 /* lower 32-bit word */
#define OTP_BMODE09_DIS_P 9
#define OTP_BMODE09_DIS_M 0x00000200 /* lower 32-bit word */
#define OTP_BMODE10_DIS_P 10
#define OTP_BMODE10_DIS_M 0x00000400 /* lower 32-bit word */
#define OTP_BMODE11_DIS_P 11
#define OTP_BMODE11_DIS_M 0x00000800 /* lower 32-bit word */
#define OTP_BMODE12_DIS_P 12
#define OTP_BMODE12_DIS_M 0x00001000 /* lower 32-bit word */
#define OTP_BMODE13_DIS_P 13
#define OTP_BMODE13_DIS_M 0x00002000 /* lower 32-bit word */
#define OTP_BMODE14_DIS_P 14
#define OTP_BMODE14_DIS_M 0x00004000 /* lower 32-bit word */
#define OTP_BMODE15_DIS_P 15
#define OTP_BMODE15_DIS_M 0x00008000 /* lower 32-bit word */
#define OTP_NFC_CTL_P 16
#define OTP_NFC_CTL_M 0x00FF0000 /* lower 32-bit word */
#define OTP_START_PAGE_P 24
#define OTP_START_PAGE_M 0xFF000000 /* lower 32-bit word */
/* bits 32 to 63 reserved */
/* ******************************************************************************************* */
/* */
/* Bit Fields in OTP Half Page PBS02L */
/* */
/* ******************************************************************************************* */
#if defined(__ADSPBF54x__)
#define OTP_EBIU_DDRCTL0_P 0
#define OTP_EBIU_DDRCTL0_M 0xFFFFFFFF /* lower 32-bit word */
#define OTP_EBIU_DDRCTL1_P 32
#define OTP_EBIU_DDRCTL1_M 0xFFFFFFFF /* upper 32-bit word */
#elif defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
#define OTP_EBIU_SDGCTL_P 0
#define OTP_EBIU_SDGCTL_M 0xFFFFFFFF /* lower 32-bit word */
#define OTP_EBIU_SDBCTL_P 32
#define OTP_EBIU_SDBCTL_M 0x0000FFFF /* upper 32-bit word */
#define OTP_EBIU_SDRCC_P 48
#define OTP_EBIU_SDRCC_M 0x0FFF0000 /* upper 32-bit word */
/* bits 60 to 62 reserved */
#define OTP_EBIU_POWERON_DUMMY_WRITE_P 63
#define OTP_EBIU_POWERON_DUMMY_WRITE_M 0x80000000 /* upper 32-bit word */
#endif
/* ******************************************************************************************* */
/* */
/* Bit Fields in OTP Half Page PBS02H */
/* */
/* ******************************************************************************************* */
#if defined(__ADSPBF54x__)
#define OTP_EBIU_DDRCTL2L_P 0
#define OTP_EBIU_DDRCTL2L_M 0x0000FFFF /* lower 32-bit word */
#define OTP_EBIU_DDRCTL3L_P 16
#define OTP_EBIU_DDRCTL3L_M 0xFFFF0000 /* lower 32-bit word */
#define OTP_EBIU_DDRQUEL_P 32
#define OTP_EBIU_DDRQUEL_M 0x0000FFFF /* upper 32-bit word */
/* bits 48 to 63 reserved */
#elif defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
/* bits 0 to 63 reserved */
#endif
/* ******************************************************************************************* */
/* */
/* Bit Fields in OTP Half Page PBS03L */
/* */
/* ******************************************************************************************* */
/* bits 0 to 63 reserved */
/* ******************************************************************************************* */
/* */
/* Bit Fields in OTP Half Page PBS03H */
/* */
/* ******************************************************************************************* */
/* bits 0 to 63 reserved */
/* ******************************************************************************************* */
/* */
/* Macros to be used along with _P versions of above bit fields */
/* */
/* ******************************************************************************************* */
#define OTP_OFFSET(x) (((x)>>5)<<2)
#define OTP_BITPOS(x) ((x)&0x1F)
/* ******************************************************************************************* */
/* */
/* Block Cipher Modes of Operation */
/* */
/* ******************************************************************************************* */
#define BLOCK_CIPHER_MODE_ECB 0
#define BLOCK_CIPHER_MODE_CBC 1
#define BLOCK_CIPHER_MODE_OFB 2
#define BLOCK_CIPHER_MODE_CTR 3
/* ******************************************************************************************* */
/* */
/* Flags for AesInit() routines */
/* */
/* ******************************************************************************************* */
#define AES_ENCRYPTION (0x01)
#define AES_DECRYPTION (0x02)
#define AES_BOTH (AES_ENCRYPTION | AES_DECRYPTION)
/* ******************************************************************************************* */
/* */
/* Return Codes for AES routines */
/* */
/* ******************************************************************************************* */
#define AES_SUCCESS 0
#define AES_INVALID_KEY_SIZE -1
#define AES_INVALID_MODE -2
/* ******************************************************************************************* */
/* */
/* Size definitions used in SHA-1 */
/* */
/* ******************************************************************************************* */
#define SHA1_SCRATCH_BUFFER_SIZE 184
#define SHA1_HASH_SIZE 20
/* ******************************************************************************************* */
/* */
/* Instruction ROM Jump Table Entries */
/* */
/* ******************************************************************************************* */
#if defined(__ADSPBF54x__)
#if defined(__SILICON_REVISION__) && (__SILICON_REVISION__==0x1)
#define BFROM_ARC4_INIT 0xFFA14018
#define BFROM_ARC4_CIPHER 0xFFA1401C
#define BFROM_AES_CIPHER 0xFFA14020
#define BFROM_AES_INV_CIPHER 0xFFA14024
#define BFROM_AES_INIT 0xFFA14028
#define BFROM_AES_KEYEXP 0xFFA1402C
#define BFROM_AES_INV_KEYEXP 0xFFA14030
#define BFROM_SHA1_INIT 0xFFA14860
#define BFROM_SHA1_HASH 0xFFA14B6C
#elif defined(__SILICON_REVISION__) && ((__SILICON_REVISION__==0x2) || (__SILICON_REVISION__==0x3) || (__SILICON_REVISION__==0x4))
#define BFROM_ARC4_INIT 0xFFA14018
#define BFROM_ARC4_CIPHER 0xFFA1401C
#define BFROM_AES_CIPHER 0xFFA14020
#define BFROM_AES_INV_CIPHER 0xFFA14024
#define BFROM_AES_INIT 0xFFA14028
#define BFROM_AES_KEYEXP 0xFFA1402C
#define BFROM_AES_INV_KEYEXP 0xFFA14030
#define BFROM_SHA1_INIT 0xFFA14990
#define BFROM_SHA1_HASH 0xFFA14C9C
#else
#define BFROM_ARC4_INIT __arc4_init
#define BFROM_ARC4_CIPHER __arc4_cipher
#define BFROM_AES_CIPHER __aes_cipher
#define BFROM_AES_INV_CIPHER __aes_inv_cipher
#define BFROM_AES_INIT __aes_init
#define BFROM_AES_KEYEXP __aes_keyexp
#define BFROM_AES_INV_KEYEXP __aes_inv_keyexp
#define BFROM_SHA1_INIT __sha1_init
#define BFROM_SHA1_HASH __sha1_hash
#endif /* __SILICON_REVISION__ */
#elif defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
#if defined(__SILICON_REVISION__) && (__SILICON_REVISION__==0x1)
#define BFROM_SHA1_INIT 0xEF001748
#define BFROM_SHA1_HASH 0xEF001A54
#elif defined(__SILICON_REVISION__) && (__SILICON_REVISION__==0x2)
#define BFROM_SHA1_INIT 0xEF001878
#define BFROM_SHA1_HASH 0xEF001B84
#else
#define BFROM_SHA1_INIT __sha1_init
#define BFROM_SHA1_HASH __sha1_hash
#endif /* __SILICON_REVISION__ */
#elif defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
#if defined(__SILICON_REVISION__) && (__SILICON_REVISION__==0x0)
#define BFROM_SHA1_INIT 0xEF001748
#define BFROM_SHA1_HASH 0xEF001A54
#elif defined(__SILICON_REVISION__) && ((__SILICON_REVISION__==0x1) || (__SILICON_REVISION__==0x2))
#define BFROM_SHA1_INIT 0xEF001878
#define BFROM_SHA1_HASH 0xEF001B84
#else
#define BFROM_SHA1_INIT __sha1_init
#define BFROM_SHA1_HASH __sha1_hash
#endif /* __SILICON_REVISION__ */
#elif defined(__ADSPBF51x__)
#if defined(__SILICON_REVISION__) && ((__SILICON_REVISION__==0x0) || (__SILICON_REVISION__==0x1) || (__SILICON_REVISION__==0x2))
#define BFROM_SHA1_INIT 0xEF001878
#define BFROM_SHA1_HASH 0xEF001B84
#else
#define BFROM_SHA1_INIT __sha1_init
#define BFROM_SHA1_HASH __sha1_hash
#endif /* __SILICON_REVISION__ */
#endif /* __ADSPBF5xx__ */
#endif

2
gcc/ice-100b.rules Normal file
View File

@ -0,0 +1,2 @@
SUBSYSTEM=="usb", ATTRS{idVendor}=="064b", ATTRS{idProduct}=="0225", MODE="0666"
SUBSYSTEM=="usb", ATTRS{idVendor}=="064b", ATTRS{idProduct}=="1225", MODE="0666"

59
gcc/l502-bf Debug.launch Normal file
View File

@ -0,0 +1,59 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<launchConfiguration type="gdb.app.elf.launchConfigurationType">
<stringAttribute key="bad_container_name" value="/gcc/l502-bf"/>
<stringAttribute key="com.analog.gnu.debug.ui.views.mmr.processor" value="ADSP-BF523"/>
<listAttribute key="com.analog.gnu.debug.ui.views.mmr.tables">
<listEntry value="System Interrupt Controller Register File"/>
<listEntry value="SIC_IMASK0"/>
<listEntry value="###"/>
</listAttribute>
<intAttribute key="com.analog.gnu.debug.ui.views.mmr.viewBase" value="16"/>
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="3"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="set remotetimeout 300"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2000"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="bfin-elf-gdb"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="bfin-elf-gdb"/>
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList&gt;&lt;content id=&quot;null-stream_proc-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;flags-out_lb-hdma-null-l502_cmd_check_req-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;null-register_handler-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;null-l502_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;sah-f_descrs[0]-null-isr_sport_dma_tx-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;sah-f_descrs[6]-null-isr_sport_dma_tx-(format)&quot; val=&quot;4&quot;/&gt;&lt;/contentList&gt;"/>
<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;globalVariableList/&gt;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList&gt;&#10;&lt;memoryBlockExpressionItem&gt;&#10;&lt;expression text=&quot;0xc3500&quot;/&gt;&#10;&lt;/memoryBlockExpressionItem&gt;&#10;&lt;/memoryBlockExpressionList&gt;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="build/debug/bin/l502-bf.elf"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="l502-bf"/>
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/l502-bf"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
</listAttribute>
</launchConfiguration>

278
gcc/l502-bf.ld Normal file
View File

@ -0,0 +1,278 @@
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0xc000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_SDRAM : ORIGIN = 0x00000000, LENGTH = 32 * 1024 * 1024
}
/* The default linker script, for single core blackfin standalone executables */
OUTPUT_FORMAT("elf32-bfin", "elf32-bfin", "elf32-bfin")
OUTPUT_ARCH(bfin)
ENTRY(__start)
SECTIONS
{
/* Read-only sections, merged into text segment: */
PROVIDE (__executable_start = SEGMENT_START("text-segment", 0x0)); . = SEGMENT_START("text-segment", 0x0);
.interp : { *(.interp) }
.note.gnu.build-id : { *(.note.gnu.build-id) }
.hash : { *(.hash) }
.gnu.hash : { *(.gnu.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.gnu.version : { *(.gnu.version) }
.gnu.version_d : { *(.gnu.version_d) }
.gnu.version_r : { *(.gnu.version_r) }
.rel.init : { *(.rel.init) }
.rela.init : { *(.rela.init) }
.rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) }
.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
.rel.fini : { *(.rel.fini) }
.rela.fini : { *(.rela.fini) }
.rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) }
.rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) }
.rel.data.rel.ro : { *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*) }
.rela.data.rel.ro : { *(.rela.data.rel.ro* .rela.gnu.linkonce.d.rel.ro.*) }
.rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) }
.rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) }
.rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) }
.rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) }
.rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) }
.rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.sdata : { *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) }
.rela.sdata : { *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) }
.rel.sbss : { *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) }
.rela.sbss : { *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) }
.rel.sdata2 : { *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) }
.rela.sdata2 : { *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) }
.rel.sbss2 : { *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) }
.rela.sbss2 : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) }
.rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) }
.rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }
.rel.iplt :
{
PROVIDE_HIDDEN (___rel_iplt_start = .);
*(.rel.iplt)
PROVIDE_HIDDEN (___rel_iplt_end = .);
}
.rela.iplt :
{
PROVIDE_HIDDEN (___rela_iplt_start = .);
*(.rela.iplt)
PROVIDE_HIDDEN (___rela_iplt_end = .);
}
.rel.plt :
{
*(.rel.plt)
}
.rela.plt :
{
*(.rela.plt)
}
.init :
{
KEEP (*(.init))
KEEP (*basiccrt*(.text .text.*))
} >MEM_L1_CODE =0
.plt : { *(.plt) }
.iplt : { *(.iplt) }
.text :
{
*(.text.unlikely .text.*_unlikely)
*(.text.exit .text.exit.*)
*(.text.startup .text.startup.*)
*(.text.hot .text.hot.*)
*(.text .stub .text.* .gnu.linkonce.t.*)
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
. = ALIGN( 64 );
} >MEM_L1_CODE
.fini :
{
KEEP (*(.fini))
} >MEM_L1_CODE
. = ALIGN( 64 );
PROVIDE (___etext = .);
PROVIDE (__etext = .);
PROVIDE (_etext = .);
.board_state :
{
_startfix_sect = .;
KEEP(*(board_state .board_state .board_state.*))
. = _startfix_sect + 8196;
} >MEM_L1_DATA_A
.rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } > MEM_L1_DATA_A
.rodata1 : { *(.rodata1) }
.sdata2 :
{
*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
}
.sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }
.eh_frame_hdr : { *(.eh_frame_hdr) } > MEM_L1_DATA_A
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > MEM_L1_DATA_A
.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. */
. = ALIGN(CONSTANT (MAXPAGESIZE)) + (. & (CONSTANT (MAXPAGESIZE) - 1));
/* Exception handling */
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) }
.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }
/* Thread Local Storage sections */
.tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) }
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
.preinit_array :
{
PROVIDE_HIDDEN (___preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (___preinit_array_end = .);
}
.init_array :
{
PROVIDE_HIDDEN (___init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE_HIDDEN (___init_array_end = .);
}
.fini_array :
{
PROVIDE_HIDDEN (___fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
PROVIDE_HIDDEN (___fini_array_end = .);
}
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} > MEM_L1_DATA_A
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} > MEM_L1_DATA_A
.jcr : { KEEP (*(.jcr)) } > MEM_L1_DATA_A
.data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*) }
.dynamic : { *(.dynamic) }
.data :
{
*(.data .data.* .gnu.linkonce.d.*)
SORT(CONSTRUCTORS)
. = ALIGN( 64 );
} > MEM_L1_DATA_A
.data1 : { *(.data1) }
.got : { *(.got.plt) *(.igot.plt) *(.got) *(.igot) }
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
.sdata :
{
*(.sdata .sdata.* .gnu.linkonce.s.*)
}
__edata = .; PROVIDE (_edata = .);
___bss_start = .;
.sbss :
{
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
}
.bss :
{
__bss_start = .;
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections.
FIXME: Why do we need it? When there is no .bss section, we don't
pad the .data section. */
. = ALIGN( 64 );
__bss_end = .;
} > MEM_L1_DATA_A
. = ALIGN( 64 );
__end = .; PROVIDE (_end = .);
.sdram_noinit (NOLOAD) :
{
*(.sdram_noinit, .sdram_noinit.*)
} > MEM_SDRAM
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo .zdebug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames .zdebug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges .zdebug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames .zdebug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.* .zdebug_info) }
.debug_abbrev 0 : { *(.debug_abbrev .zdebug_abbrev) }
.debug_line 0 : { *(.debug_line .zdebug_line) }
.debug_frame 0 : { *(.debug_frame .zdebug_frame) }
.debug_str 0 : { *(.debug_str .zdebug_str) }
.debug_loc 0 : { *(.debug_loc .zdebug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo .zdebug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames .zdebug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames .zdebug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames .zdebug_typenames) }
.debug_varnames 0 : { *(.debug_varnames .zdebug_varnames) }
/* DWARF 3 */
.debug_pubtypes 0 : { *(.debug_pubtypes .zdebug_pubtypes) }
.debug_ranges 0 : { *(.debug_ranges .zdebug_ranges) }
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
__end = .; PROVIDE (_end = .);
__stack_start = ORIGIN(MEM_L1_SCRATCH);
__stack_end = ORIGIN(MEM_L1_SCRATCH) + 0x1000;
}

78
gcc/l502-bf_basiccrt.s Normal file
View File

@ -0,0 +1,78 @@
#include <sys/platform.h>
#include <cplb.h>
#include <sys/anomaly_macros_rtl.h>
#include <defBF533.h>
#include <def_LPBlackfin.h>
.text;
.align 2;
.global __start;
.extern _main;
.type __start, STT_FUNC;
__start:
R7 = 0;
LC0 = R7;
LC1 = R7;
L0 = R7;
L1 = R7;
L2 = R7;
L3 = R7;
I0.L = (ITEST_COMMAND & 0xFFFF);
I0.H = (ITEST_COMMAND >> 16);
I1.L = (DTEST_COMMAND & 0xFFFF);
I1.H = (DTEST_COMMAND >> 16);
R7 = 0;
[I0] = R7;
[I1] = R7;
CSYNC;
SP.L=__stack_end - 12;
SP.H=__stack_end - 12;
FP = SP;
SP += -12;
// Zero bss memory
R0.L = __bss_start;
R0.H = __bss_start;
R1.L = __bss_end;
R1.H = __bss_end;
R2 = R1 - R0;
R1 = 0;
CALL.X _memset;
///////////////from PRM/////////////////////////////////////
P0.L = (EVT15 & 0xFFFF) ; /* Point to IVG15 in Event Vector Table */
P0.H = ((EVT15 >> 16) & 0xFFFF) ;
P1.L = START; /* Point to start of User code */
P1.H = START;
[P0] = P1 ; /* Place the address of START in IVG15 of EVT */
P0.L = (IMASK & 0xFFFF) ;
R0 = [P0] ;
R1.L = (EVT_IVG15 & 0xFFFF) ;
R0 = R0 | R1 ;
[P0] = R0 ; /* Set (enable) IVG15 bit in IMASK register */
RAISE 15 ; /* Invoke IVG15 interrupt */
P0.L = WAIT_HERE ;
P0.H = WAIT_HERE ;
RETI = P0 ; /* RETI loaded with return address */
RTI ; /* Return from Reset Event */
WAIT_HERE : /* Wait here till IVG15 interrupt is serviced */
JUMP WAIT_HERE ;
START: /* IVG15 vectors here */
/* Enables interrupts and saves return address to stack */
[--SP] = RETI ;
///////////////from PRM/////////////////////////////////////
[--SP]=R0;
[--SP]=R0;
FP = SP;
SP += -12;
CALL.X _main;
NOP;
__end:
IDLE;
JUMP __end;

1
gcc/l502_sdram_noinit.h Normal file
View File

@ -0,0 +1 @@
__attribute__((section(".sdram_noinit")))