firmware is working and compiling! modified cmd L502_BF_CMD_CODE_GET_PARAM (aka f_cmd_get_param()). Added param 87, which returns specific number 0xADEF (decimal 44527).
This commit is contained in:
@ -22,27 +22,27 @@ void l502_stream_init(void);
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#define L502_PLL_CTL (SET_MSEL(53) | DF)
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#define L502_PLL_DIV (SET_SSEL(4) | CSEL_DIV1)
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/* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> SDRAM
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* RDIV=((117964,8*64ms)/8192)-(6+3)=912 // <EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> 8192, <EFBFBD> 4096, <EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1834
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/* конфигурим SDRAM
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* RDIV=((117964,8*64ms)/8192)-(6+3)=912 // по логике - это последняя конфигурация
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* кстати - возможно не 8192, а 4096, в таком случае 1834
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*/
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#define L502_SDRAM_SDRRC (((132500000 / 1000) * 64) / 8192 - (6 + 3))
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/* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 32 <EFBFBD><EFBFBD>, 9 <EFBFBD><EFBFBD><EFBFBD> - <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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/* размер памяти - 32 Мб, 9 бит - под адрес колонки */
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#define L502_SDRAM_SDBCTL (EBE | EBSZ_32 | EBCAW_9)
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/* CAS latency=3, <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> <20> 2 - <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>!!!!)
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* PASR_ALL - <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD> SDRAM <EFBFBD> 2.5 <EFBFBD> - <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>
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* tRAS(min)=45 <EFBFBD><EFBFBD> (<28><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 120 <EFBFBD><EFBFBD><EFBFBD> - 6 <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
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* tRP(min)=20 <EFBFBD><EFBFBD> (<28><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 120 <EFBFBD><EFBFBD><EFBFBD> - 3 <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
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* tRCD(min)=20 <EFBFBD><EFBFBD> (<28><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 120 <EFBFBD><EFBFBD><EFBFBD> - 3 <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
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* tWR - <EFBFBD><EFBFBD>, <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 2
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* POWER startup delay - <EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>
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* PSS - power SDRAM - <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
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* SRFS - <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> SDRAM <20> <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 0 <20><> <20><><EFBFBD><EFBFBD><EFBFBD>
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* EBUFE=0 - <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD> SDRAM
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* FBBRW=0 - <EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>
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* EMREN=0 - <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD> SDRAM <EFBFBD> 2.5 <EFBFBD> - <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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* TCSR=0 - <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD> SDRAM <EFBFBD> 2.5 <EFBFBD> - <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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* CDDBG=0 - <EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> signals <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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/* CAS latency=3, хотя можно и 2 - чем меньше тем лучше (правда при этом глюки появляются!!!!)
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* PASR_ALL - тоже для SDRAM с 2.5 В - экономия энергии, поэтому рефрешим все
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* tRAS(min)=45 нс (при частоте 120 Мгц - 6 тактов)
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* tRP(min)=20 нс (при частоте 120 Мгц - 3 тактов)
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* tRCD(min)=20 нс (при частоте 120 Мгц - 3 тактов)
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* tWR - хз, на вскидку 2
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* POWER startup delay - не нужна
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* PSS - power SDRAM - должно быть
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* SRFS - нужна для перевода SDRAM в режим пониженного энергопотребления 0 не нужно
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* EBUFE=0 - только один чип SDRAM
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* FBBRW=0 - для того, чтобы чтение сразу шло за записью, может не работать - попробовать позже
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* EMREN=0 - тоже для SDRAM с 2.5 В - экономия энергии
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* TCSR=0 - тоже для SDRAM с 2.5 В - экономия энергии
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* CDDBG=0 - по моему сотекщд signals не расшарены
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*/
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#define L502_SDRAM_SDGCTL (SCTLE | CL_2 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
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@ -56,14 +56,14 @@ uint32_t l502_otp_make_invalid(uint32_t page) {
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return err;
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}
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/* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> BlackFin'a */
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/* Настройка частоты BlackFin'a */
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void l502_setup_pll(void) {
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ADI_SYSCTRL_VALUES sysctl;
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sysctl.uwPllCtl = L502_PLL_CTL;
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bfrom_SysControl(SYSCTRL_WRITE | SYSCTRL_PLLCTL, &sysctl, 0);
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}
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/* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> PLL <EFBFBD> SDRAM <EFBFBD> <20><><EFBFBD><EFBFBD> OTP, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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/* Запись настроек PLL и SDRAM в блок OTP, начиная с заданной страницы */
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uint32_t l502_otp_write_cfg(uint32_t first_page) {
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uint32_t err = bfrom_OtpCommand(OTP_INIT, (0x0A548800 | 133));
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uint64_t val = 0;
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@ -78,7 +78,7 @@ uint32_t l502_otp_write_cfg(uint32_t first_page) {
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| OTP_CHECK_FOR_PREV_WRITE, &val);
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}
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/* <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> */
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/* если была ошибка - делаем недействительным весь блок */
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if (err)
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l502_otp_make_invalid(first_page);
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}
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@ -88,23 +88,23 @@ uint32_t l502_otp_write_cfg(uint32_t first_page) {
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/* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> PLL <EFBFBD> SDRAM <EFBFBD> OTP. <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>,
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<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20> OTP <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> PLL <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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/* Проверяем, есть ли действтиельные настройки PLL и SDRAM в OTP. Если нет,
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то записываем их в OTP и инициализируем PLL вручную */
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void l502_otp_init(void) {
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uint32_t err=0, page, fnd=0, pll_setup=0;
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//err = l502_otp_make_invalid(PBS00);
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/* <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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/* ищем первый действительный блок настройки загрузки */
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for (page = PBS00; !(fnd && !err) && (page < 0xD8); page += 4) {
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uint64_t val;
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err = bfrom_OtpRead(page, OTP_LOWER_HALF, &val);
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if (!err && !((val>>OTP_INVALID_P)&0x3)) {
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fnd = 1;
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if (!val) {
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/* <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> => PLL <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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/* если блок с настройками не был записан => PLL записываем
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вручную и записываем настройки для корректной инициализации
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в дальнейшем */
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if (!pll_setup) {
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l502_setup_pll();
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pll_setup = 1;
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@ -112,17 +112,17 @@ void l502_otp_init(void) {
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err = l502_otp_write_cfg(page);
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page+=4;
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if (!err && (page< 0xD8)) {
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/* <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> - <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,
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<EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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/* если есть место - то дописываем вторую копию, чтобы всегда
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быть уверенным, что если даже при первом чтении была ошибка,
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все загрузится нормально */
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err = l502_otp_write_cfg(page);
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}
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}
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}
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}
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/* <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> PLL,
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<EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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/* если все страницы настроек испорчены, то инициализируем PLL,
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так как скорее всего его система не проинициализировала */
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if (!fnd && !pll_setup) {
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l502_setup_pll();
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}
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@ -130,16 +130,16 @@ void l502_otp_init(void) {
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}
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void l502_init(void) {
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/* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> OTP-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20> PLL, <20><><EFBFBD><EFBFBD> <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>
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* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD>. <20><><EFBFBD><EFBFBD> <20> OTP <20><><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><>
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* SDRAM <EFBFBD> PLL <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> BlackFin */
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/* инициализация OTP-памяти и PLL, если эти значения не были уже
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* проинициализированны до этого. Если в OTP уже были нужные значения, то
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* SDRAM и PLL проинициализированы уже загрузочным кодом BlackFin */
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l502_otp_init();
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/* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> SPI */
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/* настройка SPI */
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fpga_spi_init();
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/* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> SPORT0 */
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/* настройки SPORT0 */
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*pSPORT0_TCLKDIV = 0;
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*pSPORT0_RCLKDIV = 0;
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@ -153,17 +153,17 @@ void l502_init(void) {
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*pPORTF_MUX = (*pPORTF_MUX & 0xFFFC) | 1;
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*pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF7;
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/* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> SPORT RX <EFBFBD><EFBFBD> IVG7 */
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/* назначение SPORT RX на IVG7 */
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*pSIC_IAR2 = (*pSIC_IAR2 & 0xFFFFFFF0UL) | P16_IVG(7);
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REGISTER_ISR(7, isr_sport_dma_rx);
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/* SPORT TX <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> IVG9 */
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/* SPORT TX оставляем на IVG9 */
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REGISTER_ISR(9, isr_sport_dma_tx);
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/* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> HostDMA-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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/* настройка HostDMA-интерфейса */
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hdma_init();
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/* <EFBFBD><EFBFBD><EFBFBD><EFBFBD> SDRAM <EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> */
|
||||
/* если SDRAM не настроена, то инициализируем ее */
|
||||
if (*pEBIU_SDSTAT & SDRS) {
|
||||
uint32_t* a=0;
|
||||
*pEBIU_SDRRC = L502_SDRAM_SDRRC;
|
||||
@ -171,12 +171,12 @@ void l502_init(void) {
|
||||
*pEBIU_SDGCTL = L502_SDRAM_SDGCTL;
|
||||
ssync();
|
||||
|
||||
*a = 0; /* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
||||
*a = 0; /* записываем по нулевому адресу произвольное слово, чтобы активировать память */
|
||||
|
||||
while (*pEBIU_SDSTAT & SDRS) {}
|
||||
}
|
||||
|
||||
/* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>/<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
||||
/* инициализируем параметры для потоков ввода/вывода */
|
||||
l502_stream_init();
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user