209 lines
9.2 KiB
C
209 lines
9.2 KiB
C
#ifndef E502_FPGA_REGS_H
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#define E502_FPGA_REGS_H
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//#ifndef L5XX_REGS_H
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//#define L5XX_REGS_H
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#define E502_MAX_PAGES_CNT 252
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#define E502_BF_SDRAM_SIZE (32UL*1024*1024)
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#define E502_BF_MEMADDR_CMD 0xFF800800
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#define E502_BF_CMD_READ 0x0001
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#define E502_BF_CMD_WRITE 0x0002
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#define E502_BF_CMD_HIRQ 0x0004
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#define E502_BF_CMD_HDMA_RST 0x0008
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#define RING_MODE(a) (a << 2)
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// Разрешение синхронного потока цифрового вывода
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#define SYN_DIGOUT_EN (1 << 0)
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//Разрешение синхронного потока ЦАП1
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#define SYN_DAC1_EN (1 << 1)
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//Разрешение синхронного потока ЦАП2
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#define SYN_DAC2_EN (1 << 2)
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#define DCI_TEST_MODE (1)
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#define clk125_fail (1 << 0)
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#define clk125_lock (1 << 1)
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#define slv_clk_pll_fail (1 << 2)
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#define slv_clk_pll_lock (1 << 3)
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#define adcbuf_empty_err (1 << 4)
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#define adcbuf_full_err (1 << 5)
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#define dacbuf_empty_err (1 << 6)
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#define dacbuf_full_err (1 << 7)
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#define gd32_sdio_crc_err (1 << 8)
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#define dac_buf_chan_extra_err (1 << 9)
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#define dac_buf_chan_extra_err1 (1 << 10)
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#define dacbuf_rst_done_err (1 << 11)
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#define adcbuf_rst_done_err (1 << 12)
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#define ch_sdio_size_req_err (1 << 14)
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#define gd_sdio_size_req_err (1 << 15)
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#define ch32_sdio_crc_err (1 << 16)
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/********************* Адреса регистров блока ARM_INTERFACE *******************/
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#define E502_REGS_ARM_BLOCK 0x0100
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#define E502_REGS_ARM_DMA (E502_REGS_ARM_BLOCK+0)
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#define E502_REGS_ARM_FPGA_ERR (E502_REGS_ARM_BLOCK+1)
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#define E502_REGS_ARM_DAC_ERR (E502_REGS_ARM_BLOCK+3)
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#define DIGOUT_ERROR (1 << 0)
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#define DAC1_ERROR (1 << 2)
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#define DAC2_ERROR (1 << 4)
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#define E502_REGS_ARM_VERSION (E502_REGS_ARM_BLOCK + 2)
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#define E502_REGS_ARM_HARD_ID (E502_REGS_ARM_BLOCK + 0xA)
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#define E502_REGS_ARM_DEBUG_REG (E502_REGS_ARM_BLOCK + 0xB)
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#define E502_REGS_ARM_DAC_CH_EN (E502_REGS_ARM_BLOCK + 0xD)
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#define E502_REGS_ARM_TIME_CTRL (E502_REGS_ARM_BLOCK + 0x10)
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#define E502_REGS_ARM_TIME_SEC (E502_REGS_ARM_BLOCK + 0x11)
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#define E502_REGS_ARM_TIME_SSEC (E502_REGS_ARM_BLOCK + 0x12)
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#define E502_REGS_ARM_TIME_ADJ (E502_REGS_ARM_BLOCK + 0x13)
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#define E502_REGS_ARM_FLASHSIZE (E502_REGS_ARM_BLOCK + 0x14)
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/********************* Адреса регистров блока IOHARD **************************/
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#define E502_REGS_IOHARD_BLOCK 0x0200
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//Адрес Control Table
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#define E502_REGS_IOHARD_LTABLE (E502_REGS_IOHARD_BLOCK+0)
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#define E502_REGS_IOHARD_LTABLE_MAX_SIZE 0x100 // Максимальный размер Control Table
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#define E502_REGS_IOHARD_LCH_CNT (E502_REGS_IOHARD_BLOCK+0x100)
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#define E502_REGS_IOHARD_ADC_FREQ_DIV (E502_REGS_IOHARD_BLOCK+0x102)
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#define E502_REGS_IOHARD_ADC_FRAME_DELAY (E502_REGS_IOHARD_BLOCK+0x104)
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#define E502_REGS_IOHARD_DIGIN_FREQ_DIV (E502_REGS_IOHARD_BLOCK+0x106)
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#define E502_REGS_IOHARD_IO_MODE (E502_REGS_IOHARD_BLOCK+0x108)
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#define E502_REGS_IOHARD_GO_SYNC_IO (E502_REGS_IOHARD_BLOCK+0x10A)
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#define E502_REGS_IOHARD_PRELOAD_ADC (E502_REGS_IOHARD_BLOCK+0x10C)
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#define E502_REGS_IOHARD_DAC_FLUSH (E502_REGS_IOHARD_BLOCK+0x110)
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#define E502_REGS_IOHARD_ASYNC_OUT (E502_REGS_IOHARD_BLOCK+0x112)
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#define E502_REGS_IOHARD_LED (E502_REGS_IOHARD_BLOCK+0x114)
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#define E502_REGS_IOHARD_DIGIN_PULLUP (E502_REGS_IOHARD_BLOCK+0x116)
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#define E502_REGS_IOHARD_OUTSWAP_BFCTL (E502_REGS_IOHARD_BLOCK+0x118)
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#define E502_REGS_IOHARD_OUTSWAP_ERROR (E502_REGS_IOHARD_BLOCK+0x120)
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/********************* Адреса регистров блока IOARITH **************************/
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#define E502_REGS_IOARITH_BLOCK 0x0400
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#define E502_REGS_IOARITH_B10 E502_REGS_IOARITH_BLOCK
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#define E502_REGS_IOARITH_B5 (E502_REGS_IOARITH_BLOCK+0x01)
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#define E502_REGS_IOARITH_B2 (E502_REGS_IOARITH_BLOCK+0x02)
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#define E502_REGS_IOARITH_B1 (E502_REGS_IOARITH_BLOCK+0x03)
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#define E502_REGS_IOARITH_B05 (E502_REGS_IOARITH_BLOCK+0x04)
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#define E502_REGS_IOARITH_B02 (E502_REGS_IOARITH_BLOCK+0x05)
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#define E502_REGS_IOARITH_K10 (E502_REGS_IOARITH_BLOCK+0x08)
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#define E502_REGS_IOARITH_K5 (E502_REGS_IOARITH_BLOCK+0x09)
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#define E502_REGS_IOARITH_K2 (E502_REGS_IOARITH_BLOCK+0x0A)
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#define E502_REGS_IOARITH_K1 (E502_REGS_IOARITH_BLOCK+0x0B)
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#define E502_REGS_IOARITH_K05 (E502_REGS_IOARITH_BLOCK+0x0C)
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#define E502_REGS_IOARITH_K02 (E502_REGS_IOARITH_BLOCK+0x0D)
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#define E502_REGS_IOARITH_ADC_FREQ_DIV (E502_REGS_IOARITH_BLOCK+0x12)
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#define E502_REGS_IOARITH_THRESHOLD (E502_REGS_IOARITH_BLOCK+0x15)
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#define E502_REGS_IOARITH_N_CHAN_SYN (E502_REGS_IOARITH_BLOCK+0x16)
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#define E502_REGS_IOARITH_IN_STREAM_ENABLE (E502_REGS_IOARITH_BLOCK+0x19)
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#define E502_REGS_IOARITH_DIN_ASYNC (E502_REGS_IOARITH_BLOCK+0x1A)
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/********************* Адреса регистров блока CMD **************************/
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#define E502_REGS_CMD_BLOCK 0x0600
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/********************* Адреса регистров блока управления BlackFin'ом **********/
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#define E502_REGS_BF_CTL_BLOCK 0
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#define E502_REGS_BF_CTL (E502_REGS_BF_CTL_BLOCK+0)
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#define E502_REGS_BF_CMD (E502_REGS_BF_CTL_BLOCK+1)
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#define E502_REGS_BF_STATUS (E502_REGS_BF_CTL_BLOCK+2)
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#define E502_REGS_BF_IRQ (E502_REGS_BF_CTL_BLOCK+3)
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#define E502_REGS_BF_IRQ_EN (E502_REGS_BF_CTL_BLOCK+4)
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#define E502_REGS_BF_REQ_ADDR (E502_REGS_BF_CTL_BLOCK+5)
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#define E502_REGS_BF_REQ_SIZE (E502_REGS_BF_CTL_BLOCK+6)
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#define E502_REGS_BF_REQ_DATA (E502_REGS_BF_CTL_BLOCK+128)
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#define E502_BF_REQ_DATA_SIZE_MAX 128
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#define E502_BF_REQ_DATA_SIZE_MIN 8
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/********************* Адреса служебных регистров контроллера **************************/
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#define E502_REGS_ARM_SRV_BLOCK 0x0700
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#define E502_REGS_ARM_CH_UID (E502_REGS_ARM_SRV_BLOCK + 0)
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#define E502_REGS_ARM_GD_UID (E502_REGS_ARM_CH_UID + 3)
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#define E502_REGS_PTP_LOCK_LIMIT (E502_REGS_ARM_GD_UID + 3)
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#define E502_REGS_PINS_DEVID (E502_REGS_PTP_LOCK_LIMIT + 1)
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/* описание отдельных битов регистров */
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#define E502_REGBIT_ARM_DMA_ADC_BUF_CLR_Pos 0
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#define E502_REGBIT_ARM_DMA_ADC_BUF_CLR_Msk (1UL << E502_REGBIT_ARM_DMA_ADC_BUF_CLR_Pos)
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#define E502_REGBIT_ARM_DMA_DAC_BUF_CLR_Pos 1
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#define E502_REGBIT_ARM_DMA_DAC_BUF_CLR_Msk (1UL << E502_REGBIT_ARM_DMA_DAC_BUF_CLR_Pos)
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#define E502_REGBIT_ARM_DMA_RING_MODE_Pos 2
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#define E502_REGBIT_ARM_DMA_RING_MODE_Msk (1UL << E502_REGBIT_ARM_DMA_RING_MODE_Pos)
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#define E502_REGBIT_BF_STATUS_HWAIT_Pos 0
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#define E502_REGBIT_BF_STATUS_HWAIT_Msk (1UL << E502_REGBIT_BF_STATUS_HWAIT_Pos)
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#define E502_REGBIT_BF_STATUS_BUSY_Pos 1
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#define E502_REGBIT_BF_STATUS_BUSY_Msk (1UL << E502_REGBIT_BF_STATUS_BUSY_Pos)
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#define E502_REGBIT_BF_CTL_BF_RESET_Pos 1
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#define E502_REGBIT_BF_CTL_BF_RESET_Msk (0x1UL << E502_REGBIT_BF_CTL_BF_RESET_Pos)
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#define E502_REGBIT_BF_CTL_HOST_WAIT_Pos 3
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#define E502_REGBIT_BF_CTL_HOST_WAIT_Msk (0x1UL << E502_REGBIT_BF_CTL_HOST_WAIT_Pos)
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#define E502_REGBIT_BF_CTL_DSP_MODE_Pos 4
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#define E502_REGBIT_BF_CTL_DSP_MODE_Msk (0x1UL << E502_REGBIT_BF_CTL_DSP_MODE_Pos)
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#define E502_REGBIT_BF_CTL_DBG_MODE_Pos 5
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#define E502_REGBIT_BF_CTL_DBG_MODE_Msk (0x1UL << E502_REGBIT_BF_CTL_DBG_MODE_Pos)
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#define E502_REGBIT_BF_CTL_CLK_DIV_Pos 8
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#define E502_REGBIT_BF_CTL_CLK_DIV_Msk (0xFUL << E502_REGBIT_BF_CTL_CLK_DIV_Pos)
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#define E502_REGBIT_ADC_SLV_CLK_LOCK_Pos 31
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#define E502_REGBIT_ADC_SLV_CLK_LOCK_Msk (0x1UL << E502_REGBIT_ADC_SLV_CLK_LOCK_Pos)
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#define E502_REGBIT_IOHARD_OUT_SWAP_Pos 0
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#define E502_REGBIT_IOHARD_OUT_SWAP_Msk (0x1UL << E502_REGBIT_IOHARD_OUT_SWAP_Pos)
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#define E502_REGBIT_IOHARD_OUT_TFS_EN_Pos 1
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#define E502_REGBIT_IOHARD_OUT_TFS_EN_Msk (0x1UL << E502_REGBIT_IOHARD_OUT_TFS_EN_Pos)
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#define E502_REGBIT_IOHARD_OUT_RING_Pos 2
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#define E502_REGBIT_IOHARD_OUT_RING_Msk (0x1UL << E502_REGBIT_IOHARD_OUT_RING_Pos)
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#define E502_REGBIT_IOHARD_OUT_RFS_EN_Pos 3
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#define E502_REGBIT_IOHARD_OUT_RFS_EN_Msk (0x1UL << E502_REGBIT_IOHARD_OUT_RFS_EN_Pos)
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#define E502_REGBIT_DMA_IRQ_STEP_Msk(ch) (1UL << ch)
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#define E502_REGBIT_DMA_IRQ_PAGE_Msk(ch) (1UL << (ch+8))
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#define E502_REGBIT_DMA_IRQ_FLUSH_Msk(ch) (1UL << (ch+16))
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//#endif // L5XX_REGS_H
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#endif // E502_FPGA_REGS_H
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